Change 4e0e3c990d caused
a regression in that SPI_MCUX_FLEXCOMM_TX DMA
transfers weren't properly set to be a peripheral
transfer.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The syntax was wrong for the chosen dtcm node. Also fixing build error
on 1180 by re-allowing the symbol on some tests.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fix an out of bounds access found by ASan.
Also remove mock_i2c_reg_error which seems to never be read.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Fix issues found by ASan, log register writes for inspection using
console harness.
Fixes: 5f84be617e
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
There will be an compilation error if there is no interrupt GPIO defined
in the device tree file, as parts of the config and data structs
have #if that depends on the presence of interrupt GPIO.
Use the same #if constructs also on the functions that use those
structs.
Signed-off-by: Jonas Berg <jonas.s.t.berg@gmail.com>
The sleep output configuration should be skipped for pins
22 to 28.
This was causing incorrect GPIO wakeups when entering
standby mode on RW612.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Reduce the spinlock scope in stepper_handle_timing_signal
2. perform a step each time the timing signal is called
3. Increment/Decrement actual_position and steps using atomics
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The counter that is used in Power Mode 3 to track System time could
overflow for large timeouts.
Add an API that the power system could use to ignore wakeup events
from the timer.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The MAC addressed derived from the device ID is not assigned by the
manufacturer and therefor the Locally Administered Address (LAA) bit should
be set.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add support for the interrupt-driven API. Interrupts are
emulated using a polling thread.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
It is now possible to enable CONFIG_UART_INTERRUPT_DRIVEN for mspm0
uart driver.
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
When BT dedicated API was turning off the HF clock it was not resetting
status flags. When onoff API was attempting to request HF clock after
that it was detecting unexpected state as status flag was indicating
as if HF clock was on.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The ADC driver API already supports ADC readings which can return signed
values, these are differential readings. In Nordic's datasheet, we have
a mode called "single ended", but its just a name. "Single ended" is a
differential reading, with the negative channel tied to GND. This is not
compatible with zephyrs definition of a single ended reading.
To support Nordic's "single ended" mode, the user must configure
a differential reading, with the negative input tied to ground, which
the saadc driver can then use to configure the reading as Nordic SAADC
"single ended", and return negative values as expected.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Updated the PLL input frequency calculation to include
division by the HSI clock divider.
Enable HSI divider using LL_RCC_HSI_EnableDivider().
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Added support for selecting channels A, B, both together, and all channels
on the AD5686 DAC driver. This improves flexibility for multi-channel
DAC applications.
Signed-off-by: Aditya Ganesh <adga5133@colorado.edu>
The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
This change alignes HCI drivers behavior with Host expectation. That is:
if an HCI driver managed to send a packet to Controller, the HCI driver
also unreferences it. If the HCI driver didn't manage to send the
packet to Controller and returns an error code, it does not unreferences
buffer.
This change aligns the behavior of HCI drivers with the Host's
expectations. Specifically:
- If an HCI driver successfully sends a packet to the Controller, the
HCI driver also unreferences it.
- If the HCI driver fails to send the packet to the Controller and
returns an error code, it does not unreference the buffer.
Fixes#94445
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
The stm32u3x header files defines LL_ADC_SINGLE_ENDED but not
LL_ADC_DIFFERENTIAL as the device doesn't support differential mode. The
driver only checked for LL_ADC_SINGLE_ENDED and assumed that when that was
defined, LL_ADC_DIFFERENTIAL would also be defined.
Check for both when figuring out which calibration type will be required.
Signed-off-by: Keith Packard <keithp@keithp.com>
Check if cqe is NULL before accessing cqe->result in
spi_rtio_transceive(). Prevents possible null pointer dereference
from rtio_cqe_consume() return value.
CID: 516229
Fixes: #90547
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Now use the 5-parameter function "PINT_PinInterruptConfig"
deprecated in MCUX SDK, need to add compile definition
'PINT_USE_LEGACY_CALBACK' to make intc_nxp_pint compatible
with updated 'fsl_pint' driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
remove spi_cs_is_gpio checks before
spi_context_cs_control, as it is also done
inside and we don't need to check two times.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The uart_stm32 driver gives no way for a user to
tell if setting a new baud rate was successful.
Propagate error checks up to the API level.
Signed-off-by: Eden Frosst <edenfrosst@gmail.com>
The SAMPLERATE register can be used as a local timer instead
of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set
to Timers, it is sufficient to trigger SAMPLE task only once in order
to start the SAADC and triggering the STOP task will stop sampling.
The SAMPLERATE.CC field controls the sample rate.
The SAMPLERATE timer should not be combined with SCAN mode and
only one channel should be enabled when using the internal timer.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
stm32 smbus driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 sdhc driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 i3c driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dwmac_stm32h7x driver is relying on the pinctrl framework
hence select CONFIG_PINCTRL to ensure proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 mco clock driver is relying on the pinctrl framework
for configuring the MCO pin hence select CONFIG_PINCTRL
to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 crypto driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 ltdc driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 mipi dsi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmipp driver requires a reset control and pinctrl
(depending on the configuration) hence ensure that
CONFIG_RESET and CONFIG_PINCTRL are properly selected to allow
proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Ensure NSBank values are validated at build time.
That helps to identify and fix incorrect bank values.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Simplifies the driver code:
* Use existing FMC_NORSRAM_DEVICE and FMC_NORSRAM_EXTENDED_DEVICE
defines. No need to keep references to them in the driver's config.
* Refine initialization loop.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Add support for the SDMMC clock bypass feature for those SoCs that have
it. This provides a SDMMC bus speed double that of `clk-div = <0>`.
Updated the `clk-div` documentation at the same time to be clearer on
how the bus clock speed is determined.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Explicitly initialise the SDMMC initialisation struct to make it clear
the configuration being applied.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This commit updates I2C_DMA_DATA_INIT() macro to use
IF_ENABLED(DT_INST_DMAS_HAS_NAME(...), (...)),
so that the DMA configuration field is only generated if the
corresponding DMA property exists in the Device Tree.
This prevents macro expansion errors and allows a mix of I2C
peripherals with and without DMA support in the same build.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Define SAI1 node for STM32H7xx series.
Add STM32H7xx related DMA configs.
Enable samples/drivers/i2s/output for nucleo_h745zi_q/m7
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add external interrupt support for Renesas RZ/A3UL, V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
