The HAL2 glue currently works on STM32C5 series but is incomplete.
It will also break upon updating to STM32CubeC5 v2.1.0 because the API
changed a bit (bringing it closer to what existed in HAL1, really).
Plug the holes by implementing missing glue pieces, and removing any use
of the raw HAL1/HAL2 macros, except in udc_stm32_device_speed() for the
sake of simplicity. This ensures the glue works with STM32CubeC5 v2.1.0
and should ensure a series with OTG_HS Just Works, although this latter
claim has not been verified due to no such hardware being available.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Protect the assignment of user_cb and user_data in
uart_stm32_irq_callback_set() using irq_lock() and irq_unlock() to
prevent a race condition where an incoming UART interrupt executes the
new callback with stale user_data.
Fixes#118457
Signed-off-by: Jay Roy <jayroy0304@gmail.com>
Move device specific clock control shell to a common clock control shell
Fix bug in device initialization, add example configuration in yaml
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
Potential fix for pull request finding (second copilot run)
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
Potential fix for pull request finding (second copilot run)
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
Potential fix for pull request finding
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
The driver is based on the linux driver for the same family of devices.
It has the same limitations:
Y1 is always connected to the input clock,
Y2/Y3 is always connected to PLL1 (Y4/Y5-PLL2, Y6/Y7-PLL3, Y8/Y9-PLL4)
In addition it assigns ownership to the first output that requests a PLL.
The vco frequency calculation of the PLL prefers the owner, trying to
provide the best possible result for it. If a second output frequency is
requested a vco frequency based on the least common multiple is calculated
and used, if the "perfect" result for the owner can be achieved. If not,
the second output can only use its divider to get the best possible
approximation of its requested rate. Ownership is transferred if the
current owner request a output rate of 0.
The output frequencies can be configured via device tree and changed
during runtime.
A sample has been added to control the driver via a shell.
Assisted-by: Claude:claude-sonnet-5 coccinelle
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
The IW416 and IW61X module choices only covered the AzureWave and
Murata modules, so the u-blox and Quectel modules had no way to
be selected from Zephyr.
Signed-off-by: Sanjay Yadav <sanjay.yadav@nxp.com>
NXP_WIFI_COMPRESS_TX_PWTBL was not selectable for IW416, so IW416 kept
using the legacy per-channel TRPC tx power tables. Add NXP_IW416 to the
if block and to its depends on, and give NXP_WIFI_CLOCKSYNC an explicit
depends on so it stays disabled for IW416.
Also drop the NXP_IW416_REGION and NXP_IW61X_REGION choices. The driver
now selects the region table at runtime from the country code, and one
WW header already carries the WW, JP, US, EU and CA tables, so the
per-region headers are redundant. The header is selected per chip in the
wifi_nxp CMakeLists instead, as RW610 already does.
Signed-off-by: Gaofeng Zhang <gaofeng.zhang@nxp.com>
Add a locking to synchronize fetch with the actual sample fetching, on
by default as that's the API contract, but leave an option to turn it
off if needed, noting that that's not the normal API behavior.
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The current rts sample_fetch() implementation has a sleep loop up to
50ms to wait for the most recent sample, this can be problematic if the
function is called from a shared thread, for example from the sysworkq.
The advantage is it guarantees to get a recent sample, but in practice
that's rarely necessary for a fan control loop, and having the most
recent sample is probably good enough, and that's actually how other EC
tachometer drivers are implemented.
Rework the rts5912 tach driver to remove the sample_fetch() sleep
function, instead use the sample_fetch() function to start a sample
fetching asynchronously and let channel_get() return the most recent
available sample.
Note that the tachometer relies on the system clock, hence it returns
bogus values if the system happens to go into sleep during sampling.
Additionally it returns bogus samples on the first iteration after
waking up (presumably because it was already sampling from a partially
idle clock) and for the next sample as well (no idea why), so add the
necessary guards to keep the system awake during sampling, but also a
function to optionally discard the first two samples.
The discard option is off by default as in the normal use case of this
device the fan is only used while the application processor is on, and
in that condition the EC is normally stopped from entering suspend state
entirely, so it probably won't be needed, but there's no harm leaving
some code to handle that condition if it becomes necessary down the
road.
Note that there's quite few checks on the asynchronous functions to
avoid various potential race conditions between the interrupt and
overflow counter.
Also note, the tach seems to have a "limit" register and interrupt that
seemingly could work in place of timeout, but I wasn't able to make it
work correctly for some reasons.
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The AD559x needs up to 250 us to recover after a reset, per the
datasheet, before it will accept new data on the bus. The driver
previously issued the software reset immediately after de-asserting
reset-gpios, without waiting for this recovery time.
Add a reset-recovery-time-us devicetree property (default 250 us) and
busy-wait for it in mfd_ad559x_init(), after de-asserting reset-gpios
and before the software reset. The delay is only applied when
reset-gpios is present. Boards whose reset line needs extra settling
time can increase the property to match their hardware.
Tested on an STM32 Nucleo-H563ZI paired with a MikroElektronika ADAC
Click board (AD5593R). The click board's RESET pull-up was replaced
with a pull-down so RESET is guaranteed low until the MCU drives it
high, matching what the driver assumes.
A Saleae logic analyzer captured RESET and I2C activity at startup
to measure the delay between RESET going high and the first I2C
transaction. A test application swept reset-recovery-time-us across
several values: with the delay set to 0, the software reset write in
mfd_ad559x_init() failed and device_is_ready() returned false,
logging "AD559x device is not ready". With the datasheet's 250 us
default restored, init and the following I2C traffic succeeded
reliably. The reset-recovery delay is applied in mfd_ad559x_init()
before the bus-specific init, so this exercises the same code path
used by the SPI variant.
Signed-off-by: Esben Dueholm Nørgaard <esbendn@tutanota.com>
Assisted-by: Claude:claude-opus-4.8
smsc_write_tx_fifo() pads the last fragment up to a DWORD and copies
whole words out of the staging buffer, so a frame whose length is not a
multiple of four reads up to three bytes past the end of tx_buf. A
1514 byte frame, the largest one accepted, reads two bytes too far.
Size the buffer to the padded length instead.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
eth_tx() read net_pkt_get_len(pkt) bytes into a fixed
NET_ETH_MAX_FRAME_SIZE staging buffer without checking the length.
net_pkt_read() takes no destination size, so a packet larger than the
buffer overwrites memory behind it. The interface MTU is not bounded by
what the link can transmit (an IPv6 RA MTU option raises it up to 0xffff),
which makes such packets reachable from the network.
Drop oversized frames before any TX_DATA_PORT write, so the TX FIFO is
not left holding a command word without its payload.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
On newer STM32 families (STM32U5, STM32H5, STM32N6, STM32MP1, STM32MP2,
STM32L5, STM32G4), the Flexible Memory Controller (FMC) features a
2-bit DATAHLD[1:0] field in FMC_BTRx and FMC_BWTRx registers to
configure data-hold cycles for asynchronous read and write accesses.
Currently, memc_stm32_nor_psram.c skips initializing .DataHoldTime in
both normal and extended timing configurations, forcing the field to
0 cycles and causing timing violations on external devices requiring
non-zero data hold duration (such as parallel display controllers).
Older FMC v1 controllers (STM32F4, STM32F7, STM32H7) lack DATAHLD
bits entirely and their HAL timing structs omit the DataHoldTime
member.
Add optional Devicetree properties st,data-hold-cycles and
st,data-hold-cycles-ext to st,stm32-fmc-nor-psram binding without a
YAML default to prevent generating existence flags on unsupported
targets.
In memc_stm32_nor_psram.c, conditionally populate DataHoldTime when
FMC_BTRx_DATAHLD_Pos or FMC_BTR1_DATAHLD_Pos is defined, and add
compile-time assertions to prevent misconfiguration on legacy SoCs.
Fixes#118296
Signed-off-by: Priyanshu Singh <singhpriyanshu9838@gmail.com>
Add the PSOC4000T-specific peripheral clock divider handling
needed for the new SoC series.
Signed-off-by: Yurii Lozynskyi <Yurii.Lozynskyi-EE@infineon.com>
Enabling CONFIG_BT restricts SYSTEM_WORKQUEUE_PRIORITY to the
cooperative range for every build, but the requirement comes from the
individual components that submit work to the system workqueue, not
from Bluetooth being enabled.
An application that asks for a preemptible system workqueue therefore
cannot build with Bluetooth enabled at all, even when no Bluetooth
code uses that queue. Running the system workqueue below every other
thread is a common way to service a watchdog only while the whole
system is still making progress.
Add BT_SYSTEM_WORKQUEUE_COOP and apply the range only when it is set.
The components that need the system workqueue to stay cooperative
select the option themselves, so the requirement is recorded next to
the code that has it and a new work item cannot slip past it: the
host stack, the H:5 and STM32WB0 drivers, the NXP wake-on-BT LED
blink option, and BT_CTLR_PRIVACY when the split link layer builds
ull_filter.c.
Mesh, Audio and the other Host users need the Host, so they are
covered by its select; they get their own when the Host drops it.
No in-tree configuration changes behavior: SYSTEM_WORKQUEUE_PRIORITY
already defaults to -1, and no Bluetooth test or sample overrides it.
Signed-off-by: Wai-Hong Tam <waihong@google.com>
The init sequence parser copied only the first parameter byte into
a local variable but passed the full parameter size to
mipi_dsi_dcs_write(), sending stack garbage for every multi-byte
command such as the column and page address setup. Pass the
parameter bytes straight from the command table.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a Kconfig choice for the station power save mode applied
when the driver starts: minimum modem sleep, maximum modem
sleep or none. The default keeps the current behaviour, where
the Wi-Fi library starts in minimum modem sleep. The mode can
still be changed at runtime through the Wi-Fi power save
management request.
Assisted-by: Claude:fable-5.1
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When driving all columns (INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) or masking
direct port writes, gpio_kbd_matrix_drive_column() uses
BIT_MASK(common->col_size). Because col-gpios supports up to 32 pins,
col_size can be 32, which expands to (1UL << 32) - 1UL. On 32-bit
architectures where unsigned long is 32 bits wide, shifting by 32 is
undefined behavior and evaluates to 0 on x86, leaving all columns
undriven in idle mode.
Use BIT64_MASK(common->col_size) to safely compute the mask for up to
32 columns.
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
In input_kbd_matrix_update_state(), the linear key index cyc_idx into
the scan_cycle_idx array is stored in a uint8_t variable. When the
matrix has more than 256 keys (for example, 16 rows with 17 or more
columns when CONFIG_INPUT_KBD_MATRIX_16_BIT_ROW is enabled), cyc_idx
overflows and wraps modulo 256, corrupting per-key debounce tracking.
Change cyc_idx to uint16_t to support the full range of row_size *
col_size combinations.
Assisted-by: Gemini:gemini-3.1-pro
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The SFDP configuration path programmed ERASE_SECTOR/ERASE_BLOCK with the
classic 0x20/0xD8 opcodes and strode range erases by an assumed 64 KiB
block size, regardless of what the flash declares. On parts whose block
erase is larger (e.g. the ISSI IS25WX01G declares 128 KiB for 0xD8),
each block-erase step wipes 64 KiB more than the loop accounts for,
erasing past the end of the requested range.
Select the erase opcodes from the BFP erase types (DW8-DW9) instead: the
type matching the driver's 4 KiB sector size for ERASE_SECTOR, and the
largest declared type for ERASE_BLOCK, with the block erase stride taken
from that type's actual size. Erase types beyond the advertised BFP
table length are skipped, as are types declaring a nonsensical size.
Vendor-specific and default LUT paths keep the 64 KiB assumption they
hard-code today.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
nrf_clock_calibration.c declares the clock_control log module, which
only clock_control_nrf.c registers. With the split clock drivers
CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION is still set while that file
is not built, so under CONFIG_NO_OPTIMIZATIONS the module pointer
survives and the link fails on log_const_clock_control. Declare
clock_control_lfclk in that case, reusing the CONFIG_CLOCK_CONTROL_NRF
condition already used for the nrfx header.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
BIT() overflows for pins >= 32, so pio_sm_set_pins_with_mask() and
pio_sm_set_pindirs_with_mask() cannot express them. Use the 64-bit
variants, which are equivalent below GP32.
Assisted-by: Claude:claude-opus-5
Signed-off-by: John Goble <john.goble@nimbusdigital.com>
RP2350 PIO addresses a 32-pin window selected by GPIOBASE, which the
driver never writes, so PIO is limited to GP0-GP31. Add a gpio-base
property so a board can select the upper window and reach GP32-GP47 on
packages that have those pins.
GPIOBASE must be set before a program is loaded, so it is applied in
this driver's init.
Tested on an RP2350B with pio1 at gpio-base 16 driving a PIO UART on
GP37/GP39.
Assisted-by: Claude:claude-opus-5
Signed-off-by: John Goble <john.goble@nimbusdigital.com>
The SDO pin (previously known as MOSI) of the STM32 SPI controller is
floating when the SPI is idle. As we use a pull-up on that pin (it is
used as a multi-function pin), this causes an idle-high voltage
on the SDO pin. We use the SDO pin for control of WS2812 LEDs, and they
require an idle-low voltage.
Add a devicetree setting 'st,gpio-control' so the SPI controller keeps
control of the SDO pin also between transmissions.
This enables the AFCNTR bit in the STM32 SPI controller, via the
LL_SPI_EnableGPIOControl() HAL function.
The functionality is available for SPI in STM32H7, STM32H5, STM32C5
and some other series: all that rely on "st,stm32h7-spi"
DT compatible ID.
Tested on STM32H562.
Signed-off-by: Jonas Berg <jonas.berg@voiapp.io>
Add an ifx_cat1_spi_deinit() implementation and register it via
SPI_DEVICE_DT_INST_DEINIT_DEFINE so device_deinit(dev) succeeds on the
Infineon PSE84 / CAT1 SCB SPI driver. Without this hook the upstream
tests/drivers/spi/spi_loopback test_spi_deinit case returns -ENOTSUP and
skips.
The deinit:
- returns -EBUSY while a transfer is still in flight, to avoid tearing
down the SCB block in the middle of a transaction. The busy check is
consolidated into ifx_cat1_spi_is_busy(), which reports busy while the
SPI context still holds outstanding tx/rx buffers
(spi_context_tx_on()/spi_context_rx_on()), while Cy_SCB_SPI_IsBusBusy()
is active, or while an async transfer is still pending. The large-chunk
DMA path drives the transfer purely through the DMA channels without
setting data->pending, and Cy_SCB_SPI_IsBusBusy() can read idle between
FIFO-paced DMA bursts, so the SPI context buffer state is used as the
authoritative in-flight indicator that covers both the FIFO and DMA
paths for synchronous and asynchronous transfers,
- unregisters the deep-sleep SysPm callback (only when CONFIG_PM=y),
- disables the SCB IRQ and the SCB SPI block (Cy_SCB_SPI_Disable),
- stops the rx and tx DMA channels via the shared ifx_cat1_spi_dma_stop()
helper, also used by ifx_cat1_spi_release() (only when
CONFIG_SPI_INFINEON_DMA=y),
- deinits the SCB SPI block last with Cy_SCB_SPI_DeInit(), then clears the
cached SPI config so the next transceive after device_init() takes the
full reconfigure path instead of being short-circuited by
spi_context_configured().
The DMA channels are stopped before the SCB is deinitialized so the SCB
teardown is the last hardware step, and the rx/tx dma_stop sequence is
factored into ifx_cat1_spi_dma_stop() rather than duplicated between the
deinit and release paths.
The deinit function and its reference in the device definition are
guarded by CONFIG_DEVICE_DEINIT_SUPPORT, matching the pattern used by
drivers/spi/spi_nrfx_spim.c and drivers/spi/spi_bflb.c.
Also drop the unused dma_configured field from struct ifx_cat1_spi_data:
it was never read and never set to true anywhere in the driver.
Verified on kit_pse84_eval/pse846gps2dbzc4a/m55:
- [spi_loopback.test_spi_deinit] PASS
- [spi_loopback.test_spi_deinit_busy] PASS (device_deinit() returns
-EBUSY while an 8192-byte DMA transfer is in flight, then succeeds
and re-inits once the bus is idle)
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
The STM32 RCC applies a kernel clock source selection from
clock_control_on() now, so stop inspecting struct stm32_pclken to pick
between on() and configure() and enable every clocks entry the same way
in the HAL driver and in the DWC MAC glue.
Built for nucleo_h743zi with both drivers.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Peripherals whose clocks property mixes bus gates with a kernel clock
source selection have to inspect the ST-private struct stm32_pclken to
decide between clock_control_on() and clock_control_configure() for
each entry. Let on() apply a source selection entry itself instead of
rejecting it with -ENOTSUP, so that a consumer can enable every clocks
entry the same way without knowing the cell encoding. off() keeps
rejecting such entries.
Built for nucleo_h743zi, nucleo_f767zi, stm32h573i_dk and
stm32mp135f_dk.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
No need to check the compatible of the nor-flash-controller
connected as a child node of the mspi controller.
Several compatible are possible, including "zephyr,emul-device-mspi"
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the write operation in MemoryMapped mode.
This depends on the permission bit of the xip-config and on the cmd sent
Write in MemoryMapped mode with MSPI_TX only for MSPI_NOR_CMD_PP_xxx
Factorize the read/write operation in Memory Mapped mode
like the mspi_stm32_xspi driver does.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add UART_NS16550_VARIANT_NS16450 to run the controller with FIFOs
disabled. This is for hardware whose FIFO-mode receive interrupts do
not work: on the C-DAC THEJAS32, neither the receive trigger level nor
the character timeout ever raises an interrupt, so received data sits
in the FIFO unnoticed. In 16450 mode the received data available
interrupt is raised for every character.
The FIFO detection already present in the driver handles the rest: with
FIFOs disabled the IIR FIFO-enabled bits read back zero and the FIFO
size is treated as one byte.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Add a GPIO driver for the two 16-pin GPIO controllers on the C-DAC
THEJAS32 SoC. Pin data is accessed through address masking, where bits
[17:2] of the address select the pins a data access operates on, so
individual pins are set and cleared without read-modify-write. The
direction register sits above the data window at offset 0x40000.
The controllers have no pull resistors and pin interrupts are not yet
wired to the SoC interrupt controller, so both are reported as
unsupported.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Add a driver for the C-DAC THEJAS32 interrupt controller. It is a simple
second-level aggregator that ORs the SoC peripheral interrupt sources
into the RISC-V machine external interrupt line. Unlike a RISC-V PLIC it
has no per-source priority and no claim/complete protocol: it exposes a
single enable bitmask and a single (enabled and pending) status bitmask,
and a source is cleared by servicing the peripheral that raised it.
The driver registers as a second-level interrupt aggregator and exposes
enable/disable/is-enabled helpers for the SoC interrupt-management code
to route level-2 interrupts to.
Register definitions were derived from the open-source Taurus SDK
(https://github.com/rnayabed/taurus).
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Add a driver for the WIZnet W5100S standalone 10/100 Ethernet
controller with an SPI interface. The driver uses socket 0 in MACRAW
mode as the raw Ethernet MAC for the Zephyr networking stack.
The W5100S uses a flat register map with an opcode-first SPI frame and
supports N-byte burst read and write operations. Read link state from
PHYSR0 and program the source MAC after unlocking NETLCKR.
Add the concrete binding on top of the shared WIZnet Ethernet helper,
wire the build, extend build_all SPI coverage, and add the release note
entry for the new compatible.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
A failed read leaves its destination untouched, and every caller used
the value anyway. Check the reads and stop instead.
- wiznet_command(): S0_CR, the poll exit condition
- wiznet_tx(): S0_TX_WR, the TX ring offset
- wiznet_rx(): S0_RX_RSR and S0_RX_RD, the RX ring pointer, and the
frame body, which frees the packet it had already allocated
- wiznet_check_for_ir(): S0_IR, written back to clear the interrupt.
Reports no interrupt, so the poll thread checks the link instead
- wiznet_set_config(): S0_MR, written back to toggle MAC filtering
- w5500_init() and w6100_init(): RTR
- w6100_clear_pending(): SLIR, written back to clear the interrupt
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
The reset and interrupt lines come from the devicetree, so a build that
declares either needs the GPIO driver. Only the W6300 asked for it, and
it asked unconditionally.
Take GPIO on each controller when its own compatible carries one of the
two properties. The W6100 and the W6300 mark int-gpios required, so for
those the condition always holds.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
The WIZnet drivers carried identical thread, timeout and period options
under a per-chip prefix. Replace them with one ETH_WIZNET_ set.
The per-instance config then no longer needs to carry those values, so
read them where they are used and drop them from the device macro.
Only the reset timings stay in the struct, since those differ per chip.
Guard the shared options with ETH_WIZNET, which every driver in this
directory takes, rather than a list of the drivers that has to grow with
each new chip. ETH_WIZNET_CORE stays for the shared implementation,
which the W6300 does not use.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
Move the W6100 driver onto the shared MACRAW core and describe the
register and interrupt differences through the per-chip tables. The
build_all SPI overlay now covers the W6100 path.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
Add a shared MACRAW framework for the WIZnet standalone Ethernet
controllers and move the W5500 driver onto it.
The shared layer keeps the packet path and common control flow in one
place while the chip driver supplies the SPI framing and register layout.
This reduces the duplicated W5500-specific code without changing the
observable behavior of the driver.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
Move the existing W5500, W6100, and W6300 drivers under
`drivers/ethernet/wiznet` and route the parent Kconfig and CMakeLists.txt
through a vendor subdirectory.
Fold the per-chip Kconfig fragments into a single `wiznet/Kconfig` file so
the subtree matches the layout used by other vendor directories under
`drivers/ethernet`.
No functional change is intended.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
install_timeout() derives the window value by subtracting the lower
window bound from the timeout, both unsigned, so a config with
window.min above window.max underflowed into a huge window value instead
of being rejected. Validate the window before converting it.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
install_timeout() only stored the callback inside the branch taken for a
non-NULL one, so installing a timeout without a callback after a
disable() silently kept the previously installed one, and a caller that
deliberately drops its callback would still be called back. Assign it
unconditionally and turn the unsupported combination into an early
return.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
install_timeout() only stored the callback when a non-NULL one was
passed, so installing a timeout without a callback silently kept the
previously installed one, and a caller that deliberately drops its
callback would still be called back. Assign it unconditionally.
The same condition also compared cfg->window.min >= 0 on an unsigned
field, which is always true; drop it.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Currently only i.MX RT1189 had PTP NETC clock div set to 1.
But all RT118x devices need to have this for PTP to work properly.
Fixed by replacing condition with: CONFIG_SOC_SERIES_IMXRT118X
Signed-off-by: Youri Tils <youri.tils@nxp.com>
The EG915U was the only Quectel part in vendor_modem_cellular without a
set_baudrate script, so it was stuck at the devicetree current-speed.
Add one, following cellular_quectel_bg9x.c.
AT+IPR takes effect immediately and is saved only by AT&W, which the
driver does not issue, so the change does not outlive a reset and the
devicetree speed stays authoritative. The AT manual also notes the rate
cannot be changed once multiplexing is up, which is why the script has
to run before the init script opens CMUX.
Tested on an EG915U at 460800, a documented rate for the part: CMUX and
PPP come up, L4 connects, ping is unchanged, and no UART or CMUX errors
are seen.
Assisted-by: Claude:claude-opus-5
Signed-off-by: John Goble <john.goble@nimbusdigital.com>
The XSPI driver takes its DMA receive buffer from the system heap with
k_aligned_alloc(), so MSPI_DMA=y failed to link unless the application
sized HEAP_MEM_POOL_SIZE itself. Declare it on the driver and drop the
copies the STM32 test and sample confs carried.
Built tests/drivers/mspi/flash and samples/drivers/mspi/mspi_flash for
stm32h573i_dk and stm32l496g_disco; not run on hardware.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
DWC Ethernet QoS cores from version 5.00 on can signal MDIO transaction
completion with a MAC interrupt. As it is optional in the IP
configuration, use it only if MDIOIE sticks after enabling it and poll
the busy bit otherwise.
Tested on frdm_mcxe31b, which supports the MDIO completion interrupt.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Replaced SOC dependent kconfigs CONFIG_SOC_SERIES_NRF54H,
CONFIG_SOC_SERIES_NRF92 with feature oriented
CONFIG_HAS_MULTI_OPTION_CLOCKS, in clock related drivers.
Signed-off-by: Michal Frankiewicz <michal.frankiewicz@nordicsemi.no>
