drivers: mdio: fix typo in macro name
s/SOC_SERIES_STM32F1X/CONFIG_SOC_SERIES_STM32F1X/ Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
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1 changed files with 3 additions and 3 deletions
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@ -99,7 +99,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth)
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tmpreg1 &= ETH_MACMIIAR_CR_MASK;
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/* Set CR bits depending on CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC value */
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#ifdef SOC_SERIES_STM32F1X
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) &&
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(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) {
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/* CSR Clock Range between 20-35 MHz */
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@ -112,7 +112,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth)
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/* CSR Clock Range between 60-72 MHz */
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tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
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}
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#else /* SOC_SERIES_STM32F2X */
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#else /* CONFIG_SOC_SERIES_STM32F2X */
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if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) &&
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(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) {
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/* CSR Clock Range between 20-35 MHz */
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@ -129,7 +129,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth)
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/* CSR Clock Range between 100-120 MHz */
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tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
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}
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#endif /* SOC_SERIES_STM32F2X */
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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(heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
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