currently adi_tmc5xxx_common.h and adi_tmc_reg.h are placed
directly in the adi_tmc folder, however placing them in a
common folder and adding to the include directories results
in the drivers not having to include these files using relative
paths.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Replace a #ifndef directive with a if(!IS_ENABLED()) instrcution
in transceive() function. This change makes later integration of RTIO
support in this function smoother, polluting a bit less this function
with #if based directives.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix a missing braces pair around a conditioned instruction in
STM32 SPI driver. Fix that by aggregating the 2 if() instructions
into a single ANDed one.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct some indentation issues, a few useless line escapes,
double space characters or parentheses pair in STM32 SPI driver.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove bits2byte() helper function than was not always used. Replace it
with a division by BITS_PER_BYTE that is explicit enough.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reorder inclusions of header files to clarify and simplify later changes.
By the way, remove #ifdef CONFIG_SPI_STM32_DMA condition to include
DMA header files as its not required.
Keep zephyr/log.h with use of LOG_MODULE_REGISTER() first since included
local spi_context.h depends on log resources to be defined.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove inclusion of zephyr_arch/cache.h header file from STM32 SPI
driver. This header file is included by zephyr/cache.h if applicable
(e.g. CONFIG_ARCH_CACHE is enabled) and should not be used when
CONFIG_EXTERNAL_CACHE is enabled.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move some code into a new function to prepare for RTIO integration.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Devices which use AIN (COMP, LPCOMP, SAADC) don't use pinctrl to
configure their pins, thus pinctrl can't manage pin retention like
is done for other devices. Thus for now, add manually disabling
pin retention to the drivers.
In the future, we should probably use pinctrl for these inputs
as well, at which point this commit can be reverted.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Replace the pad group integration with directly setting/clearing
pin retention for output pins if required, since the pad group
integration is redundant if the quirky cross domain feature is
managed by the application.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
GPIO pad power domain management is not neccesary if the quirky
cross domain feature is handled at the application level. Replace it
with directly setting/clearing pin retention, as hardware will force
power domains on automatically.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The gpio pad groups are redundant if pin retention is handled per
pin, and the quirky cross domain feature is managed by the
application. Remove it entirely.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Return an error if trying to send data using a suspended UART,
instead of blocking, possibly forever, for a transmission that will never
succeed.
Signed-off-by: Kamil Krzyżanowski <kamnxt@kamnxt.com>
Ensure the device is added to the list only if the ENEC I3C
transaction succeeds.
Adding the device before enabling IBI may cause IBI retry failures
due to the device already being present in the list.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Initial DMA support. DMA supports implementation of SSI IP but using vendor
specific DMA in the wrapper. The setup of the DMA is done in
mspi_dw_vendor_specific.h.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
MSPI slave mode is selected through devicetree using the
op-mode property. Mode selected by SSIISMST bit in the
CTRLR0 register. EXMIF can only be Master (controller).
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Handling of asynchronous transfers uses the system workqueue,
hence they are not available when multithreading is disabled.
Also add missing dependency on multithreading in the
MSPI_DW_HANDLE_FIFOS_IN_SYSTEM_WORKQUEUE Kconfig option.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Implement smbus_stm32_pcall() with packet error correction.
For more information, please see chapter 6.5.6 of the SMBus specification.
https://smbus.org/specs/SMBus_3_1_20180319.pdf
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Add SMBus Block Write-Block Read Process Call API for STM32.
This implementation also supports PEC mode (packet error checking) and is
dependent on PEC support already being supported in-tree.
Signed-off-by: James Growden <jgrowden@tenstorrent.com>
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Use proper settings of clock, data bus width for sama7g54.
Update queue number checking and the macro definition in header file.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add property for selecting the source for GMAC Reference Clock to dts
bindings yaml file.
Choose the source for the GMAC Reference Clock by GMAC_UR register.
Signed-off-by: Tony Han <tony.han@microchip.com>
Replace cache coherence functions:
- SCB_InvalidateDCache_by_Addr() to sys_cache_data_invd_range()
- SCB_CleanDCache_by_Addr() to sys_cache_data_flush_range()
Signed-off-by: Tony Han <tony.han@microchip.com>
Add Himax HM01B0 camera sensor driver.
It depends on I2C and it is required to configure the camera.
Signed-off-by: Antonino Scarpaci <antonino.scarpaci@gmail.com>
Add a new auxdisplay driver for TM1637 7-segment LED displays.
The driver supports:
- 4-digit 7-segment display output
- Decimal point positioning
- Brightness control (0-7 levels)
- Display on/off control
- All digits (0-9)
- Basic cursor positioning
The driver implements the standard AUXDISPLAY API
Signed-off-by: Siratul Islam <sirat4757@gmail.com>
When enabling the DTC (Data Transfer Controller) for the I2S SSIE driver
on Renesas RA8x2 boards, a redundant condition check prevented the
interrupt service routines from entering during data transfer. This
caused the transfer to fail when DTC was active.
This commit removes the unnecessary condition check, allowing the DTC to
operate correctly with I2S SSIE transfers on RA8x2 devices.
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
When performing polling-based data transfer without enabling interrupts,
the current implementation stops transferring as soon as either the TX or
RX buffer becomes NULL. This causes the transfer to stop prematurely,
even if the other direction still has data to send or receive.
This commit fixes the condition so that data transfer continues
as long as one direction (TX or RX) still has data remaining.
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
- add driver for Vishay VEML6046 RGBIR color sensor
- add new compatible "vishay,veml6046"
- support fetch and get sensor subsystem operations
- triggered mode and interrupts are not yet supported
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
One-shot reads through Read-Decode API matches functionality
from Fetch-Get API, but asynchronously.
Streaming mode supporting FIFO Watermark Interrupts. Works for both
Gyro and Accel drivers.
These changes are covered under the build-all test for sensor async
api.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
enables the AHB2 peripheral clocks for SRAM1 and SRAM2
on STM32H7RSX series using LL_AHB2_GRP1_EnableClock.
These clocks are required to access the corresponding SRAM regions
during runtime.
Fixes potential access faults when using SRAM1 and SRAM2.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
