Update "CONFIG_SOC_SAMA7G54" to "CONFIG_SOC_SERIES_SAMA7G5" in "#ifdef"
for more flexible use of the drivers.
Signed-off-by: Tony Han <tony.han@microchip.com>
Instead of manually defining a variable for the compatibles' names, use
the ones that get autogenerated upon build.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of manually defining a variable for the compatible's name, use
the one that gets autogenerated upon build.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of manually defining a variable for the compatible's name, use
the one that gets autogenerated upon build.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On STM32N6, HPDMA1 channels are subject to RIF CID filtering.
Channels reach the driver with no CID claimed (CCIDCFGR reads zero),
and transfers on such channels silently move no data: the transfer
completes and raises a transfer-complete event, but the destination
is untouched. GPDMA1 is unaffected; the vendor isolation API is
documented as HPDMA-only.
Claim CID1 (the CPU compartment) during controller initialization
using the LL isolation accessors, mirroring the vendor HAL's
HAL_DMA_SetIsolationAttributes().
Signed-off-by: Sher Amir Singh Dullat <sheramir51@gmail.com>
Add a new pseudo-driver for USBPHYC instances whose input frequency
selection is configured at RCC level in a `CCIPR` register, as is
the case on STM32H7R/S series for example.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add CONFIG_RTC_EMUL_INIT_DATETIME to optionally seed the emulated
RTC's datetime from the host at driver init.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add a Zephyr mbox driver for the ARM Message Handling Unit v2.
Supports doorbell-only signalling across all hardware channel
windows from a single device instance.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
This PR migrates the MIT-licensed Xen public headers into the
`include/zephyr/xen/public` directory to the zephyr-xenlib module.
Since the xen public headers require GCC extensions,
enable GNU_C_EXTENSIONS along with enabling CONFIG_XEN.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Fix the calculation of CAN_STM32_MAX_FILTER_ID. As this is simply the
maximum number of RX filters available, it should not take the split nature
of the standard (11-bit) filter banks into consideration.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit configures the XSPI memory size and memory type
from the MSPI device configuration using the STM32 HAL APIs.
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
This patch introduces strict __ASSERT parameter validation gates to
the primary configuration read and write handlers within the ECAM
host bridge controller driver.
On platforms mapping multi-bus topologies, passing an out-of-bounds
bus index variable can cause a bit-field overflow and boundary
spillage, shifting overflow bits into upper address coordinates. The
driver then executes memory transactions over unallocated regions
inside the ECAM window, causing the hardware to return dummy data
blocks (0xFFFFFFFF) or leak address spaces silently.
Checking the raw bits before any bitwise shifts or extraction macros
are applied halts out-of-bounds parameter execution at the lowest
hardware choke point without interfering with multi-bus hierarchies
conforming to the PCI Express Specification.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Remove the dedicated xlnx_xuartps driver and consolidate support
into the Cadence UART driver (uart_cdns), as both drivers target
the same underlying Cadence UART IP used by Xilinx platforms.
Update device tree bindings and DTS files to use the Cadence
compatible string on supported platforms, remove obsolete driver
sources, and adjust build system configuration accordingly.
Also update test overlays to reflect the driver consolidation.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The width selectors are matched against the configured data sizes,
which are byte counts, but the word and long constants held enum
style values of three and four. A 32-bit element therefore
selected the 64-bit hardware width and the word width was
unreachable. Use the actual byte counts of four and eight.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- Some of the lut values are missing in the datasheet. In these places,
use UINT8_MAX to denote that this pin does not support being used as
GPIO.
- Tested using blinky sample in beagleconnect_zepto.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
The DMA Pico ISR disables the channel interrupt for the channel that
triggered it. A commonly used pattern is to start another DMA transfer from
inside the callback such as in `i2s_stm32.c` without configuring again by
calling the dma_reload() and dma_start() functions. Previously, the
dma_start() function re-enabled the channel interrupt and started the DMA
transfer whereas dma_reload() set the source and destination addresses and
started the DMA transfer. Calling either function on its own does not
produce the desired effect and calling both starts the DMA transfer twice.
The only remaining option would be to call dma_config() for every
transmission which is wasteful. This change brings the RPi Pico DMA API
functionally closer in line with the STM32 DMA API allowing dma_reload()
followed by dma_start() to correctly restart a DMA transfer with a
different source/destination address and enable the appropriate callback.
Signed-off-by: Robin Sachsenweger Ballantyne <makenenjoy@gmail.com>
The status clear command buffer is built from compile-time constants and
only read, so make it static const to keep it in read-only memory
instead of rebuilding it on the stack on every call.
Assisted-by: Claude:opus-4.8
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The ACT_DISCHARGE_CNTL position defines were one higher than the
bit index of their corresponding masks, so the discharge bit was
never written on set and reads always reported the discharge as
enabled. Align the positions with the mask bit indices.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
(dma_error & A) || (dma_error & B) || ... is equivalent to
dma_error & (A | B | ...). Collapse the rx/tx ETH_DMASR_* error tests
into single masked checks.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(tmp & A) != 0 || (tmp & B) != 0 is equivalent to (tmp & (A | B)) != 0.
Collapse the temperature and humidity threshold status tests into single
masked checks.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(status & A) || (status & B) is equivalent to status & (A | B). Collapse
the RV3032_STATUS_TLF / RV3032_STATUS_THF test into a single masked
check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(op & A) || (op & B) is equivalent to op & (A | B). Collapse the
RES_TYPE_SEL_48 / RES_TYPE_SEL_136 test into a single masked check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(mask & A) || (mask & B) is equivalent to mask & (A | B). Collapse the
RTC_ALARM_TIME_MASK_MONTHDAY / _WEEKDAY test into a single masked check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(cfg & A) || (cfg & B) is equivalent to cfg & (A | B). Collapse the
I2S_FMT_* and I2S_OPT_* tests into single masked checks.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(tmp & A) != 0 || (tmp & B) != 0 is equivalent to (tmp & (A | B)) != 0.
Collapse the I2C_ARB_INT / I2C_FER_INT test into a single masked check.
No change in behavior.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(eflg & A) || (eflg & B) is equivalent to eflg & (A | B). Collapse the
MCP2515_EFLG_RXEP / MCP2515_EFLG_TXEP test into a single masked check.
No change in behavior.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(flags & A) || (flags & B) is equivalent to flags & (A | B). Collapse
the IRQ_TYPE_* polarity/level tests into a single masked check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(flags & A) || (flags & B) is equivalent to flags & (A | B). Collapse
the pull-up/pull-down, output-init, and input/output bias tests into a
single masked check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
(options & A) || (options & B) is equivalent to options & (A | B).
Collapse the two WDT_OPT_PAUSE_IN_SLEEP / WDT_OPT_PAUSE_HALTED_BY_DBG
tests into a single masked check.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Flash operation experiments revealed that sending the OP2 command may
prematurely return status 0x80 (successful completion) while the data
is not yet ready. Per vendor note, data must be read only after
successfully confirming the operation status.
Refactor espi_taf_npcx_rpmc_op2() to separate status polling from data
reading:
- Split UMA operations into distinct status and data structures
- Add timeout check after retry loop to catch persistent BUSY status
Signed-off-by: Aditya Bhutada <aditya.bhutada@intel.com>
The default "bosch,bmi270" compatible selects the max_fifo feature set,
whose anymo_1/anymo_2 registers are NULL. Enabling SENSOR_TRIG_MOTION then
made bmi270_anymo_config() pass those NULL pointers to
bmi270_feature_reg_write(); on Cortex-M address 0 is readable, so the write
silently targeted an unintended feature page and returned success, leaving
the trigger a no-op.
Return -ENOTSUP when the configured feature set does not provide the
any-motion registers, so the condition is reported instead of failing
silently.
Fixes#112938
Signed-off-by: Rupesh Majhi <zoone.rupert@gmail.com>
The base controller holds channels 0 to 7, but the interrupt flag
lookup, flag clearing and ISR dispatch all treated channel 8 as a
base channel, shifting the 32-bit flag registers by 32 and leaving
the first extended slot unreachable. Split at eight consistently.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
use net_pkt_frag_unref instead of net_buf_unref,
so the allocation tracking information is correct
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The rampstat poll loop indexes the motion controller array but was
bounded by the stepper driver count, skipping controllers or
reading out of bounds when the two child counts differ.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
log_stallguard() called tmc50xx_read_actual_position() without the
motor index argument, breaking the build whenever
CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL_STALLGUARD_LOG is
enabled. Pass the index of the motor being polled.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
AESC_PINCTRL_MAX_PINS is the pin count, so valid indices are
0 to MAX_PINS - 1, but the guard used '>', letting pin 128 write one
register past the pin mux range. Use '>='.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
WRITE_BIT takes a bit index but was passed BIT(pin), applying the
GPIO-function enable to the wrong bit. Pass the pin index.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The tick timer fires only on an exact TTMR.TP == TTCR[27:0] match, but
sys_clock_set_timeout() wrote the computed compare value blindly. A
deadline that lands at or behind the count by the time TTMR is written
- for instance a timeout armed just before its tick boundary, or an
arm delayed by interrupt latency - is silently missed until the 28-bit
count wraps, 13.4 seconds at the 20 MHz QEMU clock. The one-tick arms
in the ISR (tickful) and at driver init carry the same, rarer,
exposure.
Route all compare writes through a catch-up: after writing the target,
re-read the count and, while the target is not strictly in the future,
push it MIN_DELAY ahead of the fresh count. A post-write count read
still behind the target proves the match is armed; the exit check
accepts any strictly-future target rather than demanding MIN_DELAY of
remaining headroom, which a count that advances between the write and
the re-read could never satisfy (that stricter form livelocks under
QEMU icount, where the count moves every instruction).
Found by the kernel.timer.timeout_churn near-boundary sweep, which
steps zero-duration timer arms across the tick phase: an arm landing
within the final microseconds of a tick fired 13430 ms late.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Let's ifdef the common variables, so we avoid unused variables
warnings when neither RTC_ALARM or RTC_UPDATE are set.
This can be reproduced for examples building
tests/drivers/rtc/rtc_api_helpers for sam_v71_xult/samv71q21
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The reset flags are a two-bit enumerated field, not independent
bits, so testing flags with a bitwise AND against
WDT_FLAG_RESET_CPU_CORE left WDT_FLAG_RESET_SOC without reset
enabled. The flag was also never cleared on re-install. Derive
allow_reset from the masked field on every install.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The channel guard combined its checks with &&, accepting any channel
type with index 0. Use ||, matching sb_tsi_emul_get_sample_range().
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The 2586 Ohm point was listed at 64 degC in a table that steps by
exactly 10 degC, skewing interpolation between 55 and 75 degC. Use
65 degC.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Operator precedence applied the scale factor to the high byte before
OR-ing in the low byte, and the 16-bit sign was lost. Assemble and
sign-extend the raw value first, as the magnetometer path does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
set_iir_config() overwrote the whole DSP_IIR register with the raw
temperature coefficient instead of programming it through the
BMP5_SET_IIR_TEMP bitfield, corrupting the pressure IIR setting.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The heartbeat error case fell through into default and returned
-ENOTSUP, so fetching the channel always failed. Add the missing
break.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
sizeof(temp_buffer) on a pointer parameter truncated the UART receive
to the pointer size. Pass MTCH9010_INTERNAL_BUFFER_SIZE.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
