The cache driver API requires cache_data_flush_all(),
cache_data_invd_all() and cache_data_flush_and_invd_all() to be
defined whenever CONFIG_DCACHE is selected. Without these symbols,
any image that pulls in the generic cache API fails to link on
ESP32 SoCs with the cache driver enabled, for example:
tests/kernel/cache on esp32s2_devkitc
tests/kernel/cache on esp32s3_devkitc/procpu
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The GPIO_DDR register uses 1 for output mode and 0 for input mode.
The previous implementation incorrectly swapped these values, causing
gpio_pin_is_input() and gpio_pin_is_output() to return wrong results.
Also mask out unconnected pins using connect_pin to ensure
disconnected GPIOs are not reported as either input or output.
Fixes gpio_get_direction test failures on RTL87x2G and RTL8752H series.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
When network is temporary lost, we might receive
PPP_DEAD event just before parsing "+CEREG: ..."
Therefore immediately redialing might lead to out-of-sync
states.
Delay the redial script by the PERIODIC_SCRIPT_TIMEOUT
as any other script failures do.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
In tcpci_tcpm_transmit_data() the gate that decides whether the packet
is a non-SOP* transmission (Hard Reset, Cable Reset, BIST) was checking
msg->header.message_type, the 5-bit PD header message type ID. That
field overlaps the SOP* range: any standard SOP message whose header
message_type is >= NUM_SOP_STAR_TYPES (e.g. PS_RDY = 6, PR_Swap = 10,
DR_Swap = 11, ...) was misclassified as non-SOP* and written to the
TRANSMIT register without retries, undermining PD negotiation
reliability against CC-line noise.
The TRANSMIT register's type field is enum pd_packet_type, which is
carried in msg->type. Use msg->type for both the gate and the
TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY() argument, matching the retry
path further down the function which already uses msg->type.
Signed-off-by: Way Young <wayyoung@gmail.com>
Replace the fixed 1-second transfer timeout with a value derived from
the actual number of SCL cycles required for the transfer, plus a
configurable margin (I3C_CADENCE_TRANSFER_TIMEOUT_MARGIN_US, default
10000 us).
Three helpers cover each transfer type:
- cdns_i3c_calc_timeout_i3c: SDR (broadcast header + 9 bits/byte) and
HDR-DDR (ENTHDR0 preamble + DDR word count at 8 SCL cycles/word,
including command header and CRC words)
- cdns_i3c_calc_timeout_i2c: 7-bit (9 bits) or 10-bit (18 bits)
address frame + 9 bits per data byte, using the I2C SCL frequency
- cdns_i3c_calc_timeout_ccc: broadcast addr + CCC command byte +
optional broadcast data + per-target address and data
Signed-off-by: Ryan McClelland <rymcclel@gmail.com>
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The battery alias is verified to be a sensor device before use.
Also the commit fixes incorrect use of `argv[1]` instead of `dev->name`.
Signed-off-by: Maksim Salau <maksim.salau@gmail.com>
Ready registers are defined for the nrf54h series but not necesssary for
other soc families.
Limit the Ready register check only to this family of socs.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Remove the 'andestech,qspi-nor-xip' compatible string and unify both
flash_andes_qspi.c and flash_andes_qspi_xip.c flash drivers use
'andestech,qspi-nor' compatible string.
The driver selection is now handled via Kconfig logic.
CONFIG_FLASH_ANDES_QSPI_XIP is strickly depends on XIP is enabled and
the 'zephyr,flash' chosen node is compatible with 'andestech,qspi-nor'.
Since these two driver variants cannot coexist, the application is
responsible for enabling the appropriate driver Kconfig.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add the pwm-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_pwm.c. The PWM channel period sets the audio
frequency and the duty cycle sets the perceived volume (50% is
loudest for piezos; the driver maps the linear 0..100% volume
percentage to a triangular 0..50% duty curve so 100% volume gives
maximum loudness).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add the gpio-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_gpio.c. Active buzzers contain their own
oscillator and produce a fixed tone whenever they are powered.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Introduce a consumer-facing buzzer API for boards that have a buzzer
wired through a PWM channel or a single GPIO. Apps drive buzzers via
buzzer_tone(), buzzer_beep() (plays the device's natural frequency
encoded in DT), buzzer_set_volume(), and buzzer_stop().
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
add spinlock for thread safety in socket operations. I noticed that
the native_sim would otherwise crash
under high network load.
Signed-off-by: Fin Maaß <info@finmaass.de>
Validate the SPI bus frequency supplied via spi_config before it is
used to compute the baud-rate clock divider to prevent the following
faults:
- A zero frequency causes an integer division-by-zero when computing
the clock divider, resulting in a hardware fault or an undefined
value being written to the SPI_BAUDR register.
- A frequency exceeding half of the input core clock produces a
divider value less than the minimum of 2 required by the
DesignWare SSI databook (section 6.2.2), overclocking the
peripheral and causing undefined bus behaviour.
Return -EINVAL for a zero frequency and -EINVAL for a frequency
greater than clk_hz / 2, surfacing the error to the caller rather
than silently misconfiguring the hardware.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
When configuring the nRF SPIM, the frequency needs to be limited by
the max frequency of the SPIM, which is specified in the devicetree.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
These functions are from phy_oa_tc14_plca.c, which
is only a helper for phys to implement the set_plca_cfg,
get_plca_cfg and get_plca_sts functions of the ethernet_phy
api, therefore they should be internal.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Fix SPI clock frequency being modified during DMA transfers.
Fix regression in DMA configuration structure update.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Fix incorrect behavior for non-8-bit SPI word sizes.
Fix the handling when both TX and RX buffers are NULL.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Enable IOCON clocks from the devicetree clocks property during
pinctrl initialization.
Keep the existing LPC path intact and only use the clock control
flow when a clock is described in devicetree.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx IOCON clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common gate support needed for RT7xx IOCON
instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Use the optional clocks property to request the GPIO port clock
during driver initialization.
This lets RT7xx GPIO instances rely on the common clock control
path instead of board-specific clock enabling.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx GPIO clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common GPIO gate support needed for RT7xx
GPIO instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The RA SDHC driver handles SD_SWITCH/CMD6 through
r_sdhi_read_and_block(), then copies the returned status from the
FSP aligned buffer into the Zephyr request buffer.
CMD6 switch status is a 64-byte data block. The driver copied only
8 bytes, which is the SCR size used by ACMD51. This left byte 13
uninitialized or stale, so the SD core could read bus_speed as 0.
With bus_speed misread, the SD core skipped high-speed setup. Since
the current init flow switches to 4-bit width after high-speed setup,
ACMD6 bus-width switching was also skipped despite host and card
both advertising 4-bit support.
Copy ra_cmd.sector_size bytes instead, matching the requested data
block size. For CMD6 this preserves the full 64-byte switch status.
Signed-off-by: Shan Pen <bricle031@gmail.com>
Added autanalog CTB support for PSE84 device.
This implementation uses the autnonomous controller (MFD)
that is shared with other autanalog drivers.
The CTB stands for Continuous Time Block. It is a set of opamps
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
Each CTB block contains two opamps, which need to be configured
together and accessed using the AC. A CTB MFD is used to bring
together the two opamp configurations. AC MFD then references the
combined CTB MFD configuration, and brings together all other
autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The missing errno return in ibi path causes the function
to return 0 (success) when raising ibi times out.
This patch addresses this issue.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
shell_info is intended for informational side-notes, not for printing
command result data. Use shell_print instead, consistent with other
Zephyr driver shell implementations (rtc_shell, gpio_shell, i2c_shell,
eeprom_shell).
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Assisted-by: Claude:claude-sonnet-4-6
When the TimeOut is enabled in MemoryMapped mode, the TO irq callback
has not to give any sem, because the read operation is done with
memcopy(). No sem was taken, nothing to release.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
When using a 32-bit based I2S peripheral such as a PCM1809, the default
DMA configuration of 16 bit doesn't work; due to the incorrect length,
the I2S buffers are filled with only zeroes. Rather than hardcode 16 bit
length, check for word size and set the DMA configuration accordingly.
Signed-off-by: Peter Allenspach <uberrice@pm.me>
The function lfclk_spinwait in the clock_control_nrf.c driver uses
k_cpu_atomic_idle() to idle until the CLOCK IRQ caused by the
LFCLKSTARTED event is triggered.
The implementation of the (check -> set -> idle) loop breaks if
unrelated clock events like XOSTARTED and XOTUNED occur concurrently,
since they trigger the the CLOCK IRQ as well. This can wake up the
CPU before LFCLKSTART event, which means NVIC_ClearPendingIRQ() is
not called before we enter idle again.
Solve the race condition between
(critical section -> check -> set -> maybe clear pending -> idle)
by refactoring it to
(critical section -> clear pending -> check -> set -> idle)
Which ensures the LFCLKSTARTED event is not lost if it occurs during
the (check -> set -> idle) flow.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Use LL_PWR_* APIs to handle UCPD_DBDIS flags in portable way.
Fix ucpd_params.psc_ucpdclk value.
Signed-off-by: Vladimir Zidar <vladimir.zidar@ars-es.com>
When a DMA channel is routed through the channel mux (dma_slot != 0), each
minor loop is paced by the peripheral request signal. In this case, the
caller-chosen burst length must be preserved to ensure correct operation.
Previously, the driver would collapse the minor loop into the whole block
for all memory-to-memory transfers without source chaining, but this logic
should only apply to genuine software-triggered transfers. Peripheral-
triggered transfers (e.g., FlexIO LCDIF) expect one minor loop per shifter
round, and collapsing the loop breaks this requirement.
Add a check for dma_slot == 0 to ensure burst length collapsing only occurs
for software-triggered transfers, not peripheral-triggered ones.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Nordic's nPM10 Series PMIC watchdog driver implementation and devicetree
bindings.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Add timer support to the nPM10 Series MFD driver. This can be used as a
general purpose timer, wakeup timer for hibernation modes and as watchdog.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Drain any pending bytes on the pipe when `modem_at_user_pipe_claim` is
called, as these will either be unsolicited notifications or messages
from previous users of the pipe. Draining the pipe on claim prevents
this data appearing in unexpected places.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add a timeout parameter to `modem_at_user_pipe_claim` to enable blocking
for a duration on pipe availability.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Update the AT user pipe API so that the initialisation does not require
the modem chat instance. This enables sharing the user pipe abstraction
between multiple users at runtime.
One consequence of this is that `modem_chat_attach` is deferred until
the user calls `modem_at_user_pipe_claim`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
LL_TIM_TRGO_UPDATE isn't yet implemented on STM32WB0x series.
Exclude WB0x series from using LL_TIM_TRGO_UPDATE.
This is addressed by testing HAS_MASTERMODE_SUPPORT that is disabled
for platforms not defining LL_TIM_TRGO_UPDATE.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
The CRC16 reflect issue is not accepted by the Renesas RA driver,
even though it is supported by the HWIP.
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Replace direct esp_cache_msync() calls in the ESP32 GDMA and
SPI master drivers with the portable sys_cache_data_*() API.
Zephyr's API is a compile-time no-op when CACHE_MANAGEMENT is
disabled, so the same source compiles cleanly on every ESP32
SoC and stays cost-free where there is no writeback cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Map the generic sys_cache_data_* API onto esp_cache_msync()
from hal_espressif. The driver is SoC-agnostic and activates on
any Espressif chip that selects CPU_HAS_DCACHE and enables
CACHE_MANAGEMENT, keeping PSRAM and DMA buffers coherent from
portable Zephyr code.
Instruction-cache and enable/disable entries are no-ops since
the bootloader brings the cache up before Zephyr runs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
