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drivers: clock_control: nrf2: align with hw binding names

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Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.

There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This commit is contained in:
Bjarki Arge Andreasen 2025-06-06 12:17:06 +02:00 • committed by Benjamin Cabé
commit 979a565289
15 changed files with 39 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/audio/dmic_nrfx_pdm.c
View file

@ -30,7 +30,7 @@ struct dmic_nrfx_pdm_drv_data {
const nrfx_pdm_t *pdm;
#if CONFIG_CLOCK_CONTROL_NRF
struct onoff_manager *clk_mgr;
#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
const struct device *audiopll_dev;
#endif
struct onoff_client clk_cli;
@ -75,7 +75,7 @@ static int request_clock(struct dmic_nrfx_pdm_drv_data *drv_data)
}
#if CONFIG_CLOCK_CONTROL_NRF
return onoff_request(drv_data->clk_mgr, &drv_data->clk_cli);
#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
return nrf_clock_control_request(drv_data->audiopll_dev, NULL, &drv_data->clk_cli);
#else
return -ENOTSUP;
@ -90,7 +90,7 @@ static int release_clock(struct dmic_nrfx_pdm_drv_data *drv_data)
#if CONFIG_CLOCK_CONTROL_NRF
return onoff_release(drv_data->clk_mgr);
#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
return nrf_clock_control_release(drv_data->audiopll_dev, NULL);
#else
return -ENOTSUP;
@ -673,7 +673,7 @@ static void init_clock_manager(const struct device *dev)
drv_data->clk_mgr = z_nrf_clock_control_get_onoff(subsys);
__ASSERT_NO_MSG(drv_data->clk_mgr != NULL);
#elif CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
struct dmic_nrfx_pdm_drv_data *drv_data = dev->data;
drv_data->audiopll_dev = DEVICE_DT_GET(DT_NODELABEL(audiopll));

12
drivers/clock_control/CMakeLists.txt
View file

@ -45,17 +45,17 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_cont
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL clock_control_nrf2_global_hsfll.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL clock_control_nrf_hsfll_global.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RTS5912_SCCON clock_control_rts5912_sccon.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL clock_control_nrf2_audiopll.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL clock_control_nrfs_audiopll.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IT51XXX clock_control_it51xxx.c)
if(CONFIG_CLOCK_CONTROL_NRF2)
zephyr_library_sources(clock_control_nrf2_common.c)
zephyr_library_sources(clock_control_nrf2_fll16m.c)
zephyr_library_sources(clock_control_nrf2_hfxo.c)
zephyr_library_sources(clock_control_nrf2_hsfll.c)
zephyr_library_sources(clock_control_nrf2_lfclk.c)
zephyr_library_sources(clock_control_nrf_fll16m.c)
zephyr_library_sources(clock_control_nrf54h_hfxo.c)
zephyr_library_sources(clock_control_nrf_hsfll_local.c)
zephyr_library_sources(clock_control_nrf_lfclk.c)
endif()
if(CONFIG_CLOCK_CONTROL_RENESAS_RZA2M_CPG)

20
drivers/clock_control/Kconfig.nrf
View file

@ -216,32 +216,32 @@ config CLOCK_CONTROL_NRF2
if CLOCK_CONTROL_NRF2
config CLOCK_CONTROL_NRF2_HSFLL_REQ_LOW_FREQ
config CLOCK_CONTROL_NRF_HSFLL_LOCAL_REQ_LOW_FREQ
bool "Local domain scale down after init"
default y if NRFS_DVFS_LOCAL_DOMAIN
help
Request the lowest operating point after DVFS initialization.
config CLOCK_CONTROL_NRF2_NRFS_DVFS_TIMEOUT_MS
config CLOCK_CONTROL_NRF_HSFLL_LOCAL_NRFS_DVFS_TIMEOUT_MS
int "Timeout waiting for nrfs dvfs service callback in milliseconds"
default 2000
config CLOCK_CONTROL_NRF2_NRFS_CLOCK_TIMEOUT_MS
config CLOCK_CONTROL_NRF_LFCLK_CLOCK_TIMEOUT_MS
int "Timeout waiting for nrfs clock service callback in milliseconds"
default 1000
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
config CLOCK_CONTROL_NRF_HSFLL_GLOBAL
bool "Clock control for global HSFLL"
depends on NRFS_GDFS_SERVICE_ENABLED
default y
if CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
if CLOCK_CONTROL_NRF_HSFLL_GLOBAL
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_TIMEOUT_MS
config CLOCK_CONTROL_NRF_HSFLL_GLOBAL_TIMEOUT_MS
int "Frequency request timeout in milliseconds"
default 10000
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_REQ_LOW_FREQ
config CLOCK_CONTROL_NRF_HSFLL_GLOBAL_REQ_LOW_FREQ
bool "Request LOW frequency on init"
default y
help
@ -255,15 +255,15 @@ config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_REQ_LOW_FREQ
unnecessary HIGH -> LOW -> HIGH cycle given some module will
request a HIGH frequency on init anyway.
config CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY
config CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
int "Init priority of global HSFLL device driver"
default 52
help
Must be higher than NRFS backend
endif # CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
endif # CLOCK_CONTROL_NRF_HSFLL_GLOBAL
config CLOCK_CONTROL_NRF2_AUDIOPLL
config CLOCK_CONTROL_NRFS_AUDIOPLL
bool "NRFS AudioPLL driver support"
depends on DT_HAS_NORDIC_NRFS_AUDIOPLL_ENABLED
depends on NRFS_AUDIOPLL_SERVICE_ENABLED

0
drivers/clock_control/clock_control_nrf2_hfxo.c → drivers/clock_control/clock_control_nrf54h_hfxo.c
View file

0
drivers/clock_control/clock_control_nrf2_fll16m.c → drivers/clock_control/clock_control_nrf_fll16m.c
View file

6
drivers/clock_control/clock_control_nrf2_global_hsfll.c → drivers/clock_control/clock_control_nrf_hsfll_global.c
View file

@ -23,10 +23,10 @@ LOG_MODULE_DECLARE(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
DT_INST_PROP_LEN(0, supported_clock_frequencies)
#define GLOBAL_HSFLL_FREQ_REQ_TIMEOUT \
K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_TIMEOUT_MS)
K_MSEC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_TIMEOUT_MS)
#define GLOBAL_HSFLL_INIT_LOW_REQ \
CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_REQ_LOW_FREQ
CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_REQ_LOW_FREQ
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE == 4);
BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(0) == 64000000);
@ -339,6 +339,6 @@ DEVICE_DT_INST_DEFINE(
&driver_data,
&driver_config,
POST_KERNEL,
CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY,
CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY,
&driver_api
);

4
drivers/clock_control/clock_control_nrf2_hsfll.c → drivers/clock_control/clock_control_nrf_hsfll_local.c
View file

@ -25,7 +25,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
#define HSFLL_FREQ_MEDLOW MHZ(128)
#define HSFLL_FREQ_HIGH MHZ(320)
#define NRFS_DVFS_TIMEOUT K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_NRFS_DVFS_TIMEOUT_MS)
#define NRFS_DVFS_TIMEOUT K_MSEC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_LOCAL_NRFS_DVFS_TIMEOUT_MS)
/* Clock options sorted from lowest to highest frequency */
static const struct clock_options {
@ -262,7 +262,7 @@ static struct hsfll_dev_data hsfll_data;
#ifdef CONFIG_CLOCK_CONTROL_NRF2_HSFLL_REQ_LOW_FREQ
static int dvfs_low_init(void)
{
static const k_timeout_t timeout = K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_NRFS_DVFS_TIMEOUT_MS);
static const k_timeout_t timeout = NRFS_DVFS_TIMEOUT;
static const struct device *hsfll_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(cpu)));
static const struct nrf_clock_spec clk_spec = {
.frequency = HSFLL_FREQ_LOW

2
drivers/clock_control/clock_control_nrf2_lfclk.c → drivers/clock_control/clock_control_nrf_lfclk.c
View file

@ -27,7 +27,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
#define LFCLK_MAX_OPTS 4
#define LFCLK_DEF_OPTS 2
#define NRFS_CLOCK_TIMEOUT K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_NRFS_CLOCK_TIMEOUT_MS)
#define NRFS_CLOCK_TIMEOUT K_MSEC(CONFIG_CLOCK_CONTROL_NRF_LFCLK_CLOCK_TIMEOUT_MS)
#define BICR (NRF_BICR_Type *)DT_REG_ADDR(DT_NODELABEL(bicr))

0
drivers/clock_control/clock_control_nrf2_audiopll.c → drivers/clock_control/clock_control_nrfs_audiopll.c
View file

2
drivers/counter/counter_nrfx_timer.c
View file

@ -481,7 +481,7 @@ static DEVICE_API(counter, counter_nrfx_driver_api) = {
*/
#define TIMER_INIT_PRIO(idx) \
COND_CODE_1(INSTANCE_IS_FAST(idx), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY)), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
(CONFIG_COUNTER_INIT_PRIORITY))
/*

4
drivers/i2s/i2s_nrf_tdm.c
View file

@ -127,7 +127,7 @@ static int audio_clock_request(struct tdm_drv_data *drv_data)
{
#if DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRF
return onoff_request(drv_data->clk_mgr, &drv_data->clk_cli);
#elif DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
return nrf_clock_control_request(audiopll, &aclk_spec, &drv_data->clk_cli);
#else
(void)drv_data;
@ -140,7 +140,7 @@ static int audio_clock_release(struct tdm_drv_data *drv_data)
{
#if DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRF
return onoff_release(drv_data->clk_mgr);
#elif DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL
#elif DT_NODE_HAS_STATUS_OKAY(NODE_ACLK) && CONFIG_CLOCK_CONTROL_NRFS_AUDIOPLL
(void)drv_data;
return nrf_clock_control_release(audiopll, &aclk_spec);

8
drivers/pwm/pwm_nrfx.c
View file

@ -55,7 +55,7 @@ LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL);
BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE_SYSTEM_MANAGED));
#endif
#if defined(PWM_NRFX_FAST_PRESENT) && CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL
#if defined(PWM_NRFX_FAST_PRESENT) && CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL
#define PWM_NRFX_USE_CLOCK_CONTROL 1
#endif
@ -484,11 +484,11 @@ static int pwm_nrfx_init(const struct device *dev)
* must be initialized after that controller driver, hence the default PWM
* initialization priority may be too early for them.
*/
#if defined(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY) && \
CONFIG_PWM_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY
#if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY) && \
CONFIG_PWM_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
#define PWM_INIT_PRIORITY(idx) \
COND_CODE_1(PWM_NRFX_IS_FAST(_, /*empty*/, idx, _), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY)), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
(CONFIG_PWM_INIT_PRIORITY))
#else
#define PWM_INIT_PRIORITY(idx) CONFIG_PWM_INIT_PRIORITY

2
drivers/serial/uart_nrfx_uarte.c
View file

@ -2587,7 +2587,7 @@ static int uarte_instance_init(const struct device *dev,
*/
#define UARTE_INIT_PRIO(idx) \
COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY)), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
(CONFIG_SERIAL_INIT_PRIORITY))
/* Macro for setting nRF specific configuration structures. */

8
drivers/spi/spi_nrfx_spim.c
View file

@ -43,7 +43,7 @@ LOG_MODULE_REGISTER(spi_nrfx_spim, CONFIG_SPI_LOG_LEVEL);
#define SPI_BUFFER_IN_RAM 1
#endif
#if defined(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL)
#if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL)
#define SPIM_REQUESTS_CLOCK(node) \
DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(node), nordic_nrf_hsfll_global)
#define SPIM_REQUESTS_CLOCK_OR(node) SPIM_REQUESTS_CLOCK(node) ||
@ -796,11 +796,11 @@ static int spi_nrfx_init(const struct device *dev)
* must be initialized after that controller driver, hence the default SPI
* initialization priority may be too early for them.
*/
#if defined(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY) && \
CONFIG_SPI_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY
#if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY) && \
CONFIG_SPI_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
#define SPIM_INIT_PRIORITY(idx) \
COND_CODE_1(SPIM_REQUESTS_CLOCK(SPIM(idx)), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY)), \
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
(CONFIG_SPI_INIT_PRIORITY))
#else
#define SPIM_INIT_PRIORITY(idx) CONFIG_SPI_INIT_PRIORITY

2
samples/boards/nordic/clock_control/sample.yaml
View file

@ -37,7 +37,7 @@ tests:
sample.boards.nrf.clock_control.global_hsfll.req_low_freq_n:
filter: dt_nodelabel_enabled("hsfll120")
extra_configs:
- CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_REQ_LOW_FREQ=n
- CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_REQ_LOW_FREQ=n
extra_args:
- CONF_FILE="configs/global_hsfll.conf"
- DTC_OVERLAY_FILE="configs/global_hsfll.overlay"