Implement the recv_duty_cycle API using the SX126x hardware
SetRxDutyCycle command. The radio autonomously alternates between
short RX windows and sleep, waking the MCU only on packet reception.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Add I2C driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master mode operation
- 7-bit and 10-bit addressing
- Standard and Fast mode speeds
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add support for configuring the Set Tear ScanLine (STE) command in the
ST7796S LCD display driver. This allows users to specify the exact
scanline where the Tearing Effect (TE) signal becomes active, providing
better control over display synchronization.
Changes:
- Add ST7796S_CMD_STE (0x44) command definition
- Add tear-scanline property to device tree binding
- Add tear_scanline field to driver configuration structure
- Implement STE command configuration in LCD initialization
The tear scanline can now be configured via device tree:
tear-scanline = <240>; // TE signal at scanline 240
Signed-off-by: Ankitkumar Modi <ankit.modi912@gmail.com>
The DWC2 USB driver was accessing hardware registers
through a raw dev->config->base pointer, which breaks on
MMU-enabled platforms where physical addresses need to be
mapped to virtual ones before use.
Use Zephyr's standard MMIO abstraction API by introducing
DEVICE_MMIO_NAMED_RAM/ROM(core) in the driver's data and
config structs, mapping the region at initialization time
with DEVICE_MMIO_NAMED_MAP, and routing all register accesses
through a dwc2_get_base() helper that calls DEVICE_MMIO_NAMED_GET.
These changes allows the driver to be useful on MMU-based
platforms like Broadcom BCM2711 SoC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Coverity reported a potential out-of-bounds access in
drivers/wifi/esp_at/esp_offload.c when accessing sin_addr
without validating the sockaddr family.
ESP-AT offload supports IPv4 only, so add an explicit
NET_AF_INET check before dereferencing the IPv4-specific
structure to prevent invalid memory access.
Fixes: #100001
Signed-off-by: Om Srivastava <srivastavaom97714@gmail.com>
Refactor the nrf_spim device driver to share the common code between
the nrf_spim_rtio implementation.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Move the private spi_rtio.h header from the public path
include/zephyr/drivers/spi/rtio.h
the the private path
drivers/spi/spi_rtio.h
and update drivers to include it using a relative path.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SPI_LOCK_ON flag is not compatible with RTIO, nor is the
related spi_release API. Introduce stub implementation for drivers to
use which simply returns -ENOTSUP and validate SPI_LOCK_ON within the
spi_rtio_transceive wrappers.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce spi_rtio_transceive_cb which is an implementation of the
spi_transceive_cb API based on the spi_rtio context.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Don't rely on drivers protecting the spi_rtio ctx from multiple
threads as this is generic and could just be part of the spi_rtio
context to avoid duplicate code and thus make using it safer and
more efficient.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi_rtio_copy implementation incorrectly sets up a transceive sqe
in place of a write or read when an empty "spacer" spi_buf is passed
which is not aligned with the "opposing" spi_buf. Using transceive in
these cases passes a NULL receive/transmit buffer with positive length,
which is a bug.
Some drivers have an additional check to clear the size if the buffer
is NULL, but we should not rely on this check in drivers as it is
duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Move variable declarations into platform-specific conditional blocks
and extend i.MX93 support to include M33 core. This eliminates unused
variable compilation warnings without affecting existing platform
functionality.
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
- Added mcux_lcdifv3_set_pixel_format api
- Fix pointer-to-integer cast error by using uintptr_t intermediate cast
instead of direct uint64_t cast
- Fixed the pixel_format setting on waveshare_dsi_lcd shield
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Add support for the DAC module on TI’s MSPM0 G-Series MCUs. The DAC
supports 8-bit and 12-bit resolution.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Call i2c_hal_init() during driver init and after the clock
off/on cycle in i2c_hw_fsm_reset(). On SoCs where the
controller clock gate defaults to off, the peripheral would
not respond until explicitly enabled, matching the behavior
of ESP-IDF's i2c_hal_init().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
IDLE exit is programmed to happen shortly before systimer
programmed wake-up event happens. If the interrupt from
the timer happens before, idle_exit() does not run, as
timeout_idle flag is cleared at the ISR. Fix condition for
both systimer (ESP32) and xtensa drivers.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Fixes zephyrproject-rtos/zephyr#106597
The current driver for the NXP C40 flash controller instantiates two
drivers, one for the controller (which has no real code -- it's just
a device with no API, config, or data), and one for the flash bank.
This breaks the various partition APIs because they expect the flash
driver API to be attached to the "grandparent" of the partitions
object -- but in the current C40 driver, it is attached to the parent.
I was worried this fix was going to be more complicated, but it
appears to have been quite simple. All I needed to do was to
instantiate a single device with the the API, config and data.
The fix requires the "soc-nv-flash" compatibility to be added to
device trees which reference this driver (see previous commit).
This fix addresses the bug report I filed a few days ago:
NXP C40 flash driver incompatibility with partitions macro APIs #106597
Signed-off-by: Rob Newberry <rob@zenomoto.com>
Signed-off-by: rob-zeno <rob@zenomoto.com>
Migrate intel_adsp_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate apic_tsc to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate hpet to the unified timer lock API. Replace the driver-private
spinlock with sys_clock_lock()/sys_clock_announce_locked().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate xtensa_sys_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline and the kernel tick counter are
always updated under the same lock.
Also migrate sys_clock_idle_exit() which updates driver state and
announces ticks on LPM exit.
Add extern declarations for sys_clock_cycle_get_32/64 in
arch/xtensa/arch.h, consistent with all other architectures, to
avoid a circular include dependency with system_timer.h. Xtensa
was the only architecture missing them.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate riscv_machine_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline (last_count) and the kernel tick
counter (curr_tick) are always updated under the same lock.
This eliminates a race on SMP where sys_clock_elapsed() could observe
the updated last_count before sys_clock_announce() had advanced
curr_tick, causing time-dependent kernel operations to see inconsistent
values.
Remove internal locking from sys_clock_set_timeout() and
sys_clock_elapsed() as they are now always called with the timer lock
held.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Migrate arm_arch_timer to the unified timer lock API. Replace the
driver-private spinlock with sys_clock_lock()/sys_clock_announce_locked()
so that the hardware cycle baseline (last_cycle) and the kernel tick
counter (curr_tick) are always updated under the same lock.
This eliminates a race on SMP where sys_clock_elapsed() could observe
the updated last_cycle before sys_clock_announce() had advanced
curr_tick, causing time-dependent kernel operations to see inconsistent
values.
Remove internal locking from sys_clock_set_timeout() and
sys_clock_elapsed() as they are now always called with the timer lock
held.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Change indentation on multi-line test instruction for consistency
and to ease readability. Also replace 2 tabulations with a space char.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
LPADC_DoOffsetCalibration() triggers offset calibration but returns
immediately without waiting for it to complete. If gain calibration
is requested before offset calibration finishes, the hardware silently
rejects it and GCC[RDY] never asserts, causing
LPADC_FinishAutoCalibration() to spin forever at boot (~50% of the
time on affected boards like FRDM-MCXA266).
Fix by replacing LPADC_DoAutoCalibration() with the split HAL API:
LPADC_PrepareAutoCalibration() + k_busy_wait(1U) +
LPADC_FinishAutoCalibration()
The 1us busy-wait gives offset calibration sufficient time to complete
on all LPADC platforms before the gain calibration request is issued.
Only the HAS_CTRL_CALOFS path is affected (the path that also calls
DoOffsetCalibration); the HAS_CFG_CALOFS path has no preceding offset
calibration and is left unchanged.
Fixes#105652
Signed-off-by: Jjateen Gundesha <jjateen97@gmail.com>
Correct some behaviors that were broken in the original SPI DMA + RTIO
work:
* Properly fallback to interrupt behavior if no DMA channels are assigned
to a given SPI peripheral.
* Properly handle held CS lines across transactions when using hardware CS
control.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The VIM IP has a register that informs the maximum
number of interrupts that can be supported.
The ASSERT must check whether the number of IRQs
is LESSER THAN OR EQUAL to above register value,
not a strict equality check.
Signed-off-by: Shreyas Shankar <s-shankar@ti.com>
Updates the legacy HAL version of the Infineon clock control driver to
be excluded for devices not using the legacy HAL based drivers.
This fixes a failure in the libraries.devicetree.api_ext test, which
on PSC3M5 introduces a "fixed-clock" DTS note that causes
DT_HAS_FIXED_CLOCK_ENABLED and SOC_FAMILY_INFINEON_CAT1 to both be
selected. This results in the HAL based driver being incorrectly
included in the build, causing build errors.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Fix build error when independent reset is enabled on custom host.
Add out-of-band reset kconfig option to guard dependency on host GPIO,
so that in-band independent reset can be supported by default.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
In the `FLEXCAN_SetTimingConfig` function(fsl_flexcan.c), the following
statement is implemented when the Enhanced Bit Timing Register is enabled:
```
base->ENCBT = CAN_ENCBT_NRJW(pConfig->rJumpwidth) |
CAN_ENCBT_NTSEG1((uint32_t)pConfig->phaseSeg1 +
pConfig->propSeg + 1U) |
CAN_ENCBT_NTSEG2(pConfig->phaseSeg2);
```
`prop_seg + 1` represents the length of the propagation segment.
- `pConfig->propSeg` = `flexcan_config.timingConfig.propSeg`
- Therefore, flexcan_config.timingConfig.propSeg(can_mcux_flexcan.c) should
be equal to `data->timing.prop_seg - 1U`.
Fixes: #106238
Signed-off-by: Jianchao Wang <Jianchao.wang_1@nxp.com>
This commit addresses two integer handling issues in the ataes132a
crypto driver identified by coverity scans.
1. In ataes132a_send_command, added a centralized validation check
to ensure the 'nparams' value, when combined with the 5-byte
packet overhead, does not exceed the 8-bit 'count' limit or the
physical 64-byte command buffer. This prevents a potential wrap-
around that would cause the chip to receive an invalid length byte.
2. In the Atmel CRC calculation, added an explicit cast to uint16_t
during the bit-shift operation. This prevents unintended integer
promotion and satisfies static analysis regarding potential
overflows during the 16-bit CRC generation.
Fixes#84683Fixes#84690
Signed-off-by: David J. Leach, Jr. <tasmar@gmail.com>
