rx and tx errors can happen durring normal
operation, but are not fatal, so we only
log them with debug level to not confuse
the users
Signed-off-by: Fin Maaß <info@finmaass.de>
add support for the esp32 in the generic
dwc_mac driver.
esp32 specific code is based
the init of the original esp32 eth driver in zephyr.
The esp32 uses HW version 3.70.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
on some socs, the dma and mac registers are
in a different order, add the possibility to change that.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The XEC SMB-I2C block samples SCL/SDA asynchronously even when its PCR
SLEEP_EN is asserted and auto clock-stretches SCL on a START until the
clocks recover.
Add an opt-in wakeup-source boolean to the binding and arm the block's
START-bit wake (WAKE_STATUS bit 0 / WAKE_ENABLE bit 0 at offsets 0x60
and 0x64) plus the GIRQ22 source bit during PM_DEVICE_ACTION_SUSPEND
when the property is set and a target is attached.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
XEC_I2C_SMB_WK_GIRQ was set to 26, but per the MEC172x and MEC175x
datasheets the SMB-I2C START-bit wake events are routed through GIRQ22
(bits 1..5 for controllers 0..4); GIRQ26 is the GPIO 240..261 aggregator
and unrelated.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add a pm_action handler to i2c_mchp_xec_v2 to gate the I2C block clock via
PCR sleep-enable on suspend and restore it on resume.
Hold a PM_STATE_SUSPEND_TO_IDLE policy lock for the duration of each
controller transfer to prevent the system from entering suspend mid-
transaction.
Additionally, acquire the PM_STATE_SUSPEND_TO_IDLE policy lock on address
match (AAT) within the target ISR. Release this lock upon IDLE, external
STOP, and bus error exits. Also, release the lock in target_unregister to
prevent lock leakage if an unregister action races with an in-flight
transaction.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Extend generic is31fl319x driver to support is31fl3193 variant.
Similar to 3194 but with slight differences on register and
features.
Reword error message.
Update example in binding of is31fl3194 as well for required
current-limit attribute.
Assisted-by: Claude:claude-sonnet-4.6 Claude-Code
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
Add CAN driver support for Realtek Bee series SoCs,
including RTL87x2G.
This driver supports:
- Classic CAN 2.0A/B
- Standard and Extended identifiers
- Remote and data frames
- Transmission and Reception
Unsupport features:
- CAN FD mode
- Manual recovery
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add initial UART driver support for the ELAN EM32 SoC family. The driver
implements basic polling TX/RX via the Zephyr serial API and instantiates
devices from devicetree when an EM32 UART node is present and okay.
Devicetree:
- Compatible: "elan,em32-uart" (binding included)
Notes:
- The driver is initialized at PRE_KERNEL_1
with CONFIG_SERIAL_INIT_PRIORITY
so the device is ready before the console backend binds.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add the initial pinctrl driver support for the ELAN EM32 SoC family.
This driver provides basic pin multiplexing and electrical configuration
support. Device tree bindings are included for pin function definitions.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add the initial GPIO driver support for the ELAN EM32 SoC family.
The driver provides basic GPIO input/output control, pin configuration,
and interrupt handling. Device instances are created from devicetree.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add clock control drivers for the Elan EM32 AHB and APB domains along with
DT bindings and clock gate IDs.
Model peripheral clock gating with #clock-cells = <1>, where the clock
specifier carries a gate-id. Introduce EM32_GATE_NONE for nodes that only
need a parent clock reference without a hardware gate.
Update the EM32 SoC/board devicetree to pass gate-ids in `clocks`
properties and integrate the drivers into Kconfig/CMake.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
clock_monitor_set_source() is declared as a __syscall and has a
z_impl_ implementation, but clock_monitor_handlers.c never provided
the matching z_vrfy_ shim (and its _mrsh.c include) like the other
four syscalls do. With CONFIG_USERSPACE=y the generated syscall
table falls back to the unimplemented-syscall handler, so a user
mode caller of clock_monitor_set_source() faults instead of being
dispatched.
Add the verifier mirroring the other optional op (get_rate): check
the device via K_SYSCALL_DRIVER_CLOCK_MONITOR() and forward the two
scalar cookies to z_impl_clock_monitor_set_source().
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
SBS_GAUGE_CMD_AVG_CURRENT returns a 16-bit signed integer (in mA,
negative when discharging). Cast tmp_val to int16_t before
multiplying by 1000 so negative values are properly extended to
int32_t instead of producing large positive uA values.
Assisted-by: Antigravity:gemini-3.6-flash
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
STM32MP13 has the possibility to use timers IP such as other MCUs
already upstreamed in the project.
Add the necessary clock support to handle it.
STM32_SRC_TIMPCLKx index has been chosed as 1,2 and 6 to match
with the APBx clock used for each timers.
Then we distinguish 3 groups of timers, each one corresponds to
one APB clock used for the timers. In the LL, they are noted as
LL_RCC_TIMG1PRES, LL_RCC_TIMG2PRES and LL_RCC_TIMG3PRES.
We so make the following assocations:
Group 1 - From TIM2 to TIM7:
Use APB1 --> STM32_SRC_TIMPCLK1 --> LL_RCC_TIMG1PRES
Group 2 - For TIM1 and TIM8:
Use APB2 --> STM32_SRC_TIMPCLK2 --> LL_RCC_TIMG2PRES
Group 3 - From TIM12 to TIM17:
Use APB6 --> STM32_SRC_TIMPCLK6 --> LL_RCC_TIMG3PRES
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
In order to prepare the Timers integration of STM32MP13,
this driver needs to be changed a bit.
Indeed, NVIC functions are called by default at some places but
MP13 is cortex A and uses GIC as interrupt controller.
Get inspired by renesas and nxp drivers to add GIC support
in STM32 one.
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
The read branch stored CAT1_I2C_PENDING_TX, copied from the write
branch; CAT1_I2C_PENDING_RX was never used. Store the RX state.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The read branch stored CAT1_I2C_PENDING_TX, copied from the write
branch; CAT1_I2C_PENDING_RX was never used. Store the RX state.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a driver for the Analog Devices / Trinamic TMC6460, a fully
integrated Field-Oriented Control (FOC) gate driver for brushless DC
(BLDC) and PMSM motors. The device is not a microstepping stepper, so it
lives under drivers/misc and exposes a small device-specific
register-access API rather than a shared DEVICE_API:
- tmc6460_read / tmc6460_write raw 32-bit register access
- tmc6460_rtmi_stream_write UART fire-and-forget stream write
- tmc6460_enable / tmc6460_disable gate-driver DRV_EN control
- tmc6460_poll_flag reusable status-bit wait helper
- tmc6460_field_update / _field_write bitfield helpers
The chip exposes 32-bit registers in a 10-bit address space and supports
both SPI and UART transports. SPI access uses fixed 48-bit datagrams;
the UART transport uses variable-length datagrams with the TMC6460 CRC8
framing (custom reflected polynomial) and tolerates interleaved RTMI
telemetry packets on the read path. The transport is selected from
devicetree via the bus the node is attached to.
The public header carries the full TMC6460 register map and the reset
values used by the sample for self-validation.
Signed-off-by: Cherrence Sarip <cherrence.sarip@analog.com>
- Adds support for pic32cm jh family
- Adds new logic for eic line mapping to the port and pin
- Adds new ISR for devices with a single IRQ line in NVIC for interrupt
controller
Signed-off-by: Muhammed Asif <asifp3104@gmail.com>
The GICv1/v2 driver (intc_gic.c) has two bugs in AMP configurations
where each core runs an independent Zephyr instance:
1. CPU target mask derivation: gic_dist_init() derived the CPU target
mask from the DTS cpu_mpid_list array. In AMP mode each core's DTS
typically only defines cpu@0, so Core 1's physical CPU interface bit
was never set in GICD_ITARGETSRn. A new gic_get_cpu_mask() helper
reads the hardware-banked GICD_ITARGETSR[0], which returns the
running core's actual target bit regardless of what the DTS defines.
2. Destructive re-initialization: arm_gic_init() on the second core
unconditionally disabled the distributor (GICD_CTLR=0) and
overwrote all SPI enables, priorities, and target registers,
clobbering the first core's configuration. Add the
CONFIG_GIC_SAFE_CONFIG guard to gic_dist_init(): if the distributor
is already enabled (GICD_CTLR bit 0 set), return early. Per-SPI
affinity for the new core is handled by arm_gic_irq_enable(), which
ORs the local CPU mask into the existing SPI target register without
disturbing other cores.
Additionally:
- Extend CONFIG_GIC_SAFE_CONFIG from GICv3-only to all GIC versions
(change Kconfig dependency from GIC_V3 to GIC).
- When CONFIG_GIC_SAFE_CONFIG is enabled, clear all SPI targets during
distributor init and let arm_gic_irq_enable() add each core's mask on
demand.
Tested on AMD Versal VCK190 (Cortex-R5 dual-core split mode):
- SGI delivery to both cores: PASS
- SPI delivery via 1-of-N with GICD_ITARGETSRn=0x03: PASS
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Updated spi_xec_qmspi_ldma driver with low power support.
Add a pm_action handler that clears MODE.ACTV and applies the
pinctrl sleep state on suspend, and reverses both on resume.
Hold a PM_STATE_SUSPEND_TO_IDLE policy lock for the duration of
each transfer (sync and async) so suspend cannot enter mid-
transaction.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Place BG9x and BC66x drivers under a shared quectel directory
and add dedicated CMakeLists.txt files for each modem family.
Update Kconfig paths and build definitions accordingly.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
Add support for configuring the target device at runtime.
Tested with:
- $i3c config_get target i3c@f03d00
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Newer it51xxx socs support the automatic IBI response mechanism.
Add driver support to configure and use this hardware feature.
Tested with: tests/subsys/pmci/mctp/i3c/
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Fix the compile error by replacing the removed `address` member
in `struct i3c_target_config` with `dynamic_addr` member in
`struct i3c_config_target`.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The GPDMA ownership register is a 16-bit MMIO register. Using
sys_write32() triggers a load/store width exception under LLVM strict
alignment checking. Replace with sys_write16() to match the actual
register width.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
The 12-hour read path added decimal 12 to the still-BCD hour value
before converting, producing wrong afternoon hours (8 PM decoded as
14). Convert from BCD first, then add the PM offset.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
DS3231_BITS_CTRL_CONV was defined as BIT(6), colliding with BBSQW;
the temperature-conversion bit is bit 5 in the control register, as
the RS2/RS1 positions below it confirm.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The charge calibration extracted its two LSBs with the discharge mask
(bits 1:0) instead of the charge mask (bits 3:2), skewing charging
current readings.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add an Ethernet-over-mesh network interface, gated by
CONFIG_WIFI_ESP32_MESH_IP, so the Zephyr IP stack runs over the
mesh. The IP-level policy is left to the application.
The interface and the raw mesh send and receive API both drain
the single mesh receive queue, which has no demultiplexing, so
they are mutually exclusive at build time. Folding both into one
reader that switches on the frame protocol tag would let them
coexist.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the Kconfig options and driver plumbing for the Espressif
Wi-Fi mesh stack. The mesh id, channel, credentials, tree limits
and node role are configurable.
The mesh stack owns both interfaces while it runs, so the
station and softAP management operations are rejected with
-EBUSY rather than left to fight it. Mesh is a boot-time mode
with no runtime teardown, which the API documents.
Bring-up waits for the stack to report that it started before
re-delivering the initial station-start event the mesh missed,
instead of assuming a fixed delay is enough.
A fixed root keeps the self-organized behavior when a router is
configured, since that is what drives its association to the
router and the reconnection that maintains the uplink. Only a
router-less fixed root stops the parent search, which would
otherwise scan for a parent that does not exist and disrupt its
softAP.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Run the Wi-Fi and mesh event handlers on a dedicated task rather
than on the Wi-Fi library task, so a handler cannot overrun or
stall it. This applies to the station and softAP paths as well,
not only to mesh: handler work is decoupled from the library
task everywhere. The task stack, priority and queue depth are
configurable.
Delivery is asynchronous, so a caller that must observe a state
change synchronizes on the event instead of reading the state
right after the call returns. A full queue drops the event and
logs at error level; the depth is sized for the bursts a mesh
re-parent or softAP client churn produces.
Each entry carries an inline copy of the payload, so the buffer
is sized at 64 bytes: enough for every event handled here, whose
largest payload is 48 bytes, with margin for a vendor struct
that grows. A build assertion checks the handled event sizes
against it, turning such a growth into a compile error instead
of a runtime drop. An event too large for the buffer is rejected
rather than delivered without its data, so a handler is never
invoked with a null payload it expects to dereference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Commit bbda65a ("drivers: counter: increase COUNTER_INIT_PRIORITY")
raised COUNTER_INIT_PRIORITY from KERNEL_INIT_PRIORITY_DEVICE (50) to
60 to guarantee counter devices initialize before bus-dependent devices
sharing the same default priority.
Revert to KERNEL_INIT_PRIORITY_DEVICE and remove the BUILD_ASSERT in
the RTC counter driver that enforced RTC_INIT_PRIORITY >
COUNTER_INIT_PRIORITY, as both now default to the same value with
ordering guaranteed by DT sub-priority.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
The current driver is prepared for the SAM4 which has a
8-bit interface only. This commit adds optional config
to support also 16-bit interfaces for the SAME7 family.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Pieter De Gendt <pieter.degendt@gmail.com>
Allow the CH32V QingKe systick timer driver to be selected on the CH32H41X
series. The systick register layout (CTLR/SR/CNT/CMP) is identical to the
existing QingKe parts, so no driver code change is needed; only the Kconfig
dependency has to be extended.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add a pinctrl driver for the CH32H41x AFIO block. Unlike the CH32V20x/30x
remap (PCFR) model, the CH32H41x selects pin alternate functions through
a per-pin 4-bit field in the AFIO GPIOx_AFLR/AFHR registers (STM32-style
mux), in addition to the usual GPIO CFGLR/CFGHR direction and bias
configuration.
The driver is gated by CONFIG_PINCTRL_WCH_H41X_AFIO (default y when the
wch,h41x-afio node is enabled) and is wired into the pinctrl CMakeLists
and Kconfig alongside the existing WCH AFIO drivers.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Extend the WCH RCC clock driver for the CH32H41X series. Add the H41X
PLL binding and SoC clock node, handle the H41X clock-enable register
names and FPRE prescaler, and implement the 480 MHz SYSCLK and
120 MHz HCLK bring-up sequence.
Select the H41X-specific path from the RCC source compatible in
devicetree. Existing CH32V00X, CH32V20X, and CH32V30X configurations
remain unaffected.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add the CH32H41X SoC series under the ch32v family. The CH32H417 is
an asymmetric dual-core (AMP) RISC-V part with a QingKe V3F boot
core and a QingKe V5F application core.
Model the two cores as cpuclusters with separate CPU descriptions,
runtime-idle power states, interrupt entry, vector handling, and
non-overlapping memory. Keep the external HSE frequency
board-specific.
The optional SOC_CH32H417_BOOT_V5F setting lets the V3F early-init
hook wake the V5F image at its real flash address, 0x08010000, while
allowing standalone V3F applications to disable that behavior.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
