drivers: net: phy: Add tja11xx driver
Adds the c22 tja11xx driver. Signed-off-by: Kevin Shaju <kevin.shaju@accenture.com>
This commit is contained in:
Kevin Shaju
Dan Kalowsky
parent
67edf2292a
commit
7e56d134c2
6 changed files with 309 additions and 1 deletions
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@ -13,5 +13,6 @@ zephyr_library_sources_ifdef(CONFIG_PHY_QUALCOMM_AR8031 phy_qualcomm_ar8031.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_REALTEK_RTL8211F phy_realtek_rtl8211f.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83825 phy_ti_dp83825.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83867 phy_ti_dp83867.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TJA1103 phy_tja1103.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TJA1103 phy_tja1103.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TJA11XX phy_tja11xx.c)
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# zephyr-keep-sorted-stop
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@ -14,6 +14,7 @@ module-dep = LOG
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module-str = Log level for Ethernet PHY driver
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module-help = Sets log level for Ethernet PHY Device Drivers.
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source "subsys/net/Kconfig.template.log_config.net"
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source "drivers/ethernet/phy/Kconfig.tja11xx"
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source "drivers/ethernet/phy/Kconfig.tja1103"
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source "drivers/ethernet/phy/Kconfig.dm8806"
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source "drivers/ethernet/phy/Kconfig.microchip_t1s"
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12
drivers/ethernet/phy/Kconfig.tja11xx
Normal file
12
drivers/ethernet/phy/Kconfig.tja11xx
Normal file
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@ -0,0 +1,12 @@
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# NXP PHY TJA11xx driver configuration options
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PHY_TJA11XX
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bool "TJA11XX PHY driver"
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default y
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depends on DT_HAS_NXP_TJA11XX_ENABLED
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depends on MDIO
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help
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Enable TJA11xx PHY driver.
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254
drivers/ethernet/phy/phy_tja11xx.c
Normal file
254
drivers/ethernet/phy/phy_tja11xx.c
Normal file
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@ -0,0 +1,254 @@
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/*
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* Copyright 2023 NXP
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* Copyright 2023 CogniPilot Foundation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_tja11xx
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#include <errno.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/net/mii.h>
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#include <zephyr/net/mdio.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(phy_tja11xx, CONFIG_PHY_LOG_LEVEL);
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/* Extended control register */
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#define TJA11XX_EXTENDED_CONTROL 0x0017U
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/* Configuration register 1 */
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#define TJA11XX_CONFIGURATION_1 0x0018U
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struct phy_tja11xx_config {
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const struct device *mdio;
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uint8_t phy_addr;
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};
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struct phy_tja11xx_data {
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const struct device *dev;
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struct phy_link_state state;
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struct k_sem sem;
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phy_callback_t cb;
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void *cb_data;
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struct k_work_delayable monitor_work;
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};
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static inline int phy_tja11xx_c22_read(const struct device *dev, uint16_t reg, uint16_t *val)
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{
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const struct phy_tja11xx_config *const cfg = dev->config;
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return mdio_read(cfg->mdio, cfg->phy_addr, reg, val);
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}
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static inline int phy_tja11xx_c22_write(const struct device *dev, uint16_t reg, uint16_t val)
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{
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const struct phy_tja11xx_config *const cfg = dev->config;
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return mdio_write(cfg->mdio, cfg->phy_addr, reg, val);
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}
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static int phy_tja11xx_reg_read(const struct device *dev, uint16_t reg_addr, uint32_t *data)
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{
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const struct phy_tja11xx_config *cfg = dev->config;
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int ret;
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mdio_bus_enable(cfg->mdio);
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ret = phy_tja11xx_c22_read(dev, reg_addr, (uint16_t *)data);
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mdio_bus_disable(cfg->mdio);
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return ret;
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}
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static int phy_tja11xx_reg_write(const struct device *dev, uint16_t reg_addr, uint32_t data)
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{
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const struct phy_tja11xx_config *cfg = dev->config;
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int ret;
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mdio_bus_enable(cfg->mdio);
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ret = phy_tja11xx_c22_write(dev, reg_addr, (uint16_t)data);
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mdio_bus_disable(cfg->mdio);
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return ret;
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}
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static int update_link_state(const struct device *dev)
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{
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struct phy_tja11xx_data *const data = dev->data;
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bool link_up;
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uint16_t val;
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if (phy_tja11xx_c22_read(dev, MII_BMSR, &val) < 0) {
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return -EIO;
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}
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link_up = (val & MII_BMSR_LINK_STATUS) != 0;
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/* Let workqueue re-schedule and re-check if the
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* link status is unchanged this time
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*/
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if (data->state.is_up == link_up) {
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return -EAGAIN;
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}
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data->state.is_up = link_up;
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return 0;
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}
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static int phy_tja11xx_get_link_state(const struct device *dev, struct phy_link_state *state)
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{
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struct phy_tja11xx_data *const data = dev->data;
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int rc = 0;
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k_sem_take(&data->sem, K_FOREVER);
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memcpy(state, &data->state, sizeof(struct phy_link_state));
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k_sem_give(&data->sem);
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return rc;
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}
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static void invoke_link_cb(const struct device *dev)
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{
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struct phy_tja11xx_data *const data = dev->data;
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struct phy_link_state state;
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if (data->cb == NULL) {
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return;
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}
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/* Send callback only on link state change */
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if (phy_tja11xx_get_link_state(dev, &state) != 0) {
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return;
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}
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data->cb(dev, &state, data->cb_data);
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}
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static void monitor_work_handler(struct k_work *work)
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{
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struct k_work_delayable *dwork = k_work_delayable_from_work(work);
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struct phy_tja11xx_data *const data =
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CONTAINER_OF(dwork, struct phy_tja11xx_data, monitor_work);
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const struct device *dev = data->dev;
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int rc;
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k_sem_take(&data->sem, K_FOREVER);
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rc = update_link_state(dev);
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k_sem_give(&data->sem);
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/* If link state has changed and a callback is set, invoke callback */
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if (rc == 0) {
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invoke_link_cb(dev);
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}
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/* Submit delayed work */
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k_work_reschedule(&data->monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
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}
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static void phy_tja11xx_cfg_irq_poll(const struct device *dev)
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{
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struct phy_tja11xx_data *const data = dev->data;
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k_work_init_delayable(&data->monitor_work, monitor_work_handler);
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monitor_work_handler(&data->monitor_work.work);
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}
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static int phy_tja11xx_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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ARG_UNUSED(dev);
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if (adv_speeds & LINK_FULL_100BASE) {
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return 0;
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}
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return -ENOTSUP;
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}
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static int phy_tja11xx_init(const struct device *dev)
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{
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struct phy_tja11xx_data *const data = dev->data;
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int ret;
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data->dev = dev;
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data->cb = NULL;
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data->state.is_up = false;
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data->state.speed = LINK_FULL_100BASE;
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ret = phy_tja11xx_reg_write(dev, TJA11XX_EXTENDED_CONTROL, 0x1804);
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if (ret < 0) {
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return ret;
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}
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ret = phy_tja11xx_reg_write(dev, MII_BMCR, 0x2100);
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if (ret < 0) {
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return ret;
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}
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ret = phy_tja11xx_reg_write(dev, TJA11XX_CONFIGURATION_1, 0x8A00);
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if (ret < 0) {
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return ret;
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}
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ret = phy_tja11xx_reg_write(dev, TJA11XX_EXTENDED_CONTROL, 0x9804);
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if (ret < 0) {
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return ret;
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}
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phy_tja11xx_cfg_irq_poll(dev);
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return ret;
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}
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static int phy_tja11xx_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
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{
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struct phy_tja11xx_data *const data = dev->data;
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data->cb = cb;
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data->cb_data = user_data;
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/* Invoke the callback to notify the caller of the current
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* link status.
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*/
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invoke_link_cb(dev);
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return 0;
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}
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static const struct ethphy_driver_api phy_tja11xx_api = {
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.get_link = phy_tja11xx_get_link_state,
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.cfg_link = phy_tja11xx_cfg_link,
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.link_cb_set = phy_tja11xx_link_cb_set,
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.read = phy_tja11xx_reg_read,
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.write = phy_tja11xx_reg_write,
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};
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#define TJA11xx_INITIALIZE(n) \
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static const struct phy_tja11xx_config phy_tja11xx_config_##n = { \
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.phy_addr = DT_INST_REG_ADDR(n), \
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.mdio = DEVICE_DT_GET(DT_INST_BUS(n)) \
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}; \
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static struct phy_tja11xx_data phy_tja11xx_data_##n = { \
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.sem = Z_SEM_INITIALIZER(phy_tja11xx_data_##n.sem, 1, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(n, &phy_tja11xx_init, NULL, &phy_tja11xx_data_##n, \
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&phy_tja11xx_config_##n, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY, \
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&phy_tja11xx_api);
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DT_INST_FOREACH_STATUS_OKAY(TJA11xx_INITIALIZE)
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@ -30,6 +30,33 @@
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(124)>;
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};
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enet: ethernet@40079000 {
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compatible = "nxp,enet";
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reg = <0x40079000 0x628>;
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clocks = <&clock NXP_S32_ENET_CLK>;
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enet_mac: ethernet {
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compatible = "nxp,enet-mac";
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interrupts = <73 0>, <74 0>, <75 0>;
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interrupt-names = "TX", "RX", "ERR";
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nxp,mdio = <&enet_mdio>;
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nxp,ptp-clock = <&enet_ptp_clock>;
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phy-connection-type = "rmii";
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};
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enet_mdio: mdio {
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compatible = "nxp,enet-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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enet_ptp_clock: ptp_clock {
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compatible = "nxp,enet-ptp-clock";
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interrupts = <72 0>;
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clocks = <&clock NXP_S32_ENET_CLK>;
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};
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};
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};
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};
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13
dts/bindings/ethernet/nxp,tja11xx.yaml
Normal file
13
dts/bindings/ethernet/nxp,tja11xx.yaml
Normal file
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@ -0,0 +1,13 @@
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# Copyright 2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: TJA11xx PHY
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compatible: "nxp,tja11xx"
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include: phy.yaml
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properties:
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reg:
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required: true
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description: PHY address
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