Byte value written to the device's
ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER
Sets the devices receive packet filter, optional. If not set
in device tree previous hard coded value`0xA3` is used.
Uni, multi and broadcast packets with valid CRC are accepted.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
This will update host dma copy aligmnet as with current
high value in some cases it was not possible to fully
empty the buffer
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
MODEM_UBX: Adds Support for UBX Messages in Modem Subsystem.
GNSS API Supported: get_supported_systems, set_fix_rate, get_fix_rate,
set_enabled_systems, get_enabled_systems, set_navigation_mode,
get_navigation_mode.
Boards Tested: MIMXRT1062_FMURT6, VMU_RT1170.
Note: Partial support for U-BLOX Messages is provided as of now.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Signed-off-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
The STTS22H is an ultralow-power, high-accuracy, digital temperature
sensor offering high performance over the entire operating temperature
range. This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/resource/en/datasheet/stts22h.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add ability to set a wakeup counter in case OS Timer is
disabled in certain low power modes. Also add code to
compensate the tick value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Enables usage Bluetooth LE GATT as a serial endpoint to exchange data
using UART APIs. This implementation is compatible with UART Interrupt
Driven APIs and uses the nus-uart device-tree node properties to
configure FIFO buffers for transmitting and receiving. Defining
multiple instances of the driver is possible and it allows implementing
multiple GATT NUS service instances to exchange data as separate serial
endpoints.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
"RW pinctrl" is clearly SOC specific naming for an IP
that is not necessarily constrained to live on one SOC series.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There were missing global dppic and ipct channels configuration
that allows to deliver events from global peripherlas like GRTC
to Radio domain.
Add missing configuration to nrf54h20 dtsi file.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The GRTC channels and irqs configuration for Radio domain
is SOC specific not board specific. Move the configuration
to SOC dtsi file.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The child-owned-channels property of GRTC is used by nrfx_grtc
driver to exclude channels for common pool of channels allowed
for dynamic allocation. That is sort-of workaround for missing
property that allowes to remove some channels from the pool.
There are also not aligned GRTC IRQs for nRF54H20 and nRF54L15.
Only one of avaialbe IRQs was added to GRTC in DTS whereas
there should be two. That allows to find second IRQ by other
drivers that use GRTC peripehral.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Split up the driver for the PWM controller MAX31790
into a multi function device driver.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the Audio Link Hub (ALH) nodes from the ACE 2.0 LNL DTS file.
This patch cleans up the Device Tree Source by removing the individual
ALH stream/FIFO nodes. The ALH hardware is not present in the ACE 2.0
architecture, and these nodes are therefore not applicable.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain definitions for the Intel ADSP ACE
2.0 LNL (Lunarlake) platform in the Device Tree Source (DTS).
Changes include:
- Removing the definitions for io2_domain, io3_domain, and ml1_domain,
which are no longer present in the ACE 2.0 LNL configuration.
- Renaming and reassigning bit positions to existing power domains to
reflect the updated power management architecture.
The reordering ensures that the DTS reflects the current power domain
architecture of the ACE 2.0 LNL platform, facilitating accurate power
management within the SoC.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Changing the power domain from 'hst_domain' to 'io0_domain' for the HDA
DMA link in/out nodes. This aligns the power domain assignments with the
actual hardware configuration and ensures that the power management
subsystem can accurately manage the power states of these interfaces.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain node definitions in the ACE 1.5
Meteorlake DTS file to improve readability and facilitate comparison with
the documentation.
Changes include:
- Reordering power domain nodes by their bit positions.
- No changes to the bit positions themselves; they remain as originally
defined.
This reordering does not affect the functionality but makes the DTS file
more maintainable and easier to cross-reference with the hardware
specification.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Some SAI instances are mutliline, meaning they can have multiple
TX/RX data lines (channels). Depending on the board, the index
of the TX/RX data lines that are connected to the consumer
(e.g: the codec) may not always be 0. This commit fixes this
issue by adding support for passing the index of the used
TX/RX data lines through the DTS.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add definition of the nRF54H20 SoC with its Application, Radio,
and Peripheral Processor (PPR) cores and an initial set of
peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make the properties for setting the initial sample points for both the
classic/arbitration phase and the data phase optional.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Implement a sensor for the output diagnostics of the low side
switch BD8LB600FS.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Split up the driver for the low side switch BD8LB600FS into a GPIO
and MFD part.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This binding is for the NXP FlexComm Interface. The
driver will setup an interface for use as a UART, SPI
or I2C device.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
These list of files add basic support for StarFive
JH7110 SOC Device Tree includes for VisionFive2
board.
Signed-off-by: Pratik Farkase <pratik.farkase@wsisweden.com>
Split the common keyboard scanning code out of the XEC specific driver
and use the generic code instead.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert the XEC keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This is a follow-up to commit 4db40601dd.
There are two ECB instances in nRF54H20 and the above commit added
only one of them.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
And add the corresponding bindings.
Move alse the already existing bindings for nrf-dppic, nrf-ppi,
and nrf-ipc so they are located together with the new ones and
in more appropriate folders (DPPIC and PPI peripherals are not
related to ARM, and IPC is for sending and receiving events,
not messages, so ipm/ does not seem to be the best fit for it).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enabling peripherals at SoC dts files should not be done, unless there
are good reasons (e.g. always needed peripherals). NFCT node should
either be enabled at board level, or, at application level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Some CAN transceivers have a lower limit on their supported bitrate. Add an
optional "min-bitrate" for specifying this limit via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The pit had a few warnings about
the format of the register address
being uppser case and one of the
reg index values were incorrect.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
This commit enables the IRQSTEER interrupt controller
on NXP's XTENSA-based i.MX8QM and i.MX8QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Define the MPU attribute to be ATTR_MPU_EXTMEM for the
external region (qspi- or octo-spi NOR flash)
starting at 0x90000000 of the stm32h7 serie.
A XiP region should be Included inside with attribute
ATTR_MPU_IO, to access the external memory in XIP.
The stm32h7a/h7b serie as another external area at 0x70000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add Nuvoton numaker series flash memory controller(RMC) with erase,
read & write features of soc-flash.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add Open Alliance spi protocol support.
Open Alliance is a chunk-based SPI protocol, based on sending
over SPI an ethernet frame divided in smaller chunks, using a
specific 32-bit header for each chunk transferred. All chunks
can be sent or received by a single dma transfer.
Default mode is set to Open Alliance SPI without protection,
since the adin2111 dev. board comes shipped this way.
Tested:
- Open Alliance SPI, no protection (default board shipped)
- Open Alliance SPI, protection
- Generic SPI, no crc
- Generic SPI, with crc8
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Define a single node that reflects the LCDC IP. Instead of defining
the same IP block twice with different compatibles (mipi dbi, display)
we define a single node for the default display interface and
other interfaces like the MIPI DBI should override the compatible entry
with the appropriate one within its DTS overlay file.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Exhibit Renesas LCD controller's driver implementation. The driver
is intended to employ the controller in the continuous mode so
it can drive display panels in the parallel RGB mode.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
The MRAM has no concept of erase blocks or pages, so this is treated as
driver configuration.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Enabled the PIT and Multi channel support
for some of the rtXXXX devices.
- rt1010
- rt1060
- rt1160
- rt1170
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Updating the nxp,pit driver to support mutliple
channels. Updating the dts and board overlays
to account for the changes.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add a new binding that should help with samples or MBOX tests by getting
information from DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
For sharing pin definition property with `worldsemi,ws2812-gpio`,
rename `output-pin` to `gpios`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
ws2812-gpio's `in-gpios` property is not used as an input pin.
Renaming it to `gpios` to reflect the actual situation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
By default N_VBUSEN signal is used by the host to define if VBUS
signal should be used for power supply (VBUS-IPSOUT).
This feature enables the possbibility to change this behaviour.
When N_VBUSEN detection is disabled, axp192 will automatically
decide to use VBUS (REG10H[7] = 1).
Please refer to datasheet for details.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
AXP192 features an EXTEN pin that is on output only.
This commit appends control of EXTEN pin to gpio functionality
of AXP192.
Port-Mapping is as follows:
- [0..4]: GPIO0..4
- [5]: EXTEN
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
This adds the minimal get_time/set_time support for the rp2040 and
enables support by default on the Pico boards. This doesn't support
configuring the clock source or alarm interrupts yet.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Utilization of chip interrupt line is mandatory to assure proper
charger state control. Handle interrupt to prepare the driver for
implementation of such functionality.
Modify charger status update so the current state is fetched in the
interrupt handler.
Use level based interrupts combined with interrupt disabling for a
period of time after interrupt handling to reduce number of interrupts
triggered by the charger. There may be a case where the charger
produces burst of interrupts for a several seconds and if the code
attempts to handle every single interrupt separatery then the system
might be significantly overloaded.
Co-authored-by: Bartosz Bilas <b.bilas@grinn-global.com>
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
Add new bindings to describe the BELLBOARD peripheral in its two
_programming modes_ local or remote.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new nodes for PPR's VEVIF. In app cores, VEVIF registers are part
of the VPR peripheral, so it is exposed as a child node (since it
requires its own properties, eg #mbox-cells). In VPR, it's a CPU child
since it's not a memory-mapped peripheral, but used with CSRs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
To allow EDMA configuration with the help of the DT_INST_DMAS_*
and DT_DMAS_* macros, all that a consumer node needs to know
is which channel to configure and what MUX value needs to be
used. As such, this commit allows doing this by forcing the
dma-cells property to 2, each cell representing one of the
aforementioned properties.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
To enable per peripheral queue pool sizing options add some bindings to
the i2c controller to setup sq/cq pool sizing.
Its possible this could go away with a shared application pair of pools.
The shared pool would require some added function pointers though to
deal with the variants as the shared pools would need a lock.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Added is_enabled devicetree property to fake regulator.
Allows testing of init behaviour when regulator is enabled
in hardware.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
On HAL RTD version 1.0.0, there is available Canexcel_Ip_DeactivateMD()
API that have similar capabilities as can_nxp_s32_abort_msg() API,
can use to instead.
Remove the reg grp_ctrl and reg base_dsc_ctrl that unused
after implementation this.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Do not enable Standby low-power mode by default since the associated
Kconfig PM_S2RAM is disabled by default. Otherwise we could enter an
unsupported low-power state.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add devicetree based settings for resolution, axis inversion and sleep
mode enable. Keep the resolution setting in its own function so it can
be called by the application again in runtime if needed.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The nRF91 series devices, when running the Serial LTE Modem (SLM)
application starting with nRF Connect SDK 2.6.0, can now be used as
standalone modems via the generic modem_cellular driver.
A configuration to run the cellular_modem sample on the nRF9160 DK
(plugged in to another nRF91 series device running SLM) is provided.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
Add memory-region to nordic,nrf-spis binding. This commit aligns SPIS
shim to utilize memory-region property. This optional property enables
user to specify placement of dma buffers in memory region. It is done
by assigning to memory-region property, phandle to node with
zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given device, buffer
is placed in default RAM region with other data.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add an initial input driver for the PixArt PAT9125EL, just core
functionalities for now, will add more configuration properties at a
later stage.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This adds additional memory region property
to NFCT peripheral. This is not mandatory
property, it adds possibility to user to
specify memory region for DMA transfer.
If it is not set then data buffer is placed
in default RAM with other data.
Signed-off-by: Kamil Gawor <Kamil.Gawor@nordicsemi.no>
Signed-off-by: Dominik Chat <dominik.chat@nordicsemi.no>
This is a setting that depends on the board or application, so it should
not be part of SoC definition files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit introduces a driver for ADC keys, a common circuit design where
keys are connected to an ADC input via a resistor ladder.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add driver for ScioSense ENS160 multi-gas sensor. The driver includes
support for I2C and SPI, attributes for setting temperature and
humidity compensation and data ready trigger.
Also add ScioSense to the list of vendor prefixes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add clarifications to mipi-dbi bindings to avoid the confusion
between two options, write-only and duplex.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Unlike SPI nodes, I2C nodes (i2c20, i2c21, i2c22 and i2c30) did not have
this required property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove pinctrl from device tree since it is not required
when internal oscillator is used.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add FlexSPI clock source to RT1010 devicetree definition for FlexSPI
node, to match FlexSPI clock source defined on standard FlexSPI dt node
that is removed in the RT1010 devicetree.
Fixes#68488
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
... so that there is no need to include that header individually
for every added board based on an nRF SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
... so that it can be included by ARM and RISC-V cores. For the same
reason, SysTick can no longer be disabled in this common file.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor. The size Property becomes useless.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor. The size Property becomes useless
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
GR716A has two SPIMCTRL SPI controllers.
This adds the SPIMCTRL description to the DTS and makes the SPI
option available in the kernel configuration.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Setup rx-clock-source for XIP flash. When running from RAM, the FLEXSPI2
attached SIP flash will be reconfigured, so we must ensure the
configuration used for it is valid.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2de12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Add a new #nordic,ficr-cells property, so that we can specify a FICR
offset in a phandle-array, e.g.
nordic,ficrs = <&ficr 0xff>;
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The `timebase-frequency` is not defined by any of the YAML binding files.
There was a discussion in #37420 to add this property, but in the end it
was rejected. This resulted in the #37685 feature request being created.
As of now, this property is not documented anywhere so this commit removes
it from the RISC-V devicetrees, as RISC-V is the only architecture that is
currently defining it - and even in RISC-V not all platforms do that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/adc and arm.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/bluetooth, can, dac and display.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/net, power-domain, pwm and qspi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/retained_mem, rng, serial and spi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/timer, usb-c, usb and watchdog.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/pinctrl directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/dma directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/sensor directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/clock directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Create a folder for RZ Renesas range device tree to follow how it's
done for other renesas ranges.
It will also help to better delimit areas to maintain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Provide jtag port pins description, so they can be used to be set in
analog mode when not required to save power (around 40uA saved in total).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
In some hardware designs it might happen that the reset signal
for the TLE9104 is not used only for this purpose, but instead for
instance to reset other devices at the same time. For such a hardware
design it is then necessary to make the reset GPIO optional. The reset
will have to be triggered earlier on.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This implements the daisy chain feature of the low side switch
BD8LB600FS. The daisy chaining is in hardware achieved via
connecting the MISO and MOSI lines of multiple instances of the IC
in a row. It is implemented in the driver through a variable number
of GPIOs on one instance. Therefore, one device tree instance of the
IC will handle multiple daisy chained physical instances.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit adds source and header files required for bmp581 I2C driver.
I have used bmp581_user.h to add more usage related definitions
but bmp581.h to add hardware related definitions.
Signed-off-by: Talha Can Havadar <havadartalha@gmail.com>
Signed-off-by: Gerhard Jörges <joerges@metratec.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
Many sensors have multiple functions, for example, icm42688 supports
accel, gyro and temperature, and the sensor streaming api always mixes
the multiple functions in one function call. So we need add a layer in
sensing subsystem to dispatch the result returned from sensor streaming
api for each function.
I changed the sensor-type(int) to sensor-types(array) in sensing sensor
device bindings, so that one device can map to multiple instances of
sensing sensor.
Signed-off-by: Zhang Lixu <lixu.zhang@intel.com>
Add hinge angle virtual sensor for sensing subsystem, hinge angle sensor
takes both base accel and lid accel as reporter.
Signed-off-by: Zhang Lixu <lixu.zhang@intel.com>
This commit introduces a driver for NXP's eDMA IP.
The main reasons for introducing a new driver are the following:
1) The HAL EDMA wrappers don't support well different
eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
revision had to be introduced, thus requiring a new Zephyr
driver.
2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
don't use the DMAMUX IP (instead, channel MUX-ing is performed
through an eDMA register in the case of i.MX93).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit updates the driver to use the flash layout pages,
rewriting it to utilize the flash_page_layout.c driver to
avoid duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
This commit adds layput page cells to the atmel sam flash
controller and the flash node. These allow for describing
the actual flash page layout of each soc, allowing the
flash driver to fully utilize the capabilities of the
flash.
With this update, we unlock the following capabilties:
- utilize 2048 erase block size for small sectors
- utilize 16384 erase block size for large sectors
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Change the gpio_qdec driver to support optical encoders.
Add a property to use for defining an arbitrary number of GPIOs for the
sensing devices (typically infrared LEDs, but could also be the
biasing for the phototransistor), and one for adding a delay between
turning those on and reading the pin status.
The infrared LEDs typically consume a non negligible amount of power, so
there's also a new idle-poll-time-us property that enables two possible
modes of operation:
- if idle-poll-time-us is zero (default) the LEDs are enabled all the
time and the driver enters polling mode using the GPIO interrupt as
with mechanical encoders. This is usable for mains powered devices and
has the lowest overhead on the CPU.
- if idle-poll-time-us is non zero, then the driver polls the encoder
all the time, turning on the LEDs just before reading the state and
shutting them off immediately after, but when the encoder is idle it
switches the polling rate to idle-poll-time-us to save power, and only
polls at sample-time-us when some movement is detected.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added new test for `DT_IRQ_LEVEL` and `DT_INST_IRQ_LEVEL`.
Introduced a new `vnd.cpu-intc` compatible so that we have a
root level interrupt controller that acts as level 1
aggregator, and modified `test_intc` to be level 2 aggregator,
updated test of `DT_IRQN(TEST_I2C_BUS)` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The meaning of txpo is was a bit confusing, as it's an enumeration
rather than a pad number. This confusion extended to the atsamd21_xpro
board using the wrong pins.
This commit adds ASCII-art tables that explain the meaning of rxpo
and txpo on different platforms.
Signed-off-by: Tom Rothamel <tom@rothamel.us>
The max size was determined by looking at the ARCH of the cpu. This really
comes from the ip configuration when generated. Add `max-xfer-size`
property to the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This cleans up the instantiation macro. DBG_COUNTER was also removed
as that appears to be unnecessary. This also allows for if it is a
serial target to be configured from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Adding driver for GC9A01A 240x240 based LCD displays.
Should be working with GC9C01 as well (untested).
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct
asserts when a pin is provided. Note that default is 32, correct for eg
FE310.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Change the synchronization of RMC and GGA NMEA messages from a
timeout to matching their UTC timestamps.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add driver for NXP nx20p3483 power path controller that can be used
to control and protect sink and source path of USB-C connector.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add calls to the PPC API that enables and disables the sink and source
paths in the appropriate USB-C stack states.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add support of voltage control to Renesas PFC driver. Voltage register
mappings have been added to r8a77951 and r8a77961 SoCs.
Allow 'power-source' property for 'renesas,rcar-pfc' node. This property
will be used for configuring IO voltage on appropriate pin. For now it
is possible to have only two voltages: 1.8 and 3.3.
Note: it is possible to change voltage only for SD/MMC pins on r8a77951
and r8a77961 SoCs.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add definition of the DMIC to the RT5xx devicetree, including all
PDM channels.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Add driver for NXP DMIC peripheral. This peripheral is present on the
iMX RT5xx and iMX RT6xx parts, as well as some LPC SOCs. The following
features are supported:
- up to 2 simultaneous channels of L/R PCM data (4 channels are not
supported due to limitations of the DMA engine)
- individual configuration of gain and filter parameters for each DMIC
channel input
The driver has been tested with up to 4 PCM data streams (2 L/R channels),
as well as the MEMS microphones present on the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Extend api test suite to cover the new devicetree macros. This
includes extending the devicetree overlay with two new bindings:
- GPIO device which is also an interrupt controller
- interrupt holder using interrupts-extended to point to both
existing interrupt controller test_intc, and the newly added
GPIO device
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
add Master Inter-Data Idleness and
Master SS Idleness field. That fields
are integers.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
Add RGPIO gpio driver. This driver is used for i.MX93 and i.MX8ULP.
GPIO pinctrl, read/write and interrupt is supported. Runtime mmio
configuration is enabled, so no need for region definition in
mimx9/mmu_region.c
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The wakeup-source is not used by the driver. Most probably this was
inadvertently left when copying the binding from pcf8523 driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Move the nRF comparator devicetree bindings from ADC to sensors, where the
rest of the comparator bindings are placed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add support for M5Stack AtomS3 Lite development board.
The AtomS3 Lite is a smaller version of the AtomS3 that
features only a StatusLED and no LCD display.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
A 1KHz counter is present in the LPC RTC.
Add support for this counter to get better
resolution for certain applications.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
A 1KHz counter is also available inside the NXP LPC RTC
block. Add a binding to support that counter.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit implements `otPlatResetToBootloader` in two ways:
- trigger reset to bootloader using boot mode retention API
- trigger reset to bootloader by triggering GPIO pin (applicable
for nRF52840 Dongle)
Signed-off-by: Maciej Baczmanski <maciej.baczmanski@nordicsemi.no>
Use the common io-channel-cells name "input" instead of "channel" to make
this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is a driver targetting the Bosch BMA 4-series accelerometers. It
has been specifically developed for the BMA422 but should be compatible
with others in that line, excepting the BMA400. Supports key attributes
and async RTIO one-shot operation. I2C operation is supported, with
stubs for a SPI implementation provided for future improvement.
Signed-off-by: Tristan Honscheid <honscheid@google.com>
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.
At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:
tx_sync_mode = <0>;
rx_sync_mode = <0>;
is the same as not specifying any of the properties,
tx_sync_mode = <1>;
rx_sync_mode = <0>;
is the same as:
tx_sync_mode = <1>;
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Some MCU have limitations with GPIO interrupts. Add a polling mode to
the gpio-keys driver to support those cases.
This required a bit of a refactoring of the driver data structure to add
a instance wide data, and move the pin specific pointer in the config
structure.
For polling, reuse the button 0 delayed work so we minimize the resource
waste, the two work handler functions are only referenced when used so
at least those are discarded automatically if no instance needs them.
Fix a bug in the PM structure instantiation as well.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add an input driver to read data from an analog device, such as a
thumbstick, connected to an ADC channel, and report it as an input
device.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver that based on RPI-PICO's PIO feature for ws2812.
This driver can handle WS2812 or compatible LED strips.
The single PIO node can handle up to 4 strips.
Any pins that can be configured for PIO can be used for strips.
I verified the samples/driver/led_ws2812 sample
working with WS2812(144 pcs) led strip using following patches.
- samples/drivers/led_ws2812/boards/rpi_pico.overlay
```
/ {
aliases {
led-strip = &ws2812;
};
};
&pinctrl {
ws2812_pio0_default: ws2812_pio0_default {
ws2812 {
pinmux = <PIO0_P21>;
};
};
};
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
ws2812: ws2812 {
status = "okay";
output-pin = <21>;
chain-length = <144>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
};
};
```
- samples/drivers/led_ws2812/boards/rpi_pico.conf
```
CONFIG_WS2812_STRIP_RPI_PICO_PIO=y
```
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch to using named IRQs as index-based access makes no guarantees about
devicetree interrupt order.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Use the common io-channel-cells name "input" instead of "positive" and
"negative" to make this binding work with the various ADC DT macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is in preparation for xmc4xxx mdio/ethernet patch set. In the
ethernet drivers, the DMA memory (including descriptor and buffers)
must live in dsram1 or dsram2.
Currently, in xmc47_relax_kit the RAM is the psram1 region meaning
that DMA transfers will not work. Switch to using dsram regions instead.
Also, merge dsram1 and dsram2 into a single region since they are
contiguous.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The zephyr-gpio w1 driver introduced in this commit implements
all routines for the w1 api on top of the zephyr gpio driver.
W1 bit read, write, and reset operations are executed by
bit-banging the selected gpio.
Signed-off-by: Hudson C. Dalpra <hudson@bduncanltd.com>
Some STM32F4xx chips have an R division factor in PLL. Add possibility
to configure that.
Even though the output from the R division is not used, it can be
increased to reduce power consumption.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The sci devices described in the device tree source for RA MCUs are
incorrectly specified as being UARTs when they should be SCIs (serial
communication interfaces) which can not only operate as UARTs but also
as I2C, SPI etc.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This commit modifies the I2S driver to work for STM32H7
family of MCU's. Currently only TX is working.
Tested on nucleo_stm32h743zi. Requires dma1 & dmamux1 to be enabled.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
Devices like the ATSAM series chips have retained registers
which are used to store memory. The memory is accessed just
like RAM, but since they are registers, their size and
address is used directly.
This commit adds a near complete copy of the generic retained
ram driver and bindings file, adding the reg property to
the bindings file, and updating the init macro in the driver
to use the reg address and size.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Rename old rpl_crb to rpl_s_crb, which is needed for adding other
Raptor Lake boards. Main changes should be in the board device tree
configuration raptor_lake_p vs raptor_lake_s.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Declare the SRAM0 region as memory-region
for the stm32f745 serie. Will be included for the stm32f746
for the stm32f765 serie. Will be included for the stm32f767
for the stm32f722 serie. Will be included for the stm32f723
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit updates the Ambiq Apollo4x series soc clock frequency
of defined instances to align with context of these dts files.
Signed-off-by: Aaron Ye <aye@ambiq.com>
ESP32 family pinctrl files are currently placed in hal_espressif.
Move to main branch as part of pinctrl dt-bindings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a property to the mdio controller binding to describe the MDC
frequency generated by the controller.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
We might have to do this differently:
Configure rng default clock in .dtsi
Set board specific config in .dts
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SRAM6 is used by RF and should be defined as RAM_NOCACHE
to allow unaligned access reads.
"IO" might be a better match but is not available on this arch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commits create the dts binding for Ambiq BT HCI instance.
And create the SPI based common HCI driver for Ambiq Apollox
Blue SoC and the extended soc driver for HCI.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Add a device driver to read events from a Linux evdev device node and
inject them back as Zephyr input events.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Generic Connector for the apollo4p_evb
Ran tests/drivers/gpio/gpio_basic_api
Ambiq does not support DUAL Edged Interrupts.
Added Connector Usages as defined by the Ambiq BSP.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
USB Audio Class 2 (UAC2) includes a method to describe audio device
topology to host using a set of class specific descriptors. The audio
device description includes complete sample clock topology and audio
processing organization.
Zephyr specific bindings are supposed to allow user to create reasonably
simple audio device description using devicetree syntax. The bindings
currently include only the absolute minimum set required for headset
example. Bindings for other entities (Clock Selector, Clock Multiplier,
Mixer Unit, Selector Unit, Feature Unit, Sample Rate Converter,
variuos Effect Units, various Processing Units, Extension Unit) can be
added later together with the actual USB class implementation.
The main idea is that user does create one zephyr,uac2 compatible node
for every USB Audio 2 class instance. Note that in majority of cases
just one USB Audio 2 class is necessary because the number of streaming
interfaces is virtually unlimited (USB Audio 2 class can have up to 255
entities). The zephyr,uac2 node includes child nodes with compatibles
set to desired entity or audiostreaming interface. The parent-child
relationship is necessary to allow grouping entities to correct audio
class instance.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The gpio_pca953x gpio driver doesn't have
the input latch and interrupt mask
configuration which causes a lack of accessing
and using those features on an gpio expander
device. Fix it by adding input latch and
interrupt mask configurations in this driver.
Signed-off-by: Vudang Thaihai <vudang.thaihai@brillpower.com>
The LIS2DU12 is a linear 3-axis accelerometer with advanced digital
functions whose MEMS and ASIC have been expressly designed to build
an outstanding ultralow-power architecture in which the anti-aliasing
filter operates with a current consumption among the lowest in the
market.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2du12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Add support for enabling the clock security system, which can detect
failures of the HSE clock.
Includes tests for nucleo_h743zi and nucleo_g474re.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
Rename the native Linux SocketCAN driver to reflect that it can can now be
used in both native_posix and native_sim (with or without an embedded
C-library).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Change the name of the node for the lptim used as lowpower
tick source to stm32_lp_tick_source.
Once enabled, this node is known as stm32_lp_tick_source
That will avoid naming the node lptim1 or lptim2 or lptim, etc.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The commit fixes the SHA driver because the ROM API has the following
changes from ES to QS chip:
1. base addres: from 0x13c -> 0x148
2. required SHA context buffer size : from 228 -> 240 bytes
This change also adds a check for the pre-allocated buffer size of the
SHA context when the driver initiliazes.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add "st,hci-spi-v1.yaml" to represent STMicroelectronics SPI protocol V1
which is used by BlueNRG-MS devices.
Add "st,hci-spi-v2.yaml" to show STMicroelectronics SPI protocol V2
utilized by BlueNRG-1 and successor devices.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add support for uc8175 display driver. uc8175 has a slightly
different command/data length requirements for certain registers,
namely TRES and PTL, compared to uc8176/uc8179
This commit refactors the driver code and such that setting TRES and PTL
registers are now done by function pointers provided by config->quirks,
by the same token as how it is done for setting CDI register
Signed-off-by: Xiao Qin <xiaoq@google.com>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add `compatible` node to Ambiq SoCs, along with secondary common compat,
since they share many similarities.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
- PHY can be set up as rmii but still use 25 MHz MDC, add DT property
value for this case
- Fix KSZ8081 driver spamming phy status in debug level logging,
and fix some other state/logging logic
- Fix PHY driver not rescheduling monitor work if first configuration
fails, change code path to use goto for errors
- Handle case where some phys are not using the gpio pins in phy driver
Make GPIO properties of ksz8081 phy optional since these hardware pins
may be unused on some boards
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.
Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add code to configure and program Lcu, Trgmux and Emios_Icu IPs to
get the the rotations by the motor in radians.
Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Co-authored-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Microchip's PolarFire SoC has a total of 9 contexts associated with the
Platform Interrupt controller (PLIC). the E51 core has a single context
(M Mode), and the application processor U54 cores have two each (M mode
and S mode, respectively)
While we are at it, there are a total of 186 interrupts, not 187.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Microchip's PolarFire SoC (device family name: MPFS) is not specific to
the Icicle Kit. Rename the devicetree sources to be more generic and to
align with Linux and allow for other development boards to adopt.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Add an optional actual-key-mask property to filter out key combinations
that are not implemented in the actual keyboard matrix.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
U-blox SARA-R4 already exists but the behavior is different,
requiring a separate driver instance. For instance, R5 autostarts,
so this commit also adds support for skipping power on pulse.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
Based on stm32wba55, stm32wba55Xg is similar from device tree description
to stm32wba52Xg.
Take the opportunity to fix stm32wba52Xg descriuption scheme which was
missing stm32wba52.dtsi.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Fixes an issue with the register addresses which was caused by a
missing `ranges;` option for the power peripheral
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add a poll and scan mode for the driver. If any of these are set, the
driver does not use the GPIO interrupts to detect when the matrix has to
switch to polling mode. Instead, it keeps polling it all the time,
either by enabling all the columns and poll the rows for activity, or
just keep scanning all the time.
Poll mode is useful if the specific SoC used does not support GPIO
interrupt on all the row GPIOs at the same time, scan mode if it does
not even support selecting all the columns at the same time.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Tweak the polling mode so that the driver never exit polling mode if
poll_timeout_ms is 0. This is useful if the specific driver does not
support idle mode.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit introduces a new interrupt controller driver used
for NXP's IRQ_STEER IP.
Apart from introducing the driver itself, this commit contains
the following changes:
1) Switch i.MX8MP to using the XTENSA core interrupt
controller instead of the dummy irqsteer one.
* this is required because the binding for the
irqsteer driver is no longer a dummy one
(since it's being used by the irqsteer driver).
As such, to avoid having problems, switch to
using another dummy binding.
2) Modify the irqsteer dummy binding such that it
serves the IRQ_STEER driver's needs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This PR set the correct value for the stm32F7 devices.
And change vrefint-cal-addr to <0x1FF07A2A> for stm32F722-F723
soc serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many driver APIs are opting to provide an `emul` driver
implementation that can be used for a number of purposes.
- providing an ideal / model driver for reference
- configurable backends
- seamless integration with device tree
- support for native posix, qemu, and any other board
- fast regression testing of app and library code
Provide an initial set of bindings for `zephyr,dma-emul` devices.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
These were first deprecated in v3.2. We have kept support for them
for as long as we can, but now their presence is causing CI failures
in some configurations. Specifically, using the deprecated 'label'
property is causing a warning which is promoted to an error in some
twister runs. This is blocking other forward progress in the
devicetree API.
I tried to rework the tests to avoid this, but it was too much effort
for the time I had to work on the task. Removing the APIs is therefore
unfortunately the best way forward to unblocking other work.
Re-work the test suite a bit to maintain coverage where we are using
the label property to test other macros.
Add a migration guide section to help with the transition.
Signed-off-by: Martí Bolívar <mbolivar@amperecomputing.com>
The possible settings for the lps22df and lps28dfw sensor are overlapping,
except the Full-Scale mode setting. Threrefore we can change the macros
from LPS22DF_DT_[..] to LPS2xDF_DT_[..].
Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
The LPS28DFW is an ultracompact, piezoresistive, absolute pressure sensor.
Compared to the LPS22DF, the LPS28DFW is waterproof and has a Dual FS
capability and does not have SPI. This commit extends the LPS22DF driver to
be compatible with the LPS28DFW device.
Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
Use the "ambiq,gpio" binding to combine the "ambiq,gpio-bank"
child nodes for Apollo4 Plus soc.
Also update the GPIO driver accordingly.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This Ambiq gpio binding provides the GPIO pin mapping for GPIO child
nodes tosolve the limitation of the maximum 32 pins handling in GPIO
driver API.
The gpio-bank nodes can be created under the gpio parent node.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This removes all occurrences of arm,num-mpu-regions relying on the value
reported by the register instead.
A user may still define this property if they need to have a compile time
definition for it.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
The C code does not required this parameter to be defined and falls back
to the MPU_TYPE's register to return the appropriate value.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
In case of boards where REF_CLK signal is not connected
to the GPIO0 by default add the possibility to use
the optional GPIO16/GPIO17 as a REF CLK source.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Although the RT1015 only supports 128 KB of FlexRAM being used at once, the
default fusemap overallocates 160KB of FlexRAM. The JLink flashloader
algorithm appears to rely on the 64KB of DTCM in the default fusemap
being configured. Reducing the DTCM allocation resulted in JLink
failing to flash the SOC.
To resolve this, utilize the default fusemap of {O, O, D, D, I} for the
RT1015 FlexRAM setup. Add a note about the restrictions on using
overallocated FlexRAM to the SOC DTSI.
Fixes#65889
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a property to the ethernet controller binding
indicating what type of connection the MAC has with
the PHY device.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Device Multiplexer (devmux) is a pseudo-device that can
be used to select between multiple included sub-devices.
It is experimental, but its current use is in system
remediation. Take for example, the scenario where the
system console and log subsystem both have the uart backend
enabled. The case may arise, where the chosen backing uart
could be an abstraction of another very high-bandwidth bus
- such as a PCIe BAR, a UDP socket, or even even just memory.
If the "service" (for lack of a better term) that backs this
abstract "uart" experiences an error, it is of critical
importance to be able to switch the system console, uart log
backend, or whatever to another uart (semi-transparently) in
order to bring up a shell, continue to view system logs, or
even just support user console I/O.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Add support for mutable devices. Mutable devices are those which
can be modified after declaration, in-place, in kernel mode.
In order for a device to be mutable, the following must be true
* `CONFIG_DEVICE_MUTABLE` must be y-selected
* the Devicetree bindings for the device must include
`mutable.yaml`
* the Devicetree node must include the `zephyr,mutable` property
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
MDIO controller is part of GMAC and it requires GMAC ethernet driver to
initialize first because it will reset the whole GMAC hw block during
initialization. Both C22 and C45 APIs are supported.
Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
add dts support for watchdog to accomodate watchdog driver bringup on
aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
The number of IRQ priority bits was incorrectly set to 3 instead
of 2, which is the correct number for Cortex-M0+.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
After porting from h5 to f7 i noticed that not all mcus have
cpu node labels. Added cpu0 node labels to all stm32 dts.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
Revert "dts: bindings: LPtimer of stm32 has a x2 factor on its clock"
The stm32u5 lptim clock source has no prescaler to divide the
the LPTIM input clock frequency : no property required.
This reverts commit 572b286010.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
r8a779f0 is also know as S4, this SoC is part of the Gen4 SoC series,
has 8 Cortex-A55 and a dual core lockstep Cortex-R52 processor.
SCIF0 is dedicated to Zephyr and SCIF3 to Linux.
**Control Domains**
IMPORTANT: This SoC is divided into two "domains":
- Application domain contains some peripherals as well as A55 & R52 cores.
- Control domain that contain a G4MH/RH850 MCU and other peripherals.
In order to access control domain peripherals such as gpio4-7 and CAN-FD
from application domain, the G4MH MCU has to unlock a protection
mechanism from control domain buses.
"Protected" controllers will be flagged in gen4 device trees,
warning users that they need to flash a custom G4MH firmware
to unlock access to these controllers.
**Clock controller**
This SoC clock controller is offering "domains"
for each world (Zephyr/Linux).
These domains are several "entry points" to the clock controller
which are arbitrated to avoid a world from turning off a clock needed
by another one.
We decided to use the same domain as Linux because the
security mechanism as to be implemented before accessing
another domain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The shi module in npcx4 supports the enhanced buffer mode.
Add a new compatible string "nuvoton,npcx-shi-enhanced" for it.
Then the shi driver can determine if it should use the enhanced buffer
mode based on the compatiable string.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
By making short inputs optional, the user can bypass short-events all
together if necessary (e.g. custom button-press listener).
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
This add regulator driver for Smartbond DA1469X SOC.
Driver can control VDD, V14, V18, V18P, V30 rails,
full voltage range supported by SOC is covered.
For VDD, V14, V18, V18P DCDC can be configured.
Special VDD_CLAMP (always on) and VDD_SLEPP are added
to allow configuration of VDD in sleep modes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add an option to drive inactive columns to inactive state rather than
high impedance. This is useful if the matrix has isolation diodes for
every key, as it allows the matrix to stabilize faster and the API for
changing the pin value is more efficient than the one to change the pin
configuration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Only RTC can be used as the idle timer for cortex-m systick. Set the
chosen node as RTC by default.
The idle timer will be enabled only if PM management is set.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.
The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add dummy interrupt id until we can support UART interuppt
on i.MX8MP in order to fix compilation warnings.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit introduces the SOF host DMA driver.
This driver is used by NXP platforms in the context of
SOF's host component to copy data from the host memory
to the firmware (local) memory. This is possible because
NXP platforms can access the host memory directly w/o
an actual DMA engine.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Adds a clock control device for a PWM node, allowing the PWM
to be controlled using the clock control API.
It is a similar idea to the device driver in linux:
linux/Documentation/devicetree/bindings/clock/pwm-clock.yaml
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Split the common keyboard scanning code out of the ITE specific driver
and use the generic code instead.
Note that this changes few timing defaults, the change is not
significant though so I suspect there's no difference in practice.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- added example of usage Infineon CAT1 i2c driver
- added note that pinctrl nodes need to be configured
as open-drain and input-enable.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Setting slew-rate property is not supported on Kinetis KE series
and the value will not have effect, so this property should not
be required.
We are also planning to reuse the Kinetis pin control binding and
associated driver for NXP S32K1xx devices, which doesn't support
setting the slew-rate rate as well.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add Verdin iMX8M Plus board with i.MX8MP SoC and ARM Cortex-M7 processor.
Add two targets (DDR and ITCM) for the iMX8M Plus board.
Port and documentation are based on NXP MIMX8MM EVK board.
This code is intented to be used with the Cortex-M7.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add support for UART1 usage by adding uart1 node and configuration
to the i.MX 8ML devicetree include.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a UART driver for the Renesas RZ/T2M
Serial Communication Interface.
The driver implements:
* Polling API,
* Interrupt-driven API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
Change the row-count and col-count to be optional in the generic
binding, add a second pair of macro to allow the implementation to
specify the numbers from a different property.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
A configurable delay during regulator switch on is currently
only supported by the GPIO and fixed regulator drivers.
This functionality has been moved to the common driver, so it can
be easily added to any regulator driver.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
i.MX93 share similiar register layout with i.MX RT11xx. Change ccm driver
to align with i.MX RT11xx, and make it easier to enable other drivers.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The LPS22DF is an ultracompact, piezoresistive, absolute pressure sensor
that functions as a digital output barometer. The LPS22DF provides lower
power consumption, achieving lower pressure noise than its predecessor.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lps22df.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The icmsg and icmsg_me backends has limitations in context of
concurrent access to single instance. Some limitations are:
* sending by more thread at the same time may cause -EBUSY
* allocating TX buffer will cause errors in other threads that want
to allocate before first thread sent the message,
* during no-copy receive, when RX buffer is on hold receiving is
totally blocked.
This backend resolves those limitations by adding dynamically allocated
buffers on shared memory next to ICmsg circular buffer. The data is
passed using those buffers, so concurrency is not a problem. The ICmsg
is used only to pass short 2-byte messages containing references to
those buffers. The backend also supports multiple endpoint.
The ipc/icmsg_me sample was modified to support this backend.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
Move all the generic code from the Nuvoton NPCX keyboard scanning driver
into input_kbd_matrix.c. While doing that convert few configs into
devicetree properties and tweak few other things to enable the generic
code to support multiple instances.
This is limited to 8 rows for now, and that's fine for all the current
in-tree drivers, the limit could be removed down the road but this
should be fine for now, added few generic build checks to make sure a
driver does not go over the limit, as well and some more implementation
specific checks.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The M4F subsystem has a dedicated GPIO controller with 24 available
pins. Add the node definition for the recently added driver.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add pinctrl to the Davinci GPIO driver to allow muxing pins dirctly
in this driver.
Also aligned the macro backslashes as line continuation character at
the end of each line with each at the same position and removed the
GPIO_DAVINCI_DEVICE_INIT macro which seems to be not used.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
DW watchdog driver is not used on ACE,
Intel ADSP watchdog driver will be used in DTS when ready to use
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding for nxp,mrt and nxp,mrt-channel. MRT is
NXP multirate timer, a simple timer with multiple
independent channels.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit introduces all changes necessary for utilizing
the serial interface on i.MX8QM/QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since the LPUART peripheral DTS binding requires the
"interrupts" property be specified even if it's not going
to be used for now we need to add a dummy interrupt controller
node to make that possible. Logically speaking, this dummy
interrupt controller should be used by peripherals which
can assert interrupts directly routed to the DSP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Generic GPIO enabled analog switch to isolate devices from an I2C bus
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Replace spsc_pbuf with pbuf implementation dedicated to
be used by IcMsg based backends.
The pbuf is written on top of simple read/write semantics
with minimal footprint and code complexity
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
The `int1-gpios` property is common for both spi and i2c
implementations of adxl372. Therefore move it to
`adi,adxl372-common.yaml`
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Add basic support for ams TSL2561 light sensor. Triggers, attributes
and manual integration time are currently not supported.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
This device lost the reg property since 88c9d1fbaf, causing the
nucleo_l011k4 board to not build anymore. Add it back, 512 bytes should
be the right number for this chip.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Both the BQ27421 and BQ27427 have a few preset Chemistry profiles.
For the BQ27421 there exists three variants of the IC, and for the BQ27427,
it can be configured. The chemistry profile among other things includes the
taper voltage, which is used to detect charge termination.
This adds an optional `chemistry-id` config option to the driver. On the
BQ27421, it will confirm that the correct variant of the IC is mounted,
and on the BQ27427, it will configure it with the correct value.
Side note: The reference manual for the BQ27427
(https://www.ti.com/lit/ug/sluucd5/sluucd5.pdf) currently contains some
errors and inconsistencies regarding these registers. The table on page 7
appears to be correct.
Signed-off-by: Tobias Pisani <topisani@hamsterpoison.com>
Added initial version of Infineon AIROC WIFI driver
Added initial version of binding file for Infineon AIROC WIFI
driver
Rename CONFIG_ABSTRACTION_RTOS_COMPONENT_ZEPHYR to
CONFIG_USE_INFINEON_ABSTRACTION_RTOS
Exclude cy8cproto_062_4343w platform from
drivers.modem.esp_at.build test
Change revision hal_infineon to
69c883d3bd9fac8a18dd8384624b8c472a68d06f
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix the following compilation warning:
```
Warning (unit_address_format): /memory@0xb0000000: \
unit name should not have leading "0x"
```
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
The variants of this family have different sizes of eeprom. This moves
eeprom definition from common family definition to device specific.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Add in DT the possibility to configure both INT1 and INT2
pin. The driver will then assign one of the two (either 1
or 2, according to what value drdy_pin is set) to a gpio
for receiving drdy interrupts.
The other pin may be used in the future to receive event
interrupts.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The HCI receive path has a delay between reading the header and payload
from the controller to give the controller time to setup the SPI
peripheral for the next transaction. Add the same delay on the transmit
path for the same reasons.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Real UARTs usually write 1 to a few bytes at a time through a
latch buffer. Add latch buffer property to binding for
uart_emul and limit fifo_read and fifo_fill to not exceed the
latch buffer.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Maxim MAX20335 is a PMIC with Ultra-Low IQ Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Unify spelling of CAN Flexible Data-rate abbreviation to "CAN FD" instead
of "CAN-FD". The former aligns with the CAN in Automation (CiA)
recommendation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Power rails of some peripherals are controlled externally.
This is a case in embedded controllers, where the power of
some I2C devices are managed by the main application
processor.
To ensure that zephyr drivers access the devices where is
powered on, introduce a "monitoring" power domain. It works
by registering interrupt handler with gpio a pin, so that
when power state changes, it will notify relevant drivers.
Additionaly add CONFIG_POWER_DOMAIN_INIT_PRIORITY to replace
harcoded init priority.
Fixes: #51349
Signed-off-by: Albert Jakieła <jakiela@google.com>
Adding initial support for Renesas RA UART.
To avoid complicating initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
