drivers: pinctrl: Add RW pinctrl driver
Add pinctrl driver for NXP RW6XX chip. Signed-off-by: Declan Snyder <declan.snyder@nxp.com> Co-authored-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Declan Snyder
Fabio Baltieri
parent
24a12802a5
commit
6f4cf5c73c
5 changed files with 254 additions and 0 deletions
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@ -34,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RW pinctrl_rw_iomux.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c)
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add_subdirectory(renesas)
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@ -62,6 +62,7 @@ source "drivers/pinctrl/Kconfig.emsdp"
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source "drivers/pinctrl/Kconfig.ti_cc32xx"
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source "drivers/pinctrl/Kconfig.numaker"
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source "drivers/pinctrl/Kconfig.eos_s3"
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source "drivers/pinctrl/Kconfig.rw"
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source "drivers/pinctrl/Kconfig.zynqmp"
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rsource "renesas/Kconfig"
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9
drivers/pinctrl/Kconfig.rw
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9
drivers/pinctrl/Kconfig.rw
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@ -0,0 +1,9 @@
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# Copyright 2022 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RW
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bool "Pin controller driver for NXP RW MCUs"
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default y
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depends on DT_HAS_NXP_RW_IOMUX_PINCTRL_ENABLED
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help
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Enable pin controller driver for NXP RW61x series MCUs
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174
drivers/pinctrl/pinctrl_rw_iomux.c
Normal file
174
drivers/pinctrl/pinctrl_rw_iomux.c
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@ -0,0 +1,174 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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static MCI_IO_MUX_Type *mci_iomux =
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(MCI_IO_MUX_Type *)DT_REG_ADDR(DT_NODELABEL(pinctrl));
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static SOCCIU_Type *soc_ctrl =
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(SOCCIU_Type *)DT_REG_ADDR(DT_NODELABEL(soc_ctrl));
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static AON_SOC_CIU_Type *aon_soc_ciu =
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(AON_SOC_CIU_Type *)DT_REG_ADDR(DT_NODELABEL(aon_soc_ctrl));
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/*
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* GPIO mux option definitions. Stored as a static array, because
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* these mux options are needed to clear pin mux settings to
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* a known good state before selecting a new alternate function.
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*/
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static uint64_t gpio_muxes[] = {IOMUX_GPIO_OPS};
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/*
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* Helper function to handle setting pin properties,
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* such as pin bias and slew rate
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*/
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static void configure_pin_props(uint32_t pin_mux, uint8_t gpio_idx)
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{
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uint32_t mask, set;
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volatile uint32_t *pull_reg = &soc_ctrl->PAD_PU_PD_EN0;
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volatile uint32_t *slew_reg = &soc_ctrl->SR_CONFIG0;
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volatile uint32_t *sleep_force_en = &soc_ctrl->PAD_SLP_EN0;
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volatile uint32_t *sleep_force_val = &soc_ctrl->PAD_SLP_VAL0;
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/* GPIO 22-27 use always on configuration registers */
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if (gpio_idx > 21 && gpio_idx < 28) {
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pull_reg = (&aon_soc_ciu->PAD_PU_PD_EN1 - 1);
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slew_reg = (&aon_soc_ciu->SR_CONFIG1 - 1);
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sleep_force_en = &aon_soc_ciu->PAD_SLP_EN0;
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sleep_force_val = &aon_soc_ciu->PAD_SLP_VAL0;
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}
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/* Calculate register offset for pull and slew regs.
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* Use bit shifting as opposed to division
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*/
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pull_reg += (gpio_idx >> 4);
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slew_reg += (gpio_idx >> 4);
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sleep_force_en += (gpio_idx >> 5);
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sleep_force_val += (gpio_idx >> 5);
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/* Set pull-up/pull-down */
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/* Use mask and bitshift here as opposed to modulo and multiplication.
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* equivalent to ((gpio_idx % 16) * 2)
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*/
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mask = 0x3 << ((gpio_idx & 0xF) << 1);
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set = IOMUX_PAD_GET_PULL(pin_mux) << ((gpio_idx & 0xF) << 1);
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*pull_reg = (*pull_reg & ~mask) | set;
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/* Set slew rate */
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set = IOMUX_PAD_GET_SLEW(pin_mux) << ((gpio_idx & 0xF) << 1);
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*slew_reg = (*slew_reg & ~mask) | set;
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/* Set sleep force enable bit */
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mask = (0x1 << (gpio_idx & 0x1F));
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set = (IOMUX_PAD_GET_SLEEP_FORCE_EN(pin_mux) << (gpio_idx & 0x1F));
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*sleep_force_en = (*sleep_force_en & ~mask) | set;
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set = (IOMUX_PAD_GET_SLEEP_FORCE_VAL(pin_mux) << (gpio_idx & 0x1F));
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*sleep_force_val = (*sleep_force_val & ~mask) | set;
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}
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static void select_gpio_mode(uint8_t gpio_idx)
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{
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uint64_t gpio_setting = gpio_muxes[gpio_idx];
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volatile uint32_t *flexcomm_reg = &mci_iomux->FC0;
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/* Clear flexcomm settings */
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flexcomm_reg += IOMUX_GET_FLEXCOMM_CLR_IDX(gpio_setting);
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*flexcomm_reg &= ~IOMUX_GET_FLEXCOMM_CLR_MASK(gpio_setting);
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/* Clear fsel settings */
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mci_iomux->FSEL &= ~IOMUX_GET_FSEL_CLR_MASK(gpio_setting);
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/* Clear CTimer in/out, if required */
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if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) {
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mci_iomux->C_TIMER_IN &=
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~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting));
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mci_iomux->C_TIMER_OUT &=
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~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting));
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}
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/* Clear SCTimer in/out, if required */
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if (IOMUX_GET_SCTIMER_IN_CLR_ENABLE(gpio_setting)) {
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mci_iomux->SC_TIMER &=
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~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting));
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}
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if (IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(gpio_setting)) {
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mci_iomux->SC_TIMER &=
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~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16));
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}
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/* Clear security gpio enable */
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mci_iomux->S_GPIO &= ~(0x1 << (gpio_idx - 32));
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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volatile uint32_t *flexcomm_reg;
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volatile uint32_t *iomux_en_reg;
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for (uint8_t i = 0; i < pin_cnt; i++) {
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flexcomm_reg = &mci_iomux->FC0;
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iomux_en_reg = &soc_ctrl->MCI_IOMUX_EN0;
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uint32_t pin_mux = pins[i];
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uint8_t gpio_idx = IOMUX_GET_GPIO_IDX(pin_mux);
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uint8_t type = IOMUX_GET_TYPE(pin_mux);
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/*
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* Before selecting an alternate function, we must clear any
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* conflicting pin configuration. We do this by resetting the
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* pin to a gpio configuration, then selecting the alternate
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* function.
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*/
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select_gpio_mode(gpio_idx);
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switch (type) {
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case IOMUX_FLEXCOMM:
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flexcomm_reg += IOMUX_GET_FLEXCOMM_IDX(pin_mux);
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*flexcomm_reg |=
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(0x1 << IOMUX_GET_FLEXCOMM_BIT(pin_mux));
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break;
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case IOMUX_FSEL:
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mci_iomux->FSEL |=
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(0x1 << IOMUX_GET_FSEL_BIT(pin_mux));
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break;
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case IOMUX_CTIMER_IN:
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mci_iomux->C_TIMER_IN |=
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(0x1 << IOMUX_GET_CTIMER_BIT(pin_mux));
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break;
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case IOMUX_CTIMER_OUT:
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mci_iomux->C_TIMER_OUT |=
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(0x1 << IOMUX_GET_CTIMER_BIT(pin_mux));
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break;
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case IOMUX_SCTIMER_IN:
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mci_iomux->SC_TIMER |=
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(0x1 << IOMUX_GET_SCTIMER_BIT(pin_mux));
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break;
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case IOMUX_SCTIMER_OUT:
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mci_iomux->SC_TIMER |=
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(0x1 << (IOMUX_GET_SCTIMER_BIT(pin_mux) + 16));
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break;
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case IOMUX_SGPIO:
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mci_iomux->S_GPIO |= (0x1 << (gpio_idx - 32));
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break;
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case IOMUX_GPIO:
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if (gpio_idx > 32) {
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mci_iomux->GPIO_GRP1 |= (0x1 << (gpio_idx - 32));
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} else {
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mci_iomux->GPIO_GRP0 |= (0x1 << gpio_idx);
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}
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break;
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case IOMUX_AON:
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/* No selection bits should be set */
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break;
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default:
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/* Unsupported type passed */
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return -ENOTSUP;
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}
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configure_pin_props(pin_mux, gpio_idx);
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/* Now, enable pin controller access to this pin */
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if (gpio_idx > 21 && gpio_idx < 28) {
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/* GPIO 22-27 use always on soc controller */
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iomux_en_reg = &aon_soc_ciu->MCI_IOMUX_EN0;
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}
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iomux_en_reg += (gpio_idx >> 5);
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*iomux_en_reg |= (0x1 << (gpio_idx & 0x1F));
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}
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return 0;
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}
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69
dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml
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69
dts/bindings/pinctrl/nxp,rw-iomux-pinctrl.yaml
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@ -0,0 +1,69 @@
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# Copyright 2022, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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RW61x pin control node. This node defines pin configurations in pin
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groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
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group within the pin configuration defines a peripheral's pin configuration.
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Each numbered subgroup represents pins with shared configuration for that
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peripheral. The 'pinmux' property of each group selects the pins to be
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configured with these properties. For example, here is a configuration
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for FLEXCOMM0 pins:
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pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
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group0 {
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pinmux = <IO_MUX_FC0_USART_DATA_IO2>,
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<IO_MUX_FC0_USART_DATA_IO3>;
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slew-rate = "normal";
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};
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};
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If only the required properties are supplied, the pin will be configured
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as normal drive strength and no pull. This corresponds to the following
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pin settings:
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PAD_PU_PD_ENx = (0x0 << pin_index)
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SR_CONFIGx = (0x2 << pin_index)
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Note
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Note the inherited pinctrl properties defined below have the following effects:
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bias-pull-up: PAD_PU_PD_ENx= (0x1 << pin_index)
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bias-pull-down: PAD_PU_PD_ENx= (0x10 << pin_index)
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compatible: "nxp,rw-iomux-pinctrl"
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include:
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- name: base.yaml
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child-binding:
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description: iMX RW IOMUX pin controller pin group
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child-binding:
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description: |
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iMX RW IOMUX pin controller pin configuration node
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-pull-up
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- bias-pull-down
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properties:
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pinmux:
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required: true
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type: array
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description: |
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Pin mux selection for this group. See the SOC level pinctrl header
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file in NXP's HAL for a defined list of these options.
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slew-rate:
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required: true
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type: string
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enum:
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- "slow"
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- "normal"
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- "fast"
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- "ultra"
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description: |
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Pin output slew rate. Sets the GPIOxx_SR field in the SR_CONFIGx
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register.
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0 - slow slew rate
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1 - normal slew rate
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2 - fast slew rate
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3 - fastest slew rate (ultra)
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