Convert the ITE keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Add binding for nxp,mrt and nxp,mrt-channel. MRT is
NXP multirate timer, a simple timer with multiple
independent channels.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit enables clock control on the i.MX8QM and QXP boards.
This is achieved through the following changes:
1) The "reg" property is no longer marked as required
for the "nxp,imx-ccm" binding. This is necessary because
in the case of i.MX8QM and i.MX8QXP the clock management
is done through the SCFW, hence there's no need to access
CCM's MMIO space (not that you could anyways).
2) The DTS now contains a scu_mu node. This node refers
to the MU instance used by the DSP to communicate with
the SCFW.
3) The CCM driver needs to support the LPUART clocks
(which will be the only IP that's supported for now)
and needs to perform an initialization so that the
NXP HAL driver knows which MU to use to communicate
with the SCFW.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This patch set provides support for T1S ethernet device - LAN8651.
For SPI communication the implementation of Open Alliance TC6
specification is used.
The driver implementation focuses mostly on reducing memory footprint,
as the used SoC (STM32G491) for development has only 32 KiB RAM in total.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Generic GPIO enabled analog switch to isolate devices from an I2C bus
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Replace spsc_pbuf with pbuf implementation dedicated to
be used by IcMsg based backends.
The pbuf is written on top of simple read/write semantics
with minimal footprint and code complexity
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
The `int1-gpios` property is common for both spi and i2c
implementations of adxl372. Therefore move it to
`adi,adxl372-common.yaml`
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Add basic support for ams TSL2561 light sensor. Triggers, attributes
and manual integration time are currently not supported.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Both the BQ27421 and BQ27427 have a few preset Chemistry profiles.
For the BQ27421 there exists three variants of the IC, and for the BQ27427,
it can be configured. The chemistry profile among other things includes the
taper voltage, which is used to detect charge termination.
This adds an optional `chemistry-id` config option to the driver. On the
BQ27421, it will confirm that the correct variant of the IC is mounted,
and on the BQ27427, it will configure it with the correct value.
Side note: The reference manual for the BQ27427
(https://www.ti.com/lit/ug/sluucd5/sluucd5.pdf) currently contains some
errors and inconsistencies regarding these registers. The table on page 7
appears to be correct.
Signed-off-by: Tobias Pisani <topisani@hamsterpoison.com>
Added initial version of Infineon AIROC WIFI driver
Added initial version of binding file for Infineon AIROC WIFI
driver
Rename CONFIG_ABSTRACTION_RTOS_COMPONENT_ZEPHYR to
CONFIG_USE_INFINEON_ABSTRACTION_RTOS
Exclude cy8cproto_062_4343w platform from
drivers.modem.esp_at.build test
Change revision hal_infineon to
69c883d3bd9fac8a18dd8384624b8c472a68d06f
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add in DT the possibility to configure both INT1 and INT2
pin. The driver will then assign one of the two (either 1
or 2, according to what value drdy_pin is set) to a gpio
for receiving drdy interrupts.
The other pin may be used in the future to receive event
interrupts.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The HCI receive path has a delay between reading the header and payload
from the controller to give the controller time to setup the SPI
peripheral for the next transaction. Add the same delay on the transmit
path for the same reasons.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Real UARTs usually write 1 to a few bytes at a time through a
latch buffer. Add latch buffer property to binding for
uart_emul and limit fifo_read and fifo_fill to not exceed the
latch buffer.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Maxim MAX20335 is a PMIC with Ultra-Low IQ Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Unify spelling of CAN Flexible Data-rate abbreviation to "CAN FD" instead
of "CAN-FD". The former aligns with the CAN in Automation (CiA)
recommendation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Power rails of some peripherals are controlled externally.
This is a case in embedded controllers, where the power of
some I2C devices are managed by the main application
processor.
To ensure that zephyr drivers access the devices where is
powered on, introduce a "monitoring" power domain. It works
by registering interrupt handler with gpio a pin, so that
when power state changes, it will notify relevant drivers.
Additionaly add CONFIG_POWER_DOMAIN_INIT_PRIORITY to replace
harcoded init priority.
Fixes: #51349
Signed-off-by: Albert Jakieła <jakiela@google.com>
Adding initial support for Renesas RA UART.
To avoid complicating initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
In the CONFIG_SPI_NOR_SFDP_MINIMAL configuration this value is hard
coded to 256 bytes. Make it configurable via devicetree.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
We currently have three keyboard scanning drivers in the code base
(npcx, it8xxx2 and mchp_xec, last two yet to be converted to input).
These have been largely copy pasted from each other and share a lot of
the same structure and code.
This PR lays a foundation to start decoupling feature from those drivers
into a common code base, and it is heavily inspired by the current
regulator common data/config one.
Feature wise this only moves the thread struct, stack and initialization
to the common code and declares the thread callback as the only API, but
the intent is to move as much code as possible in there an only abstract
device specific callbacks in the api structures.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds a GNSS driver for the Quectel LCX6G
series of GNSS modems (LC26G, LC76G, LC86G). It is
based on the modem subsystem, and the GNSS utilities
added in the two previous commits.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
The default is that the high time for open-drain clk is one
PPBAUD, which is typically very short. Some device require
a longer high time during the open-drain address phase so
add a property to allow device tree to override the default.
Signed-off-by: Mike J. Chen <mjchen@google.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Modified files (yaml, dts, overlay, and c) which were using spi-cpol
and spi-cpha to be compatible with the new structure.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add support to set SPI clock polarity (CPOL), clock phase (CPHA), and
hold-on-cs in a dts file to get rid of using related macros in spi.c driver
since each board may work on a different SPI mode rather than the default
one (based on CPOL and CPHA).
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
This commit adds basic support for m5stacks M-Bus extenions port that is
support my core and core2 module.
Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
Allows device tree to enable usage of the controller feature
where HS clock is disabled when not in use, which is good
for reducing power consumption if MIPI DSI is mostly idle.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The BCM2711 SoC exposes 58 GPIOs. The first 28 (bank 0) are accessible
to users via the 40-pin header, while the others (bank 1) are used for
controlling on-board peripherals.
This also update doc of `rpi_4b` board.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Enable driver for intel lw uart.
Changes from review:
- refactor spinlock to inside of loop
- use menuconfig for kconfig
- add CONFIG_UART_INTEL_LW_AUTO_LINE_CTRL_POLL
Signed-off-by: Teoh Shi Lin <shi.lin.teoh@intel.com>
add basic sensor support for 3-axis accelerometer, currently
this driver support data acquisition and motion detection
features.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Add wakeup_duration support. (WAKE_DUR in WAKE_UP_DUR)
Value is configurable through DT per instance.
Signed-off-by: Adrian Wojak <adrian.wojak@outlook.com>
Use a new property, "clock-mux" to select the clock mux for the SAI.
Previously, the clock mux was being selected using the "bits" specifier
of the "clocks" phandle property, which is not the purpose of this
specifier. This can be shown by the regression introduced by 5bebbb91,
which changed the "bits" field to the clock gate shift (which is the
intended meaning).
This incidently worked for the SAI1 and SAI3 peripherals, as the lower 2
bits of the correct clock source selection (0b10) are the same as the new
value placed in the "bit" specifier. For SAI2, the clock source was
switched to PLL3 PDF0 by this change.
To resolve this, use an explict "clock-mux" property for this selection.
Fixes#63541
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add a new SPI shim driver for Intel SoCs. Builds upon the SEDI bare
metal SPI driver in the hal-intel module.
Co-Authored-By: Kong Li <li.kong@intel.com>
Signed-off-by: Ye Weize <weize.ye@intel.com>
Adds a devicetree for describing common battery characteristics used
by multiple devices and subsystems.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
This is needed since commit f66b73197d
("drivers: hwspinlock: implement sqn hwspinlock driver") started
using it. Not sure how this got past CI.
Signed-off-by: Martí Bolívar <mbolivar@amperecomputing.com>
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;
- added bias_high_impedance option
- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Extend the NXP S32 GPIO driver to be able to route external interrupts
to either SIUL2 EIRQ interrupt controller or, when available on the
SoC, WKPU interrupt controller.
Since WKPU can support up to 64 external interrupt sources and SIUL2
EIRQ up to 32, gpio_get_pending_int() is removed and the interrupt
controller specific API must be used instead.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce an interrupt controller for the NXP S32 WKPU peripheral
that can be integrated with GPIO to trigger interrupts through
external interrupt pad inputs.
WKPU can trigger interrupts from certain input pads that support this
function, as well as wake-up events to the power management domain. This
patch only adds WKPU functionality as an interrupt controller to extend
the number of input pads that can interrupt the core. Power management
functionalities are not supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The example sets the power-role to "SINK", but the value is
case-sensitive and only accepts lowercase "sink".
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
Specify only the bus corresponding to the current yaml file, as done in
the adi,adxl372-spi.yaml.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
The PCA9633 i2c LED controller offers an All Call address in its nominal
operation, allowing simultaneous communication with all instances present
on the same i2c bus. The default address is 0x70. While this functionality
is convenient, it is possible that the board uses another i2c component
that also uses this address (for example, the shtcx). In such cases, the
address conflict prevents the proper functioning of the system.
The idea is to add a "disable-allcall" property to the device tree. If this
option is present, the initialization of the PCA9633 forces the bit 0
(ALLCALL) to be set to false, thereby disabling this function. It is
necessary to add this property to all PCA9633 devices on the bus to free up
the address 0x70.
Signed-off-by: Steve Jacot-Guillarmod <steve@piziwate.net>
The pre-alloacted size of the buffer for the SHA ROM API code increases
in npcx4 chip. This commit adds a new property context-buffer-size to
sha0 DT node in npcx9 and npcx4 separately. The driver can pre-allocate
buffer with the correct size based on the property.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Different nRF52 devices have different maximum TWI DMA transfer size,
and it's easy to hit the limit with i2c displays on nrf52832 (8 bit) and
nrf52810 (10 bit). Currently neither the driver or the hal validate the
limit, leading to random NACK errors when trying to transfer more data.
Add a check on the driver to fail gracefully when going over the limit.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
These two have been converted from kscan to input already, move the
bindings over to match the change.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reword the descriptions for the bus-speed, sample-point, bus-speed-data,
and sample-point-data CAN controller devicetree properties.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Removing the edge-trigger Kconfig as it is supported by default
in the RISCV PLIC specifications.
Define the edge-trigger register offset in the driver instead
of retrieving the value from devicetree as it is not something
configurable. The value 0x1080 is defined in Andes & Telink
datasheets.
Updated build_all testcase.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This continue PR #31270. The updated changes are:
- Updated to work with latest zephyr
- Inplace reads/writes of registers
- Batch read of RX messages when multiple messages can be read
- FIFO abstraction of RX/TEF queues
- Handle ivmif errors
- Use READ_CRC for register reads
- Use bitmasks instead of bitfield members
- Rename mcp25xxfd to mcp251xfd
- General cleanups
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
add host controller driver support for emmc version 5.1.
The driver expose zephyr sdhc api interface for emmc host controller.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
This introduces pwm capture shim driver for NXP S32 EMIOS,
the driver uses SAIC mode that is supported for all channels,
to capture the counter value on each edge for period/pulse
measurement
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This prepares support pwm capture APIs by extended current pwm
shim driver but use a differrence hal component:
- Introduce a Kconfig options that will be set when PWM pulse
generation API is used, it is also used to select the hal
component. Guarding current code inside this Kconfig option
- Increase #pwm-cells to 3, flags is supported for PWM capture
- Do not require duty-cycle and polarity be set in dt, PWM
capture doesn't need it.
- Rename emum value for pwm-mode to keep only key information
- Add preprocessor in case no channel is configured for generate
PWM output, to avoid warning when build
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This enables and declares interrupt handlers for eMIOS,
the handlers defined and implemented at HAL, the driver
takes the name for each id from interrupt-names devicetree
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Some Ethernet PHYs used the devicetree node name `phy`, while others
used `ethernet-phy`. Be consistent and use `ethernet-phy` throughout.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename filename of binding for quicklogic,usbserialport-s3b to make it
consistent with compatible string.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Update compatible strings and file names of Intel CPUs. Always use dash
instead of underscore. This will make all the compat strings and binding
files names for Intel consistent.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add `mdio_read_c45()`/`mdio_write_c45()` APIs for Clause 45 access
and remove the `protocol` MDIO binding property so that MDIO bus
controller can support more than one protocol.
A new MDIO header is introduced with generic opcodes, MMD and
registers addresses, to be used by MDIO and PHY drivers.
Existing MDIO drivers that support both Clause 22 and Clause 45
access are migrated to the new APIs.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.
For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk
Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add new dt binding for edma v3 that inherits whole dt
properties from current version. One more property is
added for SoCs that don't have separate error interrupt
id, use same id with channel interrupt
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
The current implementation iterates over all channels
even if only several channels share the same irq. This
introduces one more dt property to describe an offset
between two channels share the same interrupt id.
Beside that, the error interrupt must be put as last
element of "interrupt" dt property.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
With the current implementation, the 1st cell is not DMAMUX id
as mentioned in the bindings (0 for DMAMUX0 and 1 for DMAMUX1).
Moreover, the referenced Linux bindings is obsoleted, it was
migrated to use yaml syntax
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
These worked because edtlib allows 'pinctrl-.*' properties without
specifying them on the bindings. However, this has never been an
anounced pinctrl feature, the reference documents explicitly mention
that usage of pinctrl-device.yaml is mandatory.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Revise property's name & cells' name for further
devicetree reset macro used.
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Based on RM0456, each PLL in the STM32U5 has the
capability to work either in integer or fractional mode.
In this update, the fractional mode can be enabled
by setting the fracn value in the device tree.
Signed-off-by: Jatty Andriean <jandriea@outlook.com>
Introduce support for Texas Instruments TMAG5170
high-precision linear 3D Hall-effect SPI sensor.
This driver allows to configure measurements on
magnetic and temperature channels. It is also
possible to read rotation of the magnet.
Signed-off-by: Michal Morsisko <morsisko@gmail.com>
Added a phandle named dma-parent to get base address instead of
adding DMA as child node because it is causing a build warning
(avoid_unnecessary_addr_size) if the parent instance has
"#address-cells/#size-cells" dts properties marked required
and child doesn't have reg property. DMA doesn't have reg
as it gets the base address from parent device
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Adds initial support for hm330x dust sensor series. Allows to read PM1,
PM2.5 and PM10 concentrations in atmospheric environment. A further
update to the driver may add support for also reading "standard" CF1
concentrations by exposing of a custom sensor attribute or a Kconfig
option. Tested with Grove - Laser PM2.5 Sensor (HM3301) attached to a
Wio Terminal.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
When the alternate setting is configured as func3, in addition to
the setting of func3-gcr, some pins require external setting.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Introduce SMARTDMA dma driver. The SMARTDMA is a peripheral present on
some NXP SOCs, which implements a programmable DMA engine. The DMA
engine does not use channels, but rather provides a series of API
functions implemented by the firmware provided with MCUX SDK.
These API functions can be selected by the dma_config slot parameter. A
custom API is also provided to allow the user to install an alternate
firmware into the SMARTDMA.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add MDIO driver that works through GPIO pins. This driver is
useful when a microcontroller doesn't have MDIO bus or when multiple
separate MDIO buses are required. The driver provides access to
the MDIO bus through GPIO pins for any SoC that has GPIO pin control
available.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Add a property for STM32 ADC to indicate which type of sequencer is used
by the device (fully configurable or not).
Add defines to help with this setting.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Remove temp-, vref- and vbat-channel from STM32 ADC nodes as it is not
used in the driver anymore.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Deprecate the advanced CAN timing devicetree properties in favor of setting
advanced timing parameters from application code.
The advanced timing properties are giving in number of time quanta (Tq) and
requires reverse-calculation to find a suitable CAN clock divider. The
resulting bitrate error is compared against a threshold in the driver
initialization code, but the application is not able to retrieve it.
Forcing applications to use the CAN timing APIs directly instead makes it
up to the application to determine if the bitrate error is acceptable or
not.
The deprecated properties are:
- prop-seg
- phase-seg1
- phase-seg2
- prop-seg-data
- phase-seg1-data
- phase-seg2-data
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add phandle prop to reference any regulator that must
be enabled in order for the LPADC to function as intended.
Change LPADC driver to use this property if present.
LPADC on LPC55S36 depends on VREF peripheral, enable for this platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding, include header, and driver for NXP VREF IP block.
NXP VREF is an internal voltage reference generator on some SOCs
that fits well with the regulator API in zephyr.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Rework RAM disk driver to be configured using devicetree and
support multiple instances.
This patch also removes a copy of the RAM disk driver,
tests/subsys/fs/fat_fs_dual_drive/src/disk_access_test_drv.c,
that was there for testing multiple disk drivers support.
Bonus: one SYS_INIT() less and a memory region can be exported to the
host.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add yaml file for 'xen,xen', because without it an appropriate
'CONFIG_DT_HAS_XEN_XEN_ENABLED' isn't generated.
It will be used for checking Xen support on current setup, instead of
checking if it is BOARD/SOC "xenvm" (which is not correct for Domain-0
configurations).
Remove xen,xen-4.15.yaml at all, because it isn't necessary to have
yaml for some specific Xen version.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This commit adds support for the ATMEL HSMCI peripheral
for the SAM4E MCU series, enabling native SD card support.
Signed-off-by: Vincent van Beveren <v.van.beveren@nikhef.nl>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit removes the enum array with allowed values for the `riscv,isa`
field. There are many ways in which RISC-V ISA extension string can be
represented, and listing them all is futile. In addition, custom extensions
can be implemented, meaning every extension would have to be listed in the
enum array as well.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add a MBOX driver wrapper around the NXP MU, simular to
the existing wrapper around the NXP S32 MRU. This allows Zephyr IPC
to work based on the MU, on a number of NXP boards.
Also update the SHA of NXP HAL to enable the Kconfig for this driver.
Signed-off-by: Yicheng Li <yichengli@google.com>
Determine sh1106 from the `compatibility` value instead of
the SSD1306_CONTROLLER_TYPE setting.
Change the settings in `boards/shields/ssd1306/sh1106_128x64.overlay`
to follow this change.
Remove the SSD1306_CONTROLLER_TYPE from its Kconfig.defconfig,
and set the `compatibility` to `sinowealth,sh1106`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
When multiple devices are connected, the SSD1306_REVERSE_MODE setting
cannot switch for each device.
Add an equivalent setting to the devicetree properties to replace it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Moved the interrupt handling code from a bus-specific binding file to
the parent binding file. This modification ensures that interrupt
handling, which is inherently independent of the type of BUS used
(either i2c or spi), is located in the appropriate location within
the code.
Previously, this code was found in a bus-specific file, despite its
functionality being applicable to all buses. This change ensures a
more logical placement and will help to maintain coherence within the
codebase.
This change aligns with the existing implementation where the interrupt
handling code already operates independently of the BUS type.
Tested this on a nrf52840 with a bmi270 on spi bus with the sample from
zephyr/samples/sensor/bmi270 by adding an interrupt handler in main.c
which uses the bmi270_trigger.c implementation and verified this with
breakpoints and log output.
Added the irq-gpios to tests/drivers/build_all/sensor/i2c.dtsi and
tests/drivers/build_all/sensor/spi.dtsi and fixed whitespace formatting.
Fixes: #58843
Signed-off-by: Andreas Wiesinger <awiesing90@gmail.com>
The current implementation uses both, host and card capabilites to derive
the maximum bus width to be used. However, in cases where a MMC device is
not connected to the host via shdc using the full bus width of 8 lines,
device initialization fails. Introducing the `bus-width` property
circumvents this by reducing the host bus capabilites and forcing
communication with the MMC device using 1, 4 or 8 lines.
Signed-off-by: Mourad Kharrazi <mourad.kharrazi@ithinx.io>
Add a pseudo device which can be used to hook into qdec events and
optionally a button and relay the input_event to lvgl.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Initial version of Infineon CAT1 SPI Driver supporting synchronous
and asynchronous data transfer API
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add devicetree binding for the TI TCAN4x5x series of CAN controllers. These
CAN controllers are based on the Bosch M_CAN IP and interfaced via a SPI
bus.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Create dac_mcxu_lpdac.c file to implement mcux lpdac, add binding for
the mcux lpdac, update Kconfig.mcux and CMakeLists.txt file to support
mcux lpdac.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The Nuvoton NCT38xx is a multi-function device providing a TCPC
controller and a I/O expander (GPIO driver). Add a multi-function
driver to manage exclusive access to the device.
Tested with "twister -T tests/drivers/build_all/gpio".
Signed-off-by: Keith Short <keithshort@google.com>
Seems like the SSD1306 controller needs a bit of time after power up
before it can take i2c commands. This causes problems with
microcontrollers that have no other delays in the startup sequence, like
rpi_pico.
There's currently no good way of modeling this in Zephyr right now, and
there's also no clear indication of how much time the device needs in
the datasheet that I could find, but it seems like 10ms is enough for
that to start reliably so add a delay in the ssd1306 init function to
ensure that at least that time has passed from system power up.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add `thr-sel` prop. to select the relevant threshold register for adc
comparator since there're two adc modules in npcx4 series.
Signed-off-by: Kate Yen <htyen@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Previously the pwm capture only support capturing on channel 1
and 2, because the slave mode controller was used, which uses
the signal TIxFP which is not available for channel 3 and 4.
This commit adds optional support for four channel capturing by
changing the method of capturing PWM signals to not use the
slave mode controller to reset the counter register. Instead the
counter is reset in the ISR. This will result in a slight loss
of accuracy but is still within an acceptable range.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This commit adds option to dump i2c messages of only specified
devices. It makes it easier to debug communication of specific
i2c device instead of logging all i2c communication.
The filter of devices is specifiec in device-tree using the
node with "zephyr,i2c-dump-filter" compatible string.
Example of device-tree node:
i2c-dump-filter {
compatible = "zephyr,i2c-dump-filter";
devices = < &display0 >, < &sensor3 >;
};
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This introduces PWM driver with supporting PWM output
APIs based on NXP S32 EMIOS peripheral. This supports
three mode: OPWFMB, OPWMCB and OPWMB.
OPWFMB uses internal counter, the new period and duty
cycle takes effect immediately.
OPWMCB and OPWMB use external counter as timebase, changing
PWM period at runtime will impact to all channels share the
same timebase. Also the new period and duty cycle take effect
in next period boundary of the timebase
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This PR adds a misc driver for NXP S32 eMIOS peripheral.
eMIOS provides multiple unified channels (UCs), there are
several channels can be used as reference timebase
(master bus) for other channels. At this time, the
driver does initialize global configuration for eMIOS
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add TI VIM (Vectored Interrupt Manager) interrupt controller support.
VIM is a TI specific custom interrupt controller for ARM cores.
In J721E soc, VIM aggregates interrupts to Cortex R5 cores.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
VIM: section 6.3.3.6
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
As per #26393, Local APIC is using Kconfig based option for
the base address. This patch adds DTS binding support in the driver,
just like its conunter part I/O APIC.
Signed-off-by: Umar Nisar <umar.nisar@intel.com>
i.MX RT SoC have some pins related to the watchdog.
For example, iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb allows WDOG1_RST_B_DEB
signal to be used as reset source for i.MX RT10xx boards.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Allow use of multiple mb85rc frams at contiguous i2c addresses as a single
big fram module.
Tested on mb85rc1mt used as two 32K modules, where the first one was at
mb85rc1mt's first i2c address and the second one at mb85rc1mt's second i2c
address.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
The added cellular modem driver is a naive driver, which
shall serve as a template for implementing tailored
drivers for modems like the UBLOX-R4. It uses only
generic at commands, described in 3gpp, and protocols,
like CMUX and PPP.
A binding for the BG95 has been added, which replaces
the quectel,bg9x. This is neccesary since the BG95 does
not have a usable reset pin, the reset and powerkey are
internally connected to each other.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
The current-shunt calibration requires a factor of 4x if high-precision
mode is selected.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
Add two properties to define the STM32 ADC clock source:
- Clock source: synchronous or asynchronous
- Clock prescaler
By combining these two parameters, it will be possible to set the desired
ADC clock for most series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a pseudo device which can be used to hook into gpio-keys input_events
and relay the events to a lv_indev.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add the scaffolding to create input lvgl pseudo devices which route zephyr
input_event to their lvgl `indev` equivalent. As a first cut also add a
`zephyr,lvgl-pointer-input compatible which can be a drop-in replacement
for the existing kscan solution.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Added configuration of termination current and trickle voltage
Added option to bypass low voltage charge inhibit
Added option to disable automatic recharge
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Many fuel gauge ICs offer a battery cutoff/shipping mode functionality that
cutoff charge from the battery. This is often useful for preserving battery
charge on devices while in storage.
Add battery cutoff support to the fuel gauge API with a generic default SBS
driver showing an example of support in tests.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
This adds QSPI controller properties that allow tuning
chip select timings (needed for accessing QSPI at high speed)
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
RC32K/RCX/XTAL32K were present in device tree as fixed-clock.
Now calibration time for RCX and RC32K is added and settle time
for XTAL32K so additional binding is created.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for SPI host command backend for STM32 chips family.
Unfortunately, the current SPI API can't be used to handle the host
commands communication. The main issues are unknown command size sent
by the host(the SPI transaction sends/receives specific number of bytes)
and need to constant sending status byte(the SPI module is enabled and
disabled per transaction). Thus the SPI backend includes basic SPI STM32
driver adjusted to host command specification.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add basic support of 'regulator-gpio'. For now, it is support
only controling voltage and driver presents only six functions:
* enable and disable the regulator;
* set and get voltage;
* count and list of voltage(s).
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This adds support for the max1125x (max11254, max11254)
family of spi adc devices.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
Now that all in-tree phys are declared under their mdio bus, drop the
`mdio` property and use DT_INST_BUS to find the bus.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When we lock an hwspinlock, we must write the CPU identifier to
the hwspinlock register. If we want to unlock the locked hwspinlock,
we have to rewrite the same CPU identifier.
To define the CPU identifier, we use affinity 1 and affinity 2 fields
of the MPIDR register.
Signed-off-by: Aziz Idomar <aidomar@sequans.com>
Add support for ADIN1110 10BASE-T1L Ethernet MAC-PHY.
The ADIN1110 is an ultra low power, single port, 10BASE-T1L
transceiver design for industrial Ethernet applications and is com-
pliant with the IEEE® 802.3cg-2019™ Ethernet standard for long
reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated
media access control (MAC) interface, the ADIN1110 enables direct
connectivity with a variety of host controllers via a 4-wire serial
peripheral interface (SPI). This SPI enables the use of lower power
processors without an integrated MAC, which provides for the
lowest overall system level power consumption. The SPI can be
configured to use the Open Alliance SPI protocol or a generic SPI
protocol.
Documentation:
https://www.analog.com/en/products/adin1110.html
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
The existing i2c sda/slc pinctrl nodes serve as an input and output
for the USIC. This limits the number of pins that can be used for i2c
since the pin must be internally connected to both DOUT0 and DX0 signals
on the USIC (for the sda signal for example).
It is also possible to use separate pins to DOUT0 and DX0, but connect
the pins externally. Add these extra pinctrl nodes and document their
use in infineon,xmc4xxx-i2c.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In commit 541482ff20 the pinctrl alternate
function mask was increased to also include open-drain setting.
Revert this change because open-drain can already be set via property
drive-open-drain.
The commit also added separate pinctrl nodes for the i2c controller and
target modes. However, the alternate function settings
is the same in both modes, so keep only one and remove the mode
label.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
To be consistent with other xmc4xxx drivers.
A few other device tree changes:
- Rename clock signal option as it's handled by DX1.
- Remove clock-frequency option as it's already added in
i2c-controller.yaml, and interrupts is already defined as array
in base.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Rework the devicetree definition for smsc91x to put the mdio and
ethernet device at the same level, and make the phy a child of the mdio
node.
This allows matching up the device initialization sequence with the
devicetree hierarchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a property that allows explicit selection of the differential
input mode for ADC channels in DTS. This is useful for controllers
that do not have configurable inputs, so the zephyr,negative-input
property that implicitly selects the differential mode is not
specified for them.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Allow properties 'regulator-min-microvolt' and 'regulator-max-microvolt'
for fixed regulators: Note: they should be equal.
Add simple functions for getting list of allowed and count of voltages.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Possible situation is that in some driver, devices can be controlled in
different ways: in some, we can only turn the power on or off, in others,
we can only control the voltage, and in some, we can control power supply
or voltage level. There may also be devices where there is no control
over power supply at all. A clear example of this can be eMMC devices
where the voltage is usually fixed and they are always powered on.
However, we would like to have a common code for controlling all the
mentioned types of devices, at least the driver shouldn't worry about the
implementation details of voltage regulators. Therefore, there may exist
empty regulators - regulators that only contain information about the
supported voltage, and we cannot change anything in them. The device tree
node description for such a regulator is only necessary for compatibility
with other regulators. Hence, we need to add the possibility of the
existence of such a dummy fixed-regulator.
In this commit, support for a fixed dummy regulator without the ability
for any control has been added. Note that such support also exists in the
Linux kernel. In other words, the logic of the fixed regulator has been
aligned with the logic of the fixed regulator inside the Linux kernel.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Although there are no in-tree users, we will deprecate the
`facebook` vendor prefix and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Since we do not have any in-tree users, we will skip the
deprecation process for `facebook` and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This commit adds input clock selection to the RTC driver. This
is required to allow for the real hardware to operate. The
QEMU emulated hardware ignores the input clock settings.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
INPUT_REL_WHEEL is the code that normally refer to scroller wheel, which
probably makes a bit more sense in this context, use that instead of
INPUT_REL_Y.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change the gpio-keys and zephyr,gpio-keys so that they can both be used
with the input subsystem driver. Make the zephyr,code property optional
so that existing out of tree board can still use this node with their
custom code, but change everything else so that an existin gpio-keys
node can be used with the input driver as long as the codes are defined.
From the application perspective, this means that the application can
still use the GPIOs directly, the input specific driver only gets
enabled if CONFIG_INPUT is enabled and the driver can always be turned
off manually.
This makes gpio-keys behave the same as gpio-leds with CONFIG_LED.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The controller and the driver support two hardware configurations:
- one three-channel (RGB) LED
- or three single-channel LEDs
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Some boards may have connected the enable pin of the chipset to a GPIO.
On these boards, it is necessary to configure and set this GPIO before
using the chipset, otherwise the I2C circuitry is disabled.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add support for LP5009, LP5012, LP5018 and LP5024 devices which only
differ by the number of LEDs they can control.
Also, update application sample to run on all these new supported
devices.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controllers present on Ambiq SoCs implement a PL011 compatible
interface, with some minor differences that require certain quirks.
To support them a dedicated compatible is needed.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Adds a new I2C shim driver for Intel SoCs. Builds upon the SEDI bare
metal I2C driver in the hal-intel module.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The system still takes both prefixed and unprefixed dt-bindings files,
but let's use zephyr/ prefixed in the examples and documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
SPI driver is current working for common SPI devices.
However, addressable LED like WS2812 requires MOSI line to be
default LOW during initialization. This PR adds such option.
This has no effect on common SPI operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
Add initial support for NXP S32 GMAC/EMAC:
- it's a copy-implementation with DMA data buffers and buffer
descriptors in non-cached memory (buf len and ring size configurable)
- PHY interface selection only implemented for S32K3 devices as it is
SoC-specific
- no PHY driver integration, it works as a fixed link with speed/duplex
configured through devicetree
- supports multicast hash filtering, promiscuous mode, MAC loopback
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change the eth-phy definition so that the phy is pointed by a phandle
rather than a child node, make the phy device a child of mdio. This
makes more sense from a devicetree hirearchy where the phandles have to
be initialized before the device itself, allows keeping the priorities
in check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Introduce support for NXP FS26 SBC watchdog. Both Challenger and
Simple watchdog types are supported. Only watchdog functionalities of
the device are supported and any other monitoring feature is either not
supported or disabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's used to pass right device index to hal_intel module.
DT_INST_FOREACH_STATUS_OKAY() does not guarantee the node ordering.
Signed-off-by: Dong D Wang <dong.d.wang@intel.com>
Rename the phy-dev property with phy-handle to match the Linux
ethernet-controller binding and move it up to ethernet.yaml so that it
can be used by other drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adds a new serial shim driver for Intel SoCs. Builds upon the SEDI bare
metal UART driver in the hal-intel module.
Signed-off-by: Nachiketa Kumar <nachiketa.kumar@intel.com>
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add support ADC SAR for NXP S32. ADC SAR diver
support 3 group channels (precision, standard
and external), run normal trigger in oneshot
conversion mode with 2 callbacks normal end
of conversion and normal end chain callbacks.
An instance only run on 1 group channel and
1 kind of callback at the same time.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Enable SPI SDHC driver to manage card power via pwr-gpios property.
Control for this property was previously partially implemented. When
this property is present, the SPI SDHC driver will use it to control
power to the SD card.
Power is toggled during SD init, so this power control can make SD init
more reliable as the power toggle will insure the SD card state is reset.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for HX8394 TFT LCD controller. This controller is driven via
MIPI DSI, and is configured for a 720x1280 display
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
So far pin identifiers were named after CN7 and CN10 connector names on
Nucleo-64 boards. In case of Nucleo-144 there are ST Morpho connectors on
both sides, but bigger (up to 72 instead of 38 pins on each side). First 38
pins out of 72 on each side usually map to the same pins (e.g. PA5 being
13th pin on right ST Morpho connector). This means that single ST Morpho
connector definition will suffice.
Leaving CN7 and CN10 (name of pin headers on Nucleo-64 boards) is confusing
in context of Nucleo-144 boards, since corresponding pin headers are named
CN11 and CN12.
Rename:
* s/ST_MORPHO_CN7_/ST_MORPHO_L_/
* s/ST_MORPHO_CN10_/ST_MORPHO_R_/
so that pin identifiers make more sense in context of Nucleo-144 boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add mailbox and interrupt-controller nodes used for
inter-process communication.
Add also the dt binding for the interrupt-controller.
For now, this is used just to fix some compile errors,
since the mailbox requires an interrupt-controller.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Added a driver for the DFRobot A01NYUB distance sensor. This sensor
sends its readings via UART at 9600 baud. This driver uses interrupts
to read the data from the sensor.
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.
This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit aligns TWIM shim to utilize memory-region property.
The memory-region is not required property that enables user
to specify placement of dma buffers in memory region.
It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Each PSCI interface versions have different DT compatible strings
like arm,psci-0.2, arm,psci-1.1 and so on. However, the same driver
can be used for all the versions by adding #define DT_COMPAT for
required version and #undef DT_COMPAT for default version.
Add support for PSCI cold reset, warm reset and cpu-on function IDs.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
If the optional hardware reset line is available, this change
will use that reset line to assert the uart module and bring
it out of reset state to use.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which controls individual module
reset signals. During each system driver initialization, these
reset signals will be used to bring module out of reset state.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Previously the driver was retrofitted to the kscan api, handling it as a
input device with one row and three columns. With the move to the input
subsystem each input can have its proper input code instead.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The 'zephyr,memory-region-mpu' property was addede gqas a
convenient way to create and configure MPU regions using information
coming from DT. It has been used a lot since it was introduced so I
guess we can consider it a Zephyr success story ™ .
Unfortunately it has been proved to be a bit limited and with some
important limitations:
1. It was introduced as a property of the compatible
zephyr,memory-region that is used to create linker regions and
sections from DT data. This means that we can actually create MPU
regions only for DT-defined regions and sections.
2. The naming is unfortunate because it is implying that it is used only
for MPU.
3. It is misplaced being in include/zephyr/linker/devicetree_regions.h
and still it has nothing to do with the linker at all.
4. It is exporting a function called LINKER_DT_REGION_MPU that again has
nothing to do with the linker.
Point (1) is also particularly limiting because it is preventing us to
characterize memory regions that are not generated using the
'zephyr,memory-region' compatible, like generic mmio-sram regions.
While we fix all the issues, we also want to extend a bit the range of
usefulness of this property. We are renaming it 'zephyr,memory-attr' and
it is now carrying information about the type of memory the property is
attached to (cacheable, non-cacheable, IO, eXecutable, etc...). The user
can use this property and the DT API coming with it to act on the memory
node it is accompanied by.
We are still providing the DT_MEMORY_ATTR_APPLY() macro that can be used
to create the MPU regions as before, but we are adding also a
DT_MEMORY_ATTR_FOREACH_NODE() macro that can be used to cycle through
the memory nodes and act on those.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the driver to support low power mode.
Introduced "enable-low-power" flag in device tree to
control(on/off) low power mode.
If flag added in DTS, during sleep BBLED will switch off the LEDs.
Otherwise BBLED will continue the configured blinking pattern on LEDs.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add support for resetting controller at boot, and update FT5336
documentation to indicate that the FT3267 IC is also supported by this
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for RM67162 MIPI display controller. This controller
is configured to run in MIPI command/DBI mode, driving a 400x392 OLED
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Only setup DPI input from LCDIF if MODE_VIDEO is set, as this
is the the only case where input from the LCDIF would be required to
drive the display. Do not populate the dpi_config structure unless a
reference the the NXP LCDIF device is provided, since this is the output
device providing DPI data.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Make DPI mode an optional configuration for the DSI MCUX 2L driver.
DPI mode will only be enabled when the MIPI is attached in video mode,
since this is when DPI formatted packets are expected.
This will enable the DSI driver to also support DBI/command mode, for
displays that use this format.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enabled support for is31fl3733 driver. This driver supports
the full LED API, and enables the following features of the is31fl3733:
- individual LED dimming
- individual LED enable/disable
- bulk writes of LED enabled and dimming states
- global LED current limit
- blanking (via custom API)
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This driver is built on top of the IVSHMEM doorbell
notification mechanism providing an unified way
to generate inter VM interrupts.
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
Add two new bindings for STM32F1x and F3x RCC to add the ADC prescaler
specific to these series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
AXP192 is a small and simple power management IC featuring different
LDOs, DCDCs, AINs and also GPIOs. It also offers functionaltiy for
battery management.
This change includes the basic regulator driver functionaltiy for
LDO2-3 and DCDC1-3 as well as the mfd driver layer. Further drivers
for GPIO and ADC will follow.
Drivers have been developed and tested on M5StackCore2, an ESP32-based
board. Support for M5StackCore2 is still in progress.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
GT911 IC uses the INT pin to select the correct I2C address during
reset. However, some boards may not route this pin (or may only support
receiving inputs on it). This results in the I2C address selected by the
GT911 IC being arbitrary based on the state of the (floating) INT pin.
To resolve this, introduce an `alt-addr` property for this device. When
set, the INT pin will not be pulled low. Instead, the I2C address will be
probed at runtime, starting with the devicetree address and falling back to
`alt-addr`.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patchset is doing three things:
1. It is fixing the bogus algorithm to find the optimal number of
descriptors for a given memory size.
2. It is changing values for VDEV_STATUS_SIZE and
IPC_SERVICE_STATIC_VRINGS_ALIGNMENT to better align to a usual cache
line size.
3. RX/TX VRINGs are now correctly aligned to MEM_ALIGNMENT (and cache
line alignment).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This patch adds a description section for the pwms property of the PWM
LED child node. This intends to explain how the period field is used by
the led_pwm driver and to help with its configuration.
Reported-by: Scott Worley <scott.worley@microchip.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Convert the GT911 driver to the input subsystem, fix the existing boards
to work in the default config.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Aligns the filename of TI's CC13/26xx system timer peripheral devicetree
binding to its compatible string.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
This adds support for the bosch bmi085 and bmi088. This also includes
support for data sync mode.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This patch adds support for PWM blink which is found in intel's
PCH hardwares.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Adding support for the adafruit can picowbell shield for the
raspberry pi picoi. Also added nodelable for spi0 called 'pico_spi'
as well as an GPIO nexus node 'pico_header'
Signed-off-by: Joseph Yates <joeyatessecond@gmail.com>
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.
This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):
rtc: rtc@... {
compatible = "ti,cc13xx-cc26xx-rtc";
...
timer {
compatible = "ti,cc13xx-cc26xx-rtc-timer";
...
};
counter {
compatible = "ti,cc13xx-cc26xx-rtc-counter";
...
};
pps {
compatible = "ti,cc13xx-cc26xx-rtc-pps";
...
};
};
Or alternatively an MFD pattern with similar requirements.
Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.
Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add SHA256 accelerator support for it8xxx2 series.
This driver passes the following test:
tests/crypto/crypto_hash/
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Changes rshunt-milliohms to rshunt-micro-ohms allowing for current
sensing of greater than 16.4A (1mOhm resistor). This is commonly
set to 100 uOhm for VMU/FMU boards/applications.
Co-authored-by: James Goppert <james.goppert@gmail.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
SIUL2 may require multiple interrupt handlers instead of a single one as
currently supported for S32Z/E. This is needed to enable support on
S32K3.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Support pin control for NXP S32K3 devices and enable it by default on
mr_canhubk3 board configuration.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The clock controller is a singleton controller for all the system-level
clocks (XOSC, PLL, CGM, etc) to provide run-time information to the
peripheral device drivers about the module's clocks.
Clock configuration is not yet supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add a small delay between reading the transport header and reading the
HCI data. Failing to do so on a nRF9160<->nRF52832 link was reliably
resulting in the nRF9160 trying to read data before the nRF52832 had
set up the SPI transaction, resulting in the host reading a buffer full
of 0x00 and having to run the entire read result again.
Transceiving a 10 byte packet takes at least 31uS, while 100 byte
packets are around 150uS (duration of `spi_transceive` call). Waiting
1 tick to eliminate the need for most retransmissions is a valid
tradeoff.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add an option that signifies that the ESP modem may be reset at the same
time as the SoC by an external source. When this is the case, we first
wait for an unsolicited "ready" message from the modem, before
attempting to reset the device. This prevents two initialisation
sequences attempting to run at the same time.
We still want to wait for the complete initialisation sequence to
complete before returning in this case.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
The display controller supports software reset and the driver already
implements it. Therefore it's not necessary to require a reset gpio in
device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Remove `clocks` property for fixed-clock binding.
A fixed-clock should not have an input clock, since by
definition it's an always on fixed-rate clock.
Signed-off-by: Moritz Fischer <moritzf@google.com>
This adds a driver for Texas Instruments Cost-Optimized, Ultra-Small,
12-Bit, System-Monitoring ADCs. Currently only TLA2021 is supported,
TLA2022 and TLA2024 may follow based on this driver.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Convert the XPT2046 driver to the input subsystem, change the api,
remove the callback and enable logic.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Usage of 64-bit address constants from devicetree without a
UINT64_C wrapping macro results in the following warning and the
cut-off of the address value:
"warning: integer constant is so large that it is unsigned"
This change extends devicetree API adding few wrappers over the
address constant getters which add ULL size suffix to an
address integer literal when the appearance of 64-bit address
values is possible
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
Add a GPIO based quadrature decoder driver that reports relative axes
movements using the input subsystem.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adds properties to configure OCTOSPI IO
Manager data lines. That allows to use
any `IOLowPort` and `IOHightPort`.
Note: OSPIM requires additional clock to be enabled.
Please refer to Reference Manual.
Extra clock can be enabled in devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add Nuvoton numaker series UART support, including interrupt-driven,
also apply pinctrl and clock-control.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add support for communication with serial ports on native POSIX platform
via UART driver API. Serial port driver supports polling API,
configuration of the serial ports used via devicetree and command line
options, and runtime configuration with `uart_configure`.
Multiple instances of the driver are supported.
Example use and configuration is also demonstrated in the
`samples/drivers/uart/native_tty` sample.
Closes: #56586
Signed-off-by: Marko Sagadin <marko.sagadin42@gmail.com>
The IS31FL3216A is a fun light LED controller. The LED current of each
channel can be set in 256 steps by adjusting the PWM duty cycle through
an I2C interface.
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
Add a minimal driver for the ti lp5569 led controller. The driver supports
multiple instances. Commands on|off|set_brightness are supported.
Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
Currently, only the presence of a GIC is reflected in the device tree,
and its version must be set separately in each SoC's Kconfig.
This patch adds separate bindings for each GIC version whose presence
in the device tree automatically enables the corresponding Kconfig symbol.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
When the GIC driver was originally introduced, it was only used on
Cortex-R SoCs. However, this is not the case anymore. Update the
description to reflect that this driver is not specific to Cortex-R.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
Add driver for TCN75A temperature sensor. The following features are
supported:
- TCN75A oneshot mode, which allows single shot conversions with lower
power consumtion
- Resolution selection, up to 12 bit resolution (9 bit default)
- Triggering based on temperatue thresholds. If the TCN75A exits a set
threshold range, the application can be notified via a callback.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This PR adds a custom driver for the ADS1112 ADCs. Unlike ADS1113/4/5
family served by the ADS1x1x driver, the ADS1112 does not use an address
pointer to address config registers. Instead, there is only one writable
register and all i2c writes will set it. The registers resemble the
ADS1119 device, but config bitmap is different, include a distinct data
rate table, gain table, and input multiplexing table. There is also not a
status register to be monitored with the ADS1112, as it uses config bit 7
for the same purpose instead of a separate register.
The driver was tested on hardware using the ADC shell interface. Manual
probing validated the voltages for the MUX_SINGLE configs at datarate 15
in CM_SINGLE. Higher gains were not tested and CM_CONTINUOUS is not
supported in this initial implementation.
The new driver has also been added to the existing ADC test using adc_emul
for completeness.
Origin: original
License: Apache 2.0
Purpose: Adding support for ADS1112 ADCs
Signed-off-by: Jordan Montgomery <jordan.montgomery@getcruise.com>
Restructure the Bosch M_CAN driver backend to use per-instance Message RAM
configuration.
This removes the need for a common, artificial "can" devicetree node for
SoCs with multiple Bosch M_CAN-based CAN controllers and allows for
per-instance configuration of the number of e.g. standard (11-bit) and
extended (29-bit) filter elements.
As part of the restructure, software handling of CAN filter flags was moved
from per-flags bitfields to per-filter bitfields, solving an issue when
using more than 32 standard (11-bit) filter elements or more than 16
extended (29-bit) filter elements.
Fixes: #42030, #53417
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch the Bosch M_CAN devicetree binding to use a bosch,mram-cfg property
for specifying the memory layout of the Bosch M_CAN Message RAM. This is
identical to the Linux kernel devicetree binding for Bosch M_CAN IP core
based CAN controllers.
This introduces an offset cell which can be used for controllers with
shared Message RAM between Bosch M_CAN instances.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The BG95 pin configuration does not internally ever use the reset pin.
Because of this, there is no need to make reset pin mandatory.
Commit removes reset pin dependency [e.g. in case of BG95].
Signed-off-by: Andrei Hutanu <andrei.hutanu.i@gmail.com>
Add a property to the ADC channels which allows the configuration
of the current source pin.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Added Input/Output trigger mux address's as properties
that can be passed into the DMA driver. This is intended
to send INPUTMUX signals into the DMA.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Ports the Jinghua Display JHD1313 LCD (with RGB backlight) driver
to use the new auxdisplay driver interface. This driver is used on
the seeed grove LCD RGB display, and replaces it.
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Removed few VIF properties which are being hardcoded
Updated the script to parse source VIF XML and add information to
the output
Added optional Kconfig option to configure custom source VIF XML path
Cleaned up the code
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Adds PHY driver. Works via MDIO API and
exposed ADIN2111 MDIO Clause 45
functions.
Link status detection is triggered by
ADIN2111 driver within offloaded IRQ
handler.
Supports:
- LED0, LED1 enable/disable
- Fatal HW error detection
- AN 2.4V tx mode enable/disable
The initialization order is important.
PHY 2 must be initialized after PHY1.
Therefore, it shall be defined after the 1st one
in the devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds MDIO driver. Works via exposed
ADIN2111 functions.
It is possible to access Clause 45 and 22 registers.
Due to MDIO API limitation Clause 45 access
is done using driver specific MDIO functions.
Provides API and functions for PHY driver.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds initial ADIN2111 2-Port 10BASE-T1L (SPE)
switch support. Works over SPI.
The driver creates 2 interfaces, 1 per port (PHY).
Configures multicast and broadcast filters.
The same unicast is applied to both ports.
Supports:
- Link state detection
- CRC enable/disable
- Ports config set
- Ports ETH stats
Provides functions for MDIO driver.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
The OpenTitan power manager is responsible for changing the OpenTitan's
operation to and from low power state. This patch adds a simple binding
for the power manager's config registers.
This is part of the OpenTitan watchdog patch series. The power manager
HWIP block needs to be configured to enable the watchdog reset
functionality in the OpenTitan Verilator simulation.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The OpenTitan AON Timer is a hardware device that has two features:
the wakeup timer and watchdog timer. This commit series implements the
watchdog feature.
The spec can be found here:
https://opentitan.org/book/hw/ip/aon_timer/index.html
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
This adds support for the USB interface for the
Renesas Smartbond DA1469x device family.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Add an API-less MFD driver for nPM6001. In this case, the MFD device
driver doesn't expose any API as plain I2C API is used within other
device drivers (regulator, GPIO, watchdog). This driver just initializes
some device properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
include the infineon,cat1-scb.yaml for I2c and UART bindings to convey
that they are using SCB (Serial Control Block)
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add a new regulator driver for Analog Devices ADP5360. While it is a MFD
device, only support for BUCK/BUCKBOOST regulators is added in this
patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add VREF+ sensor driver and DT node definition.
This driver allows determining the actual voltage applied to an SoC's
VREF+ pin, by comparing the VREFINT internal bandgap voltage reference
with its factory calibration data.
In packages where VREF+ is bonded to VDDA, this permits direct measurement
of VDDA voltage.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI
driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll
SPI-Flash and DFSS SPI to connect external devices. Both drivers
share most source code, but DFSS uses ARC auxiliary registers.
Move FIFO depth setting to device tree.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Renesas Renesas SmartBond(tm) have two ADC blocks:
GPADC and SDADC.
This change adds drivers for both.
Each ADC supports only one channel setup, drivers allow
to have multiply channels in sequence. Switching
between ADC sources in done in software.
GPADC has 10 bit resolution (accuracy can be increase
with oversampling). Values up to 3.6V can be measured
on selected pins. V30 and VBAT1 can also be measured.
SDADC has 14 bit resolution and can take measurements
from 8 pins (single of differential) and VBAT.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Since Merge zephyrproject-rtos#57360, user can use ch<x> and ch<x>N
simultaneously, which is beneficial for STM32 users
working in motor control area.
Signed-off-by: Savent Gate <savent_gate@outlook.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This driver implement basic functions of ili9342c controller
which comes mostly with IPS displays.
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
The LSM6DSV16X is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSV16X embeds advanced dedicated features such as
a finite state machine (FSM) for configurable motion tracking and a
machine learning core (MLC) for context awareness.
https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Convert the NPCX keyboard scan driver to the input subsystem and add the
input to kscan compatibility driver to maintain functionality with the
current API.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a USB device controller driver skeleton to use as a starting point
for implementing a specific driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Example configuration uses 'A' and 'X' key codes for longpress events.
Described behavior shows correct key codes (30 and 45), however comments
near those key codes were invalid for 'X' key. Fix that.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Allows Ethernet communication between "cells"
in the Jailhouse hypervisor.
The vring queue deviates from a standard virtqueue
so is implemented separately.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This allows finding the correct PCIe device when multiple devices
have the same vendor-id/device-id but differ in the class-rev register
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Use the same wording in description for both I2C and SPI variants to
improve consistency.
Create st,lsm6dsl-common.yaml to include common binding properties from I2C
and SPI variants.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add common LCD interface binding. This binding captures the
following properties, which are shared between multiple LCD interface
IP blocks:
- VSYNC/HSYNC pulse width
- Vertical/Horizontal front and back porch
- HSYNC,VSYNC,data enable, and pixel clock polarity flags
- pixel clock frequency
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Although snps,designware-usb bindings already exist, this one is
prolematic. Compatible is too general and does not reflect
the actual controller IP. It has Zephyr-specific properties,
but has no zephyr prefix. It forces properties that are not
necessary for this controller. We start here with new bare minimum
properties for DesignWare OTG USB 2.0 controller.
The STM32F4 SoC family USB controllers, which are also implement
DesignWare OTG USB 2.0 IP, can also be used with existing drivers,
but require certain quirks. To use these we need special compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Added device tree bindings and implementaion for setting the
spi controllers chip select setup and hold time settings.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
As recommended in AN4760 the memory region where the QSPI flash can be
memory mapped should be configured to be Strongly ordered memory. This
works around an issue where a speculative read from the CPU may cause
later problems with using the QSPI bus.
This avoids #57466.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The LSM6DSO16IS is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSO16IS embeds a new ST category of processing,
ISPU (intelligent sensor processing unit) to support real-time applications
that rely on sensor data. The ISPU is an ultra-low-power, high-performance
programmable core which can execute signal processing and AI algorithms
in the edge.
https://www.st.com/en/mems-and-sensors/lsm6dso16is.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This PR adds a driver for the BMI323, which implements
the following features:
* Enable and disable accelerometer and gyroscope respectively
* Set full scale for accelerometer and gyroscope respectively
* Set data rate for accelerometer and gyroscope respectively
* Get samples (x,y,z) from accelerometer and gyroscope respectively
* Get die temperature
* Set trigger to accelerometer data ready, and accelerometer any motion.
The driver implements device and device runtime power management. If
runtime management is used, it is initialized into the suspended state,
which soft-resets the device to achieve the lowest possible power
consumption, otherwise it is resumed when initialized. When resumed,
the bus is initialized, the feature engine is enabled, and INT1 is
initialized.
The driver only implements the SPI bus at this time. The driver is
prepared to be expanded with I2C support in the future.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
Add the `full-duplex` property for the `microchip,enc28j60` node.
Replace ETH_ENC28J60_0_FULL_DUPLEX Kconfig option with this property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Updated the code to to invoke reset using PCR block
z_mchp_xec_pcr_periph_reset() instead of resetting
using I2C Configuration register
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add the ability for the flash simulator to store its contents in a
memory region.
This allows filesystems on the flash simulator to survive a reboot.
And allows subsystems (e.g. coredump) to store their info on ram while
using the (existing) flash partition backend.
Add a example (for nucleo_f411re) that shows how to configure the flash
simulator for hardware (cfg discussion #54166).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
Add support for a generic NTC, `ntc-thermistor-generic`. In this case,
the compensation table is provided via devicetree. Note that DT property
is prefixed with `zephyr,`, because while hardware related, it is linked
to a particular software implementation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactor driver to align a bit more with its Linux counterpart, ie,
ntc_thermistor. This driver did quite a few _unconventional_ things,
like using "zephyr," compatibles, a dedicated node for pre-computed
compensation table (referenced by the actual pseudo-device node), etc.
The comparison helper function should likely be simplified as well (to
avoid the need for custom wrapper for bsearch), but this can be done
later.
In this refactor, each thermistor gets a compatible, e.g. "epcos,xxxx".
Compatibles are known by the driver, so are compensation tables. This
simplifies devicetree files. There's no need to bother about
compensation tables in **every** board file if Zephyr supports a certain
NTC model.
In general we should respect Linux bindings, which in the end influence
how drivers are implemented. In this case, this principle resulted in
simplified, easier to use code.
For future developers, this is how support for a new NTC can be added:
1. Add to the end of the driver:
```c
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT vnd_model
static __unused const struct ntc_compensation comp_vnd_model[] = {
{ x, y },
...,
};
#define DT_INST_FOREACH_STATUS_OKAY_VARGS(NTC_THERMISTOR_DEV_INIT,
DT_DRV_COMPAT, comp_vnd_model)
```
3. In driver's Kconfig make sure it depends on
DT_HAS_$DT_DRV_COMPAT$_ENABLED
Note: $X$ means _value_ of X.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It looks like the Zephyr thermistor driver bindings were half-copied
from Linux ntc-thermistor. Zephyr principle is to maintain compatibility
with Linux, when possible, so there's no reason to deviate here. Convert
the connection type from a custom enum to a boolean, as Linux does.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Initial sensor driver for NPM1300 PMIC charger.
Includes basic configuration of charger voltage and current.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
All Nucleo boards provide the ST Morpho connector/header, which exposes
all pins of the MCU. It is tipically used in ST shields, so provide a
nexus node to allow creating generic shields.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch introduces support for NXP S32 CANEXCEL (CANXL) peripheral.
CAN protocol supporting:
- CAN classic
- CAN FD
Remote transmission request is not supported as this feature is not
available on NXP S32 CANXL HAL.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This patch adds support for the TI INA3221 current monitor.
This is the datasheet used for reference:
https://www.ti.com/lit/gpn/ina3221
Since this device has three channels, there is a custom attribute to
select which channel is to be used when getting a sample.
Measurements are done on all enabled channels.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Make it possible to use CPOL/CPHA SPI clock modes with the SDHC driver.
Some cards require the clock to switch to low when not active.
Signed-off-by: Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
Add a binding for STM32 ADC to specify the resolutions and all associated
register information (through a STM32_ADC_RES macro).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Remove build asserts in favor of DT enums
- Remove power level property since it is unused by SDK
- Correct voltage ref value in DT to correspond to
chip specific values documented in reference manuals
instead of corresponding to SDK enum names.
- Fix SOC devicetrees affected by these changes.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This is a new parameter to divide the LPTIM input clock
by a prescaler, changing the max reachable timeout of the LP timer.
It will divide the LPTIM input clock by 1 (reset value) up to 128.
The lptim configuration register is written with a 3bit value.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implements a UART driver using PIO. Both PIOs are supported.
Only polling API is supported. Only 8N1 mode is supported.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Added a generic driver for RaspberryPi Pico PIO.
This driver is an intermediate driver for abstracting the PIO
device driver from physical pin configuration.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
Add STM32WL-specific sx126x_set_tx_params function based on the
STM32CubeWL modifications to LoRaMac-node.
Add the "power-amplifier-output" DT property to
"st,stm32wl-subghz-radio" for selecting between the RFO_LP and RFO_HP
output configurations provided by the above mentioned function.
Add the "rfo-lp-max-power" and "rfo-hp-max-power" DT properties for
defining the maximum design power of the respective outputs' matching
networks.
closes#48511
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Adds a retention system which builds on top of retained_mem
drivers to allow partitioning of areas and data integrity with
magic header prefixes and checksum of stored data.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This commit makes the alarms-count dts property of the
rtc-device.yaml optional, setting the default to 0.
This simplifies the dts rtc dts node by not requiring
the property to be set to 0 if it is not supported.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
- Add initial version of Infineon CAT1 i2c driver.
- Add initial version of binding file for Infineon
CAT1 I2C driver
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Move the devicetree bindings for Analog-to-Digital Converters (ADCs)
from dts/bindings/iio/adc to dts/bindings/adc as Zephyr does not have
an IIO layer.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
On iMX.RT devices, the number of GPIO pins exceeds the maximum of
64 that the PINT interrupt controller can support. Therefore, two
interrupt lines are now shared between the GPIO modules.
This patch allows the user to set the interrupt source for a GPIO
peripheral. For most LPC devices, this will always be the PINT. For some
RT devices, the PINT cannot use pins on GPIO modules other than 0 and 1
as input, and thus the INTA and INTB sources should be used.
Since Zephyr does not support sharing these interrupt between all GPIO
controllers, the user must configure a subset of all GPIO controllers to
use the shared module interrupts. An example of how to do so is provided
for the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce PINT driver, for NXP pin interrupt and pattern match engine.
The driver currently supports only the pin interrupt feature of the
PINT.
Add DTS entires for the PINT on LPC and RT devices that support this
peripheral, and remove the interrupt defintions that are PINT specific
from the GPIO module on these devices.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The I2CLCTL_MLCS setting was recently added to MTL
platform. LNL has these registers in separate space, therefore
new field is added to intel,ssp-dai.yaml and appropraite definitions
to LNL device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Repleace usage of shim2 device tree field with hdamlssp.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In current implementation the HDAMLI2SL register is represented by
shim2 field in common SSP device tree file. This could be misleading
since the filed is is different location to I2S IP.
Adding separate device for this register following DMIC case.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A recent change added the stop-bits and data-bits to the base
uart-controller binding, meaning it's no longer required to
be added in the Altera specific binding.
This requires no further changes because its only use is in
uart_altera.c where only the index of the enum is used,
which remains the same between the new implementation and
how it was previously implemented in the altera specific binding.
Relevant commit: 0234f12
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add the header file required for the example to work. Users get the
following error due to unresolved INPUT_BTN_* values otherwise:
parse error: expected number or parenthesized expression
Signed-off-by: Amit Kucheria <amitk@kernel.org>
Signed-off-by: Amit Kucheria <amit@mbedrock.com>
These bindings are removed because they are now handled in the
included base uart-controller.yml.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add bindings for LTC1665/LTC1660, which is a 8/10-bit
Digital-to-Analog Converter with eight individual channels.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
This addition should help users to better understand potential issues
with domain clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In ACE 2.0 platform (LNL) dmic got two new shim register ranges.
DMIC driver need to program them to configure the interface.
This patch adds new shims to device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
The temperature sensor of the STM32F0x0 is similar to C0 (with one value
for calibration) but uses a negative coefficient, so we add it to the
bindings, just like in st,stm32-temp.yaml
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a devicetree binding for the CAN-FD capable variant of the NXP FlexCAN
controller. Add example devicetree snippets to both NXP FlexCAN and NXP
FlexCAN-FD binding documentation to limit confusion.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the nxp,kinetis-flexcan devicetree compatible to nxp,flexcan as it
is not specific to the NXP Kinetis series.
This is preparation for adding a nxp,flexcan-fd binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add new compatible to separate production calibrated sensors
with single and dual calibration temperatures. Also update
stm32_temp driver to support single calibration sensors.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
Adds support for a devicetree property that controls the ClockDiv
value provided to the SDIO during init.
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Arm fvp_baser_aemv8r and fvp_base_revc_2xaemv8a boards are using
SMSC91C111 as their ethernet adapters.
Portions of the codes are based on FreeBSD code from its
'src/sys/dev/smc/if_smc.c' and 'src/sys/dev/smc/if_smcreg.h'.
This driver has two parts, one is the ethernet controller driver, which
is MAC layer driver. The other is the MDIO driver, which is the PHY
layer driver. Both of them are in the same source file due to that they
need to share the same reading and writing register functions and
the smsc object.
The mdio driver is needed by the existing 'phy_mii' driver, which is
a driver for the generic MII-compliant PHY.
This driver was developed under the fvp_base_revc_2xaemv8a target and
has been tested on the fvp_baser_aemv8r target.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
move DT_DRV_COMPAT to bmm150.h. so that can be decide which interface
to use.
define struct bmm150_bus_io interface for bmm150_i2c.c and bmm150_spi.c
in bmm150.h.
redefined bus operation interface in bmm150.c, this allow the driver
to decide which interface to use during construction.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Convert the SDL driver to use the input subsystem. This is specifically
meant to emulate touchscreen drivers, so it's setup to send triplet of
x, y, touch for touch-on events and just touch off on touch off events.
Renamed the driver to input-sdl-touch since now we can also develop an
sdl driver for simulating key events.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds support for ANY_MOTION and DATA_READY interrupts for
the BMI270. To implement this, a different config blob than the
"max_fifo" blob has to be used.
Signed-off-by: Benjamin Lindqvist <benjamin@eub.se>
This adds the i2c driver for the Renesas SmartBond(tm) MCU family.
It supports blocking transfers and callback transfers.
Currently only supports controller mode.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Under disk bindings. NVMe is a purely PCIe based technology, thus the
relevant includes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This adds a driver for the DS2482-800 1-wire multi channel bus driver.
The driver uses a split architecture in order to share a common lock
among all configured channels of a single IC.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Add test for the experimental feature GPIO_ENABLE_DISABLE_INTERRUPT,
which covers APIs gpio_pin_interrupt_enable() and
gpio_pin_interrupt_disable().
Signed-off-by: Sung-Chi Li <lschyi@google.com>
Use the LTDC in combination with the DSI HOST makes the pinctrl obsolete.
DSI HOST has dedicated pins.
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
The driver has been recently moved under the input subsystem but the
corresponding driver was left over. Move it from kscan to input.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Give precision to the description of the dma phandle in the
quadspi node.
When a DMAMUX is present and enabled, the channel is the dma one
(not dmamux channel) and the request is given by the DMAMUX.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The emulated RTC device driver is used to emulate a real
RTC device. Note that it is not a replacement for the
native_rtc module, which is used to control simulated time,
get time from the host system, etc.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
This test suite adds tests for the following:
- Setting and getting time
- Validating time is incrementing correctly
- Validating behavior of alarms with callback disabled
- Validating behavior of alarms with callback enabled
- Validating update callback
The test suite uses the devicetree alias rtc to find
the device to test.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
Add optional filter value properties. The filter is disabled by default
but can be enabled by setting the filter-sample-period > 0 in the dts
file. A latency is introduced if the filter is enabled. The latency can
be printed by setting sensor log level to debug.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
This commit implements the temperature sensor interface for
the Maxim MAX31865 SPI Temperature Sensor.
Signed-off-by: Fin Maaß <fin.maass@haw-hamburg.de>
Co-authored-by: Armin Brauns <armin.brauns@embedded-solutions.at>
In ACE 2.0 platform (LNL) ssp got new shim registers.
SSP driver need to program them to configure the interface.
This patch adds new shims to device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds definition of ACE 2.0 Lunar Lake board.board.
Signed-off-by: Krzysztof Frydryk <Krzysztofx.Frydryk@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds tmd2620 driver and devicetree bindings to work in
trigger and polling mode supporting Power management.
Signed-off-by: Peter Fecher <p.fecher@phytec.de>
Add LEDC device for esp32s3
Update PWM LED binding
Remove invalid comment from driver source file
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Enabled simultaneous support by adding a DTS variable named “io-mapped”.
There are 3 possibilities through instance in dtsi file.
Under PCIe, PCIe ns16550.
Under soc and has a variable io-mapped, legacy(IO mapped).
Under soc and don’t have a variable io-mapped, MMIO mapped.
Simultaneous access can be enabled by a Kconfig.
For PCIe instances UART initialization should be done post-kernel as it
depends on PCIe initialization.
Co-authored-by: Najumon BA <najumon.ba@intel.com>
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Add the `zephyr,pm-device-runtime-auto` flag to `pm.yaml` and
`struct pm_device`.
This flag is intended to signify to the boot system that device runtime
PM should be automatically enabled on the device after the init function
has run.
Only run `pm_device_runtime_auto_enable` function on a device if
initialisation succeeded. This prevents actions being run on devices
that are not ready.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add a driver that listens for input events and reports them on a kscan
API. This allows porting kscan drivers to the input APIs while
maintaining compatibility with the existing kscan based applications.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Update DMA bindings with DMA config macros
only for st,stm32-dma-v2.yaml and st,stm32-dma-v2bis.yaml
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Adds the new stm32h5 serie to the list of st,stm32g0-exti
compatible : now the matching targets is C0/G0/H5/U5/L5/MP1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add binding and sensor attribute to allow single phase
mode where only one signal is required from the encoder.
The signal must be connected to Phase A input.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a GPIO nexus binding for Pmod interface connectors.
This commit also includes a header file with macros
that map signal names in the Pmod specification to
the corresponding indices in the GPIO nexus, meant for
use in devicetree files.
Signed-off-by: Alexander Mihajlovic <alexander@eub.se>
Add an input device to take input key events as an input and generates
short press or long press devices as output.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The number of available EasyDMA MAXCNT bits is now defined per-instance
in Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Deleted adc_mchp_xec.c and microchip,xec-adc.yaml file.
DTSI, yaml, CMakeLists.txt and Kconfig.xec files are
updated for compatible.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and
MEC15xx SOC.
ADC smapling clock configuration updated using DTS.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The regulator driver has a configured min/max range that is used
to limit set values, and to initialise the regulator.
A new init value has been added, so that the startup voltage can
be higher than the lowest permitted value.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Added initial version of Infineon cyw43xxx BT (
H4 HCI extension drivers/bluetooth/hci/CMakeLists.txt)
Add initial version of binding file for Infineon CYW43xx BT
HCI extension driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This adds a basic Intel TCO watchdog driver. The driver doesn't support
windowed timeouts (a non-zero window.min value) or callbacks. The driver
currently assumes TCO version 6, which can be found e.g. on Elkhart Lake
and Raptor Lake platforms. The driver also expects the TCOBA base
address to be specified through DTS, rather than doing runtime lookup
(using e.g. ACPI or PCIe).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Remedial rework to handle the enabling of the I2S master clock
output based on the presence of an introduced DT property.
For details see issue/54841.
Signed-off-by: Raul Pando <raul.pando@bytegrity.co.uk>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add support for the TI TPS382x series. The IC has an input pin which
should be toggled by the processor and a output pin which should be
connected to the RESET input of the processor. The timeout is not
configurable.
This device can be used by devices which does not have any internal
hardware watchdog device.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.
Adapting dtsi for all SoCs and adapting test configuration.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Adds a driver for the Nordic nRF GPREGRET registers and adds
entries to the SoCs for this peripheral.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support for virtual UART device that uses ARC Hostlink channels
for data transfers. Due to the Hostlink principle, this driver
supports only polling API.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This symbol allows users of the driver to disable the
power management feature of just this sensor if they are
not using the int_gpios pin of the BQ274XX.
Signed-off-by: Nick Ward <nix.ward@gmail.com>
interrupts property was previously added with "required: false", but
when required was removed (redundant), the interrupts property was left
dangling.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
To enable Bluetooth controller coexistence feature, there is
implementation of ticker task, which aborts any ongoing radio events
during assertion of the grant pin. This solves the co-existence issue
in the role of the subordinate transceiver.
Signed-off-by: Tomáš Beneš <tomas@dronetag.cz>
The zephyr,gpio-keys is now emitting input events, so it makes sense to
require a key code to be set. Change the zephyr,code property to be
required and add an example in the binding description.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Port the gpio_keys_zephyr driver from the gpio subsystem with a
dedicated API to the input subsystem reporting input events.
Move the test as well, simplify the cases a bit since the API is simpler
now.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.
Also make it the same type as `config_delay_us` (`uint16_t`).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The board embeds an audio codec IC, Cirrus CS42L73. While there is no
in-tree driver for it, we need a binding to describe how it is wired in
the board, e.g. for IRQ/RESET lines.
Following Linux binding for the same IC, create one in
dts/bindings/sound. Note that Linux binding is less complete/outdated.
Ref. https://statics.cirrus.com/pubs/proDatasheet/CS47L63_DS1249F2.pdf
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add driver for Xptek XPT2046 resistive touch controller on SPI.
Only interrupt driven mode supported, does not do polling.
Signed-off-by: Seppo Takalo <seppo.takalo@iki.fi>
Introduce driver for NXP DCNANO LCDIF (lcd interface) peripheral,
present on iMX.RT500. Currently this driver only supports updating
the primary framebuffer, and does not implement support for the cursor
buffer present on this IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for MCUX MIPI DSI 2L. This IP block differs slightly from
the existing MCUX MIPI peripheral, and uses a different hardware
abstraction layer. For these reasons, a new driver was introduced rather
than extending the existing mcux_dsi implementation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of AHB RX buffer allocation. This allows sections
of the AHB RX buffer to be reserved for specific masters, which can
enhance performance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The driver utilizes ST Microelectronics library (which
exists in modules\hal\st\sensor\vl53l1x. Platform specific
headers and source files used by the library are included
and adapted for Zephyr.
The driver can be configured in proj.conf to use a
interrupt/polling methods and the use of the XSHUT pin on
the VL53L1X. All uses were tested successfully.
Signed-off-by: Mark Watson <mwatson@prosaris.ca>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Add support for configuring power on delay when using SPI SDHC. This
allows cards that reliably initialize with a shorter (1ms) delay to
avoid the long initialize delay otherwise imposed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add I2C bus recovery support to the STM32 v1 and v2 driver. The STM32 i2c
peripheral does not natively support I2C bus recovery so recovery is
performed using GPIO bitbanging. This mirrors the bus recovery
implementation for NXP MCUX LPI2C driver.
Fixes: zephyrproject-rtos#54917
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
Added initial version of Infineon CAT1 GPIO driver.
Added initial version of binding file for Infineon CAT1 GPIO driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Provide dts binding for F412 PLL I2S.
This I2S dedicated PLL is fully configurable and take same
input as Main PLL
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F412 and F413 parts for instance.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide dts binding for F4 PLL I2S.
This PLL share input source and input M diviso with F4 Main PLL.
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F401 parts for instance.
Additionally, provide related header definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
