ITE: drivers/pinctrl: Add alternate function additional setting
When the alternate setting is configured as func3, in addition to the setting of func3-gcr, some pins require external setting. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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63badb0fa7
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dca9cbff08
4 changed files with 53 additions and 22 deletions
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@ -24,6 +24,10 @@ struct pinctrl_it8xxx2_gpio {
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uintptr_t func3_gcr[GPIO_GROUP_MEMBERS];
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/* function 3 enable mask */
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uint8_t func3_en_mask[GPIO_GROUP_MEMBERS];
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/* function 3 external control register */
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uintptr_t func3_ext[GPIO_GROUP_MEMBERS];
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/* function 3 external mask */
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uint8_t func3_ext_mask[GPIO_GROUP_MEMBERS];
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/* function 4 general control register */
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uintptr_t func4_gcr[GPIO_GROUP_MEMBERS];
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/* function 4 enable mask */
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@ -132,6 +136,7 @@ static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin;
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volatile uint8_t *reg_func3_gcr = (uint8_t *)(gpio->func3_gcr[pin]);
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volatile uint8_t *reg_func4_gcr = (uint8_t *)(gpio->func4_gcr[pin]);
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volatile uint8_t *reg_func3_ext = (uint8_t *)(gpio->func3_ext[pin]);
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/* Handle PIN configuration. */
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if (pinctrl_it8xxx2_set(pins)) {
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@ -155,6 +160,11 @@ static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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/* Common settings for alternate function. */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_INPUT |
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GPCR_PORT_PIN_MODE_OUTPUT);
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/* Ensure that func3-ext setting is in default state. */
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if (reg_func3_ext != NULL) {
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*reg_func3_ext &= ~gpio->func3_ext_mask[pin];
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}
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switch (pins->alt_func) {
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case IT8XXX2_ALT_FUNC_1:
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/* Func1: Alternate function has been set above. */
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@ -169,6 +179,11 @@ static int pinctrl_gpio_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
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* Func3 also need to set the general control.
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*/
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*reg_func3_gcr |= gpio->func3_en_mask[pin];
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/* Func3-external: Some pins require external setting. */
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if (reg_func3_ext != NULL) {
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*reg_func3_ext |= gpio->func3_ext_mask[pin];
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}
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break;
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case IT8XXX2_ALT_FUNC_4:
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/*
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@ -327,11 +342,6 @@ static int pinctrl_it8xxx2_init(const struct device *dev)
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*/
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gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
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/*
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* TODO: If UART2 swaps from bit2:1 to bit6:5 in H group, we
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* have to set UART1PSEL = 1 in UART1PMR register.
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*/
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
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/*
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* Swap the default I2C2 SMCLK2/SMDAT2 pins from GPC7/GPD0 to GPF6/GPF7,
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@ -345,23 +355,25 @@ static int pinctrl_it8xxx2_init(const struct device *dev)
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return 0;
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}
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#define INIT_UNION_CONFIG(inst) \
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COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
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(.gpio = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}), \
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(.ksi_kso = { \
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.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
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.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
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}) \
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#define INIT_UNION_CONFIG(inst) \
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COND_CODE_1(DT_INST_PROP(inst, gpio_group), \
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(.gpio = { \
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.reg_gpcr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.func3_gcr = DT_INST_PROP(inst, func3_gcr), \
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.func3_en_mask = DT_INST_PROP(inst, func3_en_mask), \
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.func3_ext = DT_INST_PROP_OR(inst, func3_ext, {0}), \
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.func3_ext_mask = DT_INST_PROP_OR(inst, func3_ext_mask, {0}), \
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.func4_gcr = DT_INST_PROP(inst, func4_gcr), \
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.func4_en_mask = DT_INST_PROP(inst, func4_en_mask), \
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.volt_sel = DT_INST_PROP(inst, volt_sel), \
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.volt_sel_mask = DT_INST_PROP(inst, volt_sel_mask), \
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}), \
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(.ksi_kso = { \
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.reg_gctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \
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.reg_ctrl = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \
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.pp_od_mask = (uint8_t)DT_INST_PROP(inst, pp_od_mask), \
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.pullup_mask = (uint8_t)DT_INST_PROP(inst, pullup_mask), \
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}) \
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)
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#define PINCTRL_ITE_INIT(inst) \
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@ -14,6 +14,15 @@ properties:
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func3-en-mask:
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type: array
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func3-ext:
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type: array
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description: |
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When the alternate setting is configured as func3, in addition to
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the setting of func3-gcr, some pins require external setting.
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func3-ext-mask:
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type: array
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func4-gcr:
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type: array
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@ -198,6 +198,10 @@
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NO_FUNC 0xf016f5 0xf016f5 NO_FUNC>;
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func3-en-mask = <0 0x20 0x20 0
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0 0x04 0x08 0 >;
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func3-ext = <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
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NO_FUNC 0xf03a23 0xf03a23 NO_FUNC>;
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func3-ext-mask = <0 0 0 0
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0 0x01 0x01 0 >;
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func4-gcr = <NO_FUNC 0xf016f5 0xf016f5 NO_FUNC
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NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
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func4-en-mask = <0 0x04 0x08 0
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@ -383,6 +383,12 @@
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uart2_tx_gph2_default: uart2_tx_gph2_default {
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pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_4>;
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};
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uart2_rx_gph5_default: uart2_rx_gph5_default {
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pinmuxs = <&pinctrlh 5 IT8XXX2_ALT_FUNC_3>;
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};
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uart2_tx_gph6_default: uart2_tx_gph6_default {
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pinmuxs = <&pinctrlh 6 IT8XXX2_ALT_FUNC_3>;
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};
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uart2_rx_gpf0_default: uart2_rx_gpf0_default {
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pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_3>;
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};
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