SMP support on cAVS is implemented by using uncached addresses
for all writable data sections except for stack, i.e. for .data,
.bss and some other specialised ones. So far that has been
implemented for cAVS 1.5. This patch does the same for cAVS 1.8.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Make the divide instruction not being optimized of the ztest example
test case. Do this because it will be replaced by invalid opcode
exception instruction generated by GCC.
Fixes#33403.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
In this example, python test case get the running directory by handling
the "--cmdopt" option passed by pytest.
Signed-off-by: YouhuaX Zhu <youhuax.zhu@intel.com>
1. Add a class of Pytest(Harness) which can handle pytest script
in harness.py
2. Use running_dir to store current test directory which be
used in pytest scrpt.
3. Add usage of this feature into zephyr doc.
Signed-off-by: YouhuaX Zhu <youhuax.zhu@intel.com>
This is mainly a feature release which includes a few ways to speed up
'west update', along with a couple of fixes and other changes.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When multithreading is off, kernel source files like sem.c (samphore
implementation) are not present in the build. Some platforms by default
fetch modules or drivers that are using multithreading primitives and
because of that fails to compile when multithreading is off.
Limit the test to only qemu platforms since test is arch specific.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
reg value should match value provided within node name (as in pll@2).
Fix this to avoid warning.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The STM32H7x flash has an integrated ECC that can correct single
errors and detect double errors. When a double ECC error is detected,
the DBECCERR1/2 flag is raised and there is a bus fault.
We now mask this bus fault and check the error flags. ECC errors are
logged with the offset of the data. Single ECC errors cause a warning
to be logged and double ECC errors return -EIO.
Fixes#33140.
Signed-off-by: Göran Weinholt <goran.weinholt@endian.se>
Switch to using I2C0 as this I2C controller on the FRDM-K64F is actually
configured (pinmux) for use and is available on an arduino header if
someone would wire up an adxl372 to it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add pinctrl-0 as being required on NXP Kinetis DTS bindings for I2C,
FTM, UART, and DSPI related devices.
Other devices like ethernet and CAN are utilized outside of just the
Kinetis family and thus we can not require pinctrl-0 property for them
at this time.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As the KW2XD is a SiP (System-in-package) the SPI1 controller on the MCU
is connected to the modem. As the pinctrl details for this in the
SoC dtsi file as these pins are not exposed in the pindata XMLs from
NXP.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Set SPI0 controller to default to being disabled in SoC dtsi files and
having the board dtsi files enable it. The only board that wasn't doing
this already was the frdm_kw41z.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The devicetree enables i2c0 and ftm1 but these devices are connected to
anything on the board so they shouldn't be enabled. Remove them from
being enabled by the board devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we have specific bindings for STM32F100 devices,
we need dedicated treatment for PLL source HSI case.
Otherwise, we end up using undefined symbol STM32_PLL_PREDIV1.
Please note that previous code compiled, it was assigning
a wrong value to prediv. This had no consequence because
prediv value is forced in Cube LL functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert board to use of device tree for clocks configuration.
Note: Fixed sys clock frequency that was not taking into account
systematic /2 divisor when HSI is selected as pll source.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add specific binding for stm32f100 pll which differs from existing
stm32f1 and stm32f105 specific pll binding.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
