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boards: waveshare_open103z: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-05-04 10:32:00 +02:00 • committed by Kumar Gala
commit fe9cfb2ffd
2 changed files with 20 additions and 13 deletions
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19
boards/arm/waveshare_open103z/waveshare_open103z.dts
View file

@ -77,6 +77,25 @@
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
current-speed = <115200>;

14
boards/arm/waveshare_open103z/waveshare_open103z_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103XE=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# enable uart driver
CONFIG_SERIAL=y
@ -17,15 +15,5 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# enable clocks
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not to exceed 36MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1