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boards: 96b_stm32_sensor_mez: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-05-03 17:28:12 +02:00 • committed by Kumar Gala
commit 9ebf2623bc
2 changed files with 23 additions and 22 deletions
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22
boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts
View file

@ -51,6 +51,28 @@
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <84>;
div-p = <2>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&i2s2 {
status = "okay";

23
boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig
View file

@ -3,9 +3,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F446XX=y
# 84MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -24,23 +21,5 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=16000000
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=84
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not exceed 50MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1