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boards: 96b_aerocore2: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-05-03 17:05:49 +02:00 • committed by Kumar Gala
commit dbba80886d
2 changed files with 23 additions and 22 deletions
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22
boards/arm/96b_aerocore2/96b_aerocore2.dts
View file

@ -40,6 +40,28 @@
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
&pll {
div-m = <24>;
mul-n = <336>;
div-p = <2>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(168)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
current-speed = <115200>;

23
boards/arm/96b_aerocore2/96b_aerocore2_defconfig
View file

@ -3,8 +3,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F427XX=y
# 168MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=168000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -24,24 +22,5 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=24000000
# produce 168MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=24
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=7
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not exceed 50MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=4
CONFIG_CLOCK_STM32_APB2_PRESCALER=2