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boards: 96b_argonkey: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-05-03 17:12:20 +02:00 • committed by Kumar Gala
commit 08ffa0c4f4
2 changed files with 24 additions and 23 deletions
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23
boards/arm/96b_argonkey/96b_argonkey.dts
View file

@ -46,6 +46,29 @@
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <84>;
div-p = <2>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
/* APB2 clock is fixed at 42MHz to prevent known SPI/I2S bug */
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
current-speed = <115200>;

24
boards/arm/96b_argonkey/96b_argonkey_defconfig
View file

@ -3,9 +3,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F412CG=y
# 84MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -21,28 +18,9 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=16000000
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=84
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not exceed 50MHz limit
# APB2 clock is fixed at 42MHz to prevent known SPI/I2S bug
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=2
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y