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boards: 96b_neonkey: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-05-03 17:23:43 +02:00 • committed by Kumar Gala
commit 8dcb58675f
2 changed files with 21 additions and 20 deletions
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20
boards/arm/96b_neonkey/96b_neonkey.dts
View file

@ -56,6 +56,26 @@
};
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <16>;
mul-n = <336>;
div-p = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
current-speed = <115200>;

21
boards/arm/96b_neonkey/96b_neonkey_defconfig
View file

@ -3,9 +3,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F411XE=y
# 84MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -21,25 +18,9 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=16
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not exceed 50MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y