Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Add Flash HP support for ra6-cm4, ra6-cm33, ra4-cm33 (except
r7fa4w1ad2cng)
- Add config to set the minimal size of data which can be written
for RA4E2, RA4M2, RA4M3, RA6E1, RA6E2, RA6M1, RA6M2, RA6M3, RA6M4,
RA6M5
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/G3S
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This adds minimal support for a new SoC Renesas RZ/G3S
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Remove the renesas,ra-pinctrl driver, which is no longer
needed after migrating to the FSP-based implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Since the Option Setting Memory area is set in FSP, the Kconfig value
switches between using the FSP implementation or the existing
Option Setting Memory implementation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add condition for KConfig Renesas FSP hal module
Move the DUAL_BANK_MODE from SOC to flash driver KCONFIG
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Update pinctrl driver which used for Renesas RA series with
PFS secure register
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Initial commit to suppor RA8D1 SoC
This is deveop base on RA8M1 so it will have similar stucture and
feature
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
RA4M1-specific options were being applied system-wide because
conditions were not set properly.
This change fixes this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
