drivers: adc: initialize to add ADC driver
Add minimal ADC driver code for EK-RA8M1 board Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com> Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
This commit is contained in:
parent
d7fa28bf72
commit
4cebe5354f
15 changed files with 557 additions and 1 deletions
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@ -35,4 +35,12 @@
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drive-strength = "medium";
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};
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};
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adc0_default: adc0_default {
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group1 {
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/* input */
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psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
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renesas,analog-enable;
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};
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};
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};
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@ -7,7 +7,7 @@
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#include <renesas/ra/ra8/r7fa8m1ahecbd.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include "ek_ra8m1-pinctrl.dtsi"
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/ {
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@ -152,3 +152,9 @@ mikrobus_serial: &uart3 {};
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pinctrl-0 = <&iic1_default>;
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pinctrl-names = "default";
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};
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&adc0 {
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status = "okay";
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pinctrl-0 = <&adc0_default>;
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pinctrl-names = "default";
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};
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@ -52,3 +52,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NUMAKER adc_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200 adc_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU adc_mcux_gau_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ adc_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA adc_renesas_ra.c)
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@ -130,4 +130,6 @@ source "drivers/adc/Kconfig.ene"
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source "drivers/adc/Kconfig.ambiq"
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source "drivers/adc/Kconfig.renesas_ra"
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endif # ADC
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12
drivers/adc/Kconfig.renesas_ra
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12
drivers/adc/Kconfig.renesas_ra
Normal file
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@ -0,0 +1,12 @@
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# Renesas RA Family
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config ADC_RENESAS_RA
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bool "Renesas RA ADC"
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default y
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depends on DT_HAS_RENESAS_RA_ADC_ENABLED
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select USE_RA_FSP_ADC
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help
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Enable Renesas RA ADC Driver.
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390
drivers/adc/adc_renesas_ra.c
Normal file
390
drivers/adc/adc_renesas_ra.c
Normal file
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@ -0,0 +1,390 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_adc
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/logging/log.h>
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#include <instances/r_adc.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(adc_ra, CONFIG_ADC_LOG_LEVEL);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define ADC_RA_MAX_RESOLUTION 12
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void adc_scan_end_isr(void);
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/**
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* @brief RA ADC config
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*
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* This structure contains constant data for given instance of RA ADC.
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*/
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struct adc_ra_config {
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/** Number of supported channels */
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uint8_t num_channels;
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/** pinctrl configs */
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const struct pinctrl_dev_config *pcfg;
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/** function pointer to irq setup */
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void (*irq_configure)(void);
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};
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/**
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* @brief RA ADC data
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*
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* This structure contains data structures used by a RA ADC.
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*/
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struct adc_ra_data {
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/** Structure that handle state of ongoing read operation */
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struct adc_context ctx;
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/** Pointer to RA ADC own device structure */
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const struct device *dev;
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/** Structure that handle fsp ADC */
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adc_instance_ctrl_t adc;
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/** Structure that handle fsp ADC config */
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struct st_adc_cfg f_config;
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/** Structure that handle fsp ADC channel config */
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adc_channel_cfg_t f_channel_cfg;
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/** Pointer to memory where next sample will be written */
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uint16_t *buf;
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/** Mask with channels that will be sampled */
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uint32_t channels;
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/** Buffer id */
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uint16_t buf_id;
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};
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/**
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* @brief Setup channels before starting to scan ADC
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*
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* @param dev RA ADC device
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* @param channel_cfg channel configuration
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*
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* @return 0 on success
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* @return -ENOTSUP if channel id or differential is wrong value
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* @return -EINVAL if channel configuration is invalid
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*/
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static int adc_ra_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg)
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{
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fsp_err_t fsp_err = FSP_SUCCESS;
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struct adc_ra_data *data = dev->data;
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if (!((channel_cfg->channel_id >= 0 && channel_cfg->channel_id <= 2) ||
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(channel_cfg->channel_id >= 4 && channel_cfg->channel_id <= 8) ||
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(channel_cfg->channel_id >= 16 && channel_cfg->channel_id <= 19))) {
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LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
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return -ENOTSUP;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("Acquisition time is not valid");
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return -EINVAL;
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}
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if (channel_cfg->differential) {
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LOG_ERR("unsupported differential mode");
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return -ENOTSUP;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("Gain is not valid");
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return -EINVAL;
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}
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data->f_channel_cfg.scan_mask |= (1U << channel_cfg->channel_id);
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/* Configure ADC channel specific settings */
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fsp_err = R_ADC_ScanCfg(&data->adc, &data->f_channel_cfg);
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if (FSP_SUCCESS != fsp_err) {
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* Interrupt handler
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*/
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static void adc_ra_isr(const struct device *dev)
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{
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struct adc_ra_data *data = dev->data;
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fsp_err_t fsp_err = FSP_SUCCESS;
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adc_channel_t channel_id = 0;
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uint32_t channels = 0;
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int16_t *sample_buffer = (int16_t *)data->buf;
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channels = data->channels;
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for (channel_id = 0; channels > 0; channel_id++) {
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/* Check if it is right channel id */
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if ((channels & 0x01) != 0) {
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fsp_err = R_ADC_Read(&data->adc, channel_id, &sample_buffer[data->buf_id]);
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if (FSP_SUCCESS != fsp_err) {
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break;
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}
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data->buf_id = data->buf_id + 1;
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}
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channels = channels >> 1;
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}
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adc_scan_end_isr();
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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/**
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* @brief Check if buffer in @p sequence is big enough to hold all ADC samples
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*
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* @param dev RA ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOMEM if buffer is not big enough
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*/
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static int adc_ra_check_buffer_size(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct adc_ra_config *config = dev->config;
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uint8_t channels = 0;
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size_t needed;
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uint32_t mask;
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for (mask = BIT(config->num_channels - 1); mask != 0; mask >>= 1) {
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if (mask & sequence->channels) {
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channels++;
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}
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}
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needed = channels * sizeof(uint16_t);
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if (sequence->options) {
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needed *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed) {
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return -ENOMEM;
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}
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return 0;
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}
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/**
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* @brief Start processing read request
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*
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* @param dev RA ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_ra_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_ra_start_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct adc_ra_config *config = dev->config;
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struct adc_ra_data *data = dev->data;
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int err;
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if (sequence->resolution > ADC_RA_MAX_RESOLUTION || sequence->resolution == 0) {
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LOG_ERR("unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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if (find_msb_set(sequence->channels) > config->num_channels) {
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LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
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return -ENOTSUP;
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}
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err = adc_ra_check_buffer_size(dev, sequence);
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if (err) {
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LOG_ERR("buffer size too small");
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return err;
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}
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data->buf_id = 0;
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data->buf = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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adc_context_wait_for_completion(&data->ctx);
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return 0;
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}
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/**
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* @brief Start processing read request asynchronously
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*
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* @param dev RA ADC device
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* @param sequence ADC sequence description
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* @param async async pointer to asynchronous signal
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_ra_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_ra_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_ra_data *data = dev->data;
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int err;
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adc_context_lock(&data->ctx, async ? true : false, async);
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err = adc_ra_start_read(dev, sequence);
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adc_context_release(&data->ctx, err);
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return err;
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}
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/**
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* @brief Start processing read request synchronously
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*
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* @param dev RA ADC device
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* @param sequence ADC sequence description
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*
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* @return 0 on success
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* @return -ENOTSUP if requested resolution or channel is out side of supported
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* range
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* @return -ENOMEM if buffer is not big enough
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* (see @ref adc_ra_check_buffer_size)
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* @return other error code returned by adc_context_wait_for_completion
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*/
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static int adc_ra_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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return adc_ra_read_async(dev, sequence, NULL);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_ra_data *data = CONTAINER_OF(ctx, struct adc_ra_data, ctx);
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data->channels = ctx->sequence.channels;
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R_ADC_ScanStart(&data->adc);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct adc_ra_data *data = CONTAINER_OF(ctx, struct adc_ra_data, ctx);
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if (repeat_sampling) {
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data->buf_id = 0;
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}
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}
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/**
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* @brief Function called on init for each RA ADC device. It setups all
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* channels to return constant 0 mV and create acquisition thread.
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*
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* @param dev RA ADC device
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*
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* @return -EIO if error
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*
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* @return 0 on success
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*/
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static int adc_ra_init(const struct device *dev)
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{
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const struct adc_ra_config *config = dev->config;
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struct adc_ra_data *data = dev->data;
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int ret;
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fsp_err_t fsp_err = FSP_SUCCESS;
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* Open ADC module */
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fsp_err = R_ADC_Open(&data->adc, &data->f_config);
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if (FSP_SUCCESS != fsp_err) {
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return -EIO;
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}
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config->irq_configure();
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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const adc_extended_cfg_t g_adc_cfg_extend = {
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.add_average_count = ADC_ADD_OFF,
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.clearing = ADC_CLEAR_AFTER_READ_ON,
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.trigger_group_b = ADC_START_SOURCE_DISABLED,
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.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
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.adc_vref_control = ADC_VREF_CONTROL_VREFH,
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.enable_adbuf = 0,
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.window_a_irq = FSP_INVALID_VECTOR,
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.window_a_ipl = (1),
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.window_b_irq = FSP_INVALID_VECTOR,
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.window_b_ipl = (BSP_IRQ_DISABLED),
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.trigger = ADC_START_SOURCE_DISABLED, /* Use Software trigger */
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};
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#define IRQ_CONFIGURE_FUNC(idx) \
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static void adc_ra_configure_func_##idx(void) \
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{ \
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R_ICU->IELSR[DT_INST_IRQ_BY_NAME(idx, scanend, irq)] = \
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ELC_EVENT_ADC##idx##_SCAN_END; \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
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DT_INST_IRQ_BY_NAME(idx, scanend, priority), adc_ra_isr, \
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DEVICE_DT_INST_GET(idx), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(idx, scanend, irq)); \
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}
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#define IRQ_CONFIGURE_DEFINE(idx) .irq_configure = adc_ra_configure_func_##idx
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#define ADC_RA_INIT(idx) \
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IRQ_CONFIGURE_FUNC(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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static struct adc_driver_api adc_ra_api_##idx = { \
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.channel_setup = adc_ra_channel_setup, \
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.read = adc_ra_read, \
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.ref_internal = DT_INST_PROP(idx, vref_mv), \
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IF_ENABLED(CONFIG_ADC_ASYNC, (.read_async = adc_ra_read_async))}; \
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static const struct adc_ra_config adc_ra_config_##idx = { \
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.num_channels = DT_INST_PROP(idx, channels_num), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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IRQ_CONFIGURE_DEFINE(idx), \
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}; \
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static struct adc_ra_data adc_ra_data_##idx = { \
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ADC_CONTEXT_INIT_TIMER(adc_ra_data_##idx, ctx), \
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ADC_CONTEXT_INIT_LOCK(adc_ra_data_##idx, ctx), \
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ADC_CONTEXT_INIT_SYNC(adc_ra_data_##idx, ctx), \
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.dev = DEVICE_DT_INST_GET(idx), \
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.f_config = \
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{ \
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.unit = idx, \
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.mode = ADC_MODE_SINGLE_SCAN, \
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.resolution = ADC_RESOLUTION_12_BIT, \
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.alignment = (adc_alignment_t)ADC_ALIGNMENT_RIGHT, \
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.trigger = 0, \
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.p_callback = NULL, \
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.p_context = NULL, \
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.p_extend = &g_adc_cfg_extend, \
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.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq), \
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.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority), \
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.scan_end_b_irq = FSP_INVALID_VECTOR, \
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.scan_end_b_ipl = (BSP_IRQ_DISABLED), \
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}, \
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.f_channel_cfg = \
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{ \
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.scan_mask = 0, \
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.scan_mask_group_b = 0, \
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.priority_group_a = ADC_GROUP_A_PRIORITY_OFF, \
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.add_mask = 0, \
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.sample_hold_mask = 0, \
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.sample_hold_states = 24, \
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.p_window_cfg = NULL, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, adc_ra_init, NULL, &adc_ra_data_##idx, &adc_ra_config_##idx, \
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POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, &adc_ra_api_##idx)
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DT_INST_FOREACH_STATUS_OKAY(ADC_RA_INIT);
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@ -277,6 +277,28 @@
|
|||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
adc0: adc@40332000 {
|
||||
compatible = "renesas,ra-adc";
|
||||
interrupts = <38 1>;
|
||||
interrupt-names = "scanend";
|
||||
reg = <0x40332000 0x100>;
|
||||
#io-channel-cells = <1>;
|
||||
vref-mv = <3300>;
|
||||
channels-num = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc1: adc@40332200 {
|
||||
compatible = "renesas,ra-adc";
|
||||
interrupts = <39 1>;
|
||||
interrupt-names = "scanend";
|
||||
reg = <0x40332200 0x100>;
|
||||
#io-channel-cells = <1>;
|
||||
vref-mv = <3300>;
|
||||
channels-num = <13>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
option_setting_ofs: option_setting_ofs@300a100 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x0300a100 0x18>;
|
||||
|
|
28
dts/bindings/adc/renesas,ra-adc.yaml
Normal file
28
dts/bindings/adc/renesas,ra-adc.yaml
Normal file
|
@ -0,0 +1,28 @@
|
|||
# Copyright (c) 2024 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas RA ADC node
|
||||
|
||||
compatible: "renesas,ra-adc"
|
||||
|
||||
include: [adc-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
vref-mv:
|
||||
type: int
|
||||
required: true
|
||||
description: ADC reference voltage (Unit:mV)
|
||||
|
||||
channels-num:
|
||||
type: int
|
||||
required: true
|
||||
description: ADC channels number
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
|
@ -103,3 +103,6 @@ child-binding:
|
|||
description: |
|
||||
The drive strength of a pin. The default value is low, as this
|
||||
is the power on reset value.
|
||||
renesas,analog-enable:
|
||||
type: boolean
|
||||
description: enable analog input
|
||||
|
|
|
@ -42,6 +42,7 @@
|
|||
#define RA_PSEL_ETH_RMII 0x17
|
||||
#define RA_PSEL_GLCDC 0x19
|
||||
#define RA_PSEL_OSPI 0x1c
|
||||
#define RA_PSEL_ADC 0x00
|
||||
|
||||
#define RA_PSEL_POS 8
|
||||
#define RA_PSEL_MASK 0x1f
|
||||
|
|
|
@ -27,3 +27,8 @@ config USE_RA_FSP_SCI_UART
|
|||
bool
|
||||
help
|
||||
Enable RA FSP SCI UART driver
|
||||
|
||||
config USE_RA_FSP_ADC
|
||||
bool
|
||||
help
|
||||
Enable RA FSP ADC driver
|
||||
|
|
|
@ -39,6 +39,7 @@ typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t;
|
|||
.pin_num = RA_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
|
||||
.cfg = (DT_PROP(node_id, bias_pull_up) << 4) | \
|
||||
(DT_PROP(node_id, drive_open_drain) << 6) | \
|
||||
(DT_PROP(node_id, renesas_analog_enable) << 15) | \
|
||||
(DT_ENUM_IDX(node_id, drive_strength) << 10) | \
|
||||
(RA_GET_MODE(DT_PROP_BY_IDX(node_id, prop, idx)) << 16) | \
|
||||
(RA_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)) << 24), \
|
||||
|
|
27
tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
Normal file
27
tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
Normal file
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/ {
|
||||
zephyr,user {
|
||||
io-channels = <&adc0 0>;
|
||||
reference_mv = <3300>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc0{
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
zephyr,gain = "ADC_GAIN_1";
|
||||
zephyr,reference = "ADC_REF_INTERNAL";
|
||||
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
|
||||
zephyr,resolution = <12>;
|
||||
zephyr,vref-mv = <3300>;
|
||||
};
|
||||
};
|
|
@ -12,8 +12,10 @@ tests:
|
|||
fixture: dac_adc_loopback
|
||||
platform_allow:
|
||||
- frdm_k64f
|
||||
- ek_ra8m1
|
||||
drivers.adc.accuracy.ref_volt:
|
||||
harness_config:
|
||||
fixture: adc_ref_volt
|
||||
platform_allow:
|
||||
- frdm_kl25z
|
||||
- ek_ra8m1
|
||||
|
|
48
tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay
Normal file
48
tests/drivers/adc/adc_api/boards/ek_ra8m1.overlay
Normal file
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
/ {
|
||||
zephyr,user {
|
||||
io-channels = <&adc1 0>, <&adc1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
adc1_default: adc1_default {
|
||||
group1 {
|
||||
/* input */
|
||||
psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
|
||||
renesas,analog-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
pinctrl-0 = <&adc1_default>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
zephyr,gain = "ADC_GAIN_1";
|
||||
zephyr,reference = "ADC_REF_INTERNAL";
|
||||
zephyr,resolution = <12>;
|
||||
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
|
||||
zephyr,vref-mv = <3300>;
|
||||
};
|
||||
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
zephyr,gain = "ADC_GAIN_1";
|
||||
zephyr,reference = "ADC_REF_INTERNAL";
|
||||
zephyr,resolution = <12>;
|
||||
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
|
||||
zephyr,vref-mv = <3300>;
|
||||
};
|
||||
};
|
Loading…
Add table
Add a link
Reference in a new issue