Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
Update the hal_nordic module revision, to switch to nrfx 2.1.0.
Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This checks if the DMA controller supports or not
the memory-to-memory transfers. For DMA Version1,
in the stm32f2xx, stm32f4xx, stm32f7xx series,
only DMA instance 2 is able to transfer mem-to-mem.
For other series, with DMA Version2, there is no such a limitation.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds initial support for the Silicon Labs EFM32
Giant Gecko GG11 StarterKit.
Features supported for now are NVIC, SysTick, GPIO, Flash,
Counter, I2C, UART and Ethernet. Support for Watchdog and
ADC will follow as soon as their respective PRs are merged.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Currently, only the stm32h747 soc is supported in the h7 foler.
The h7 series comes with both single core and dual core products.
This change moves C-M4 core out of stm32h7.dtsi so that it can be
included by single core STM32H7 soc description.
Signed-off-by: Moonkwun Jung <mkainyh@gmail.com>
Fix the RTC device tree node for the NXP K6x SoC series. This device
is compatible with nxp,kinetis-rtc.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
STM32L073 soc variant is a STM32L072 with LCD peripheral.
Reflect this in dts definition by including stm32l072.dtsi
in stm32l073.dtsi.
This also allows to fix an issue on stm32l073 gpioe which
declared wrong reg definition.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The I2C controllers on the MEC1501 SoC can be attached to
different I2C output line. For example, the I2C #0 controller
can be used with I2C7 physical lines out of SoC. The output
selection is done by the attribute "port_sel". This renames
the parent I2C nodes on the SoC side to refer to
the controller themselves instead of the output lines to
avoid confusion. The labels of these nodes are also renamed
to reflect the controllers.
On the board level, the DTS labels are overwritten to indicate
the actual output lines.
Aliases are also provided in both SoC and board levels to
provide shortcuts to the DTS nodes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such. If anyone
is interesting in supporting this platform we can easily recovery it
from git.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis K6x SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis KE1xF SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.
Signed-off-by: Roland Ma <rolandma@yahoo.com>
The amount of lock regions differs between different sam0 MCUs.
saml10: 2
saml11: 4
samd2x: 16
saml2x: 16
samd5x: 32
ASF does not provide a definition for this, so create a new one
in dts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all lpc socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx 6/7 socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx rt socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all kinetis socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add device_type DTS property in sram0 and sram1 nodes,
for nRF5340 Application and Network CPU, respectively.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit fixes the following problems with the RPU device tree:
1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
Cortex-R4.
2. RPU and APU use different interrupt controllers (PL390 GICv1 and
GIC-400 GICv2, respectively) mapped to the same CPU local bus address
region but with different offsets for the distributor and CPU
interrupt control register sets. The GIC address mapping specified by
the current dts is that of an APU and does not apply to the PL390
GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
Reference" document from Xilinx for more information).
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.
Changes:
- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.
Test: Tested USART3 as console at 115200 baud
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Adds spi device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new spi driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
