Commit graph

988 commits

Author SHA1 Message Date
Kamil Lazowski
5b4f4253c1 drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.

Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2020-01-29 15:15:49 +01:00
Andrzej Głąbek
7899b1f5b6 modules: hal_nordic: Update nrfx to version 2.1.0
Update the hal_nordic module revision, to switch to nrfx 2.1.0.

Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-01-29 15:00:45 +01:00
Henrik Brix Andersen
5a82424767 dts: arm: stm32f3: add can controller
Add the CAN controller device tree node for CAN_1 of the STM32F3 SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-29 09:47:27 +01:00
Henrik Brix Andersen
6487ecc784 dts: arm: nxp: ke1xf: fix LPO clock frequency
The frequency of the Low Power Oscillator (LPO) is 128kHz, not 125kHz.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-28 14:47:35 -06:00
Francois Ramu
82799d2ae4 dts: bindings: dma controller supports mem2mem transfer
This checks if the DMA controller supports or not
the memory-to-memory transfers. For DMA Version1,
in the stm32f2xx, stm32f4xx, stm32f7xx series,
only DMA instance 2 is able to transfer mem-to-mem.
For other series, with DMA Version2, there is no such a limitation.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-01-28 12:58:44 -06:00
Jose Alberto Meza
da87abd971 dts: arm: microchip: Adjust DT IRQ priorities
Adjust default IRQ priorities.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-01-28 20:13:36 +02:00
Jonas Eriksson
3e64e751b6 soc: stm32f1: Add support for stm32f1xx SoCs
Define stm32f100xx family, tested using stm32vl_disco
(stm32f100rb).

Signed-off-by: Jonas Eriksson <jonas@upto.se>
2020-01-28 08:30:52 -06:00
Oane Kingma
c52787c4d1 boards/arm: Add initial support for SiLabs Giant Gecko GG11 STK
This commit adds initial support for the Silicon Labs EFM32
Giant Gecko GG11 StarterKit.

Features supported for now are NVIC, SysTick, GPIO, Flash,
Counter, I2C, UART and Ethernet. Support for Watchdog and
ADC will follow as soon as their respective PRs are merged.

Signed-off-by: Oane Kingma <o.kingma@interay.com>
2020-01-24 10:28:33 -06:00
Benjamin Valentin
2fef2002e8 soc: atmel_sam0: add SAM TRNG to DTS
We can use the SAM entropy node here.

Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2020-01-23 12:40:59 +01:00
Moonkwun Jung
a67ca8f202 dts: arm: st: h7: fix stm32h7 separate cores
Currently, only the stm32h747 soc is supported in the h7 foler.
The h7 series comes with both single core and dual core products.
This change moves C-M4 core out of stm32h7.dtsi so that it can be
included by single core STM32H7 soc description.

Signed-off-by: Moonkwun Jung <mkainyh@gmail.com>
2020-01-23 09:54:39 +01:00
Henrik Brix Andersen
230b278f84 dts: arm: nxp: k6x: fix rtc dts node
Fix the RTC device tree node for the NXP K6x SoC series. This device
is compatible with nxp,kinetis-rtc.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-22 06:27:30 -06:00
Antony Pavlov
fc1cdf233d soc: arm: stm32l1: Add STM32L152Xe stuff
The STM32L151 and STM32L152 differ in that
the STM32L152 features an LCD controller.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2020-01-20 18:08:43 -06:00
Erwan Gouriou
87a440b8c6 dts: stm32: Define stm32l073 as stm32l072 superset
STM32L073 soc variant is a STM32L072 with LCD peripheral.
Reflect this in dts definition by including stm32l072.dtsi
in stm32l073.dtsi.
This also allows to fix an issue on stm32l073 gpioe which
declared wrong reg definition.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-01-20 12:17:31 -06:00
Daniel Leung
6ecb36cbe0 dts: arm: mec1501hsz: rename I2C nodes
The I2C controllers on the MEC1501 SoC can be attached to
different I2C output line. For example, the I2C #0 controller
can be used with I2C7 physical lines out of SoC. The output
selection is done by the attribute "port_sel". This renames
the parent I2C nodes on the SoC side to refer to
the controller themselves instead of the output lines to
avoid confusion. The labels of these nodes are also renamed
to reflect the controllers.

On the board level, the DTS labels are overwritten to indicate
the actual output lines.

Aliases are also provided in both SoC and board levels to
provide shortcuts to the DTS nodes.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-01-18 13:33:20 -05:00
Kumar Gala
b1602c8e39 arm: Removed support for CC2650
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such.  If anyone
is interesting in supporting this platform we can easily recovery it
from git.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-01-18 09:27:55 -06:00
Henrik Brix Andersen
05dca5df04 dts: nxp: k6x: add temperature sensor nodes
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis K6x SoC series.

A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-16 17:30:42 -06:00
Henrik Brix Andersen
ca9861f690 dts: nxp: ke1xf: add temperature sensor nodes
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis KE1xF SoC series.

A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-16 17:30:42 -06:00
Roland Ma
01049b73be dts: arm: st: Add dts and soc additions for stm32 F767ZI board
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.

Signed-off-by: Roland Ma <rolandma@yahoo.com>
2020-01-16 22:51:13 +01:00
Andrei Gansari
5ac450ecc4 dts: lpc55s6x flash controller add
Added flash controller and all memory mapped regions to DTS.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-01-16 08:19:46 -06:00
Andrei Gansari
fb9a41dc0b dts: lpc55s69 all flash regions
Added reserved partition and bootrom partitions.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-01-16 08:19:46 -06:00
Andrei Gansari
85800622f9 dts: remove artificial include
DTS inclusion simplification for LPC55S69 cpu 0.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-01-16 08:19:46 -06:00
Kwon Tae-young
cea68ea492 dts: arm: stm32: add dts support for EEPROM of STM32L0
Add eeprom to STM32L0 series.
stm32l053X8: 2k
stm32l072Xz, stm32l073Xz: 6k

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2020-01-14 11:13:42 -05:00
Benjamin Valentin
fc7f458ab3 flash: sam0: Define LOCK_REGIONS in dts
The amount of lock regions differs between different sam0 MCUs.

	saml10:  2
	saml11:  4
	samd2x:	16
	saml2x: 16
	samd5x: 32

ASF does not provide a definition for this, so create a new one
in dts.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-01-14 11:12:33 -05:00
Maureen Helm
b8ad9969ef drivers: counter: Refactor mcux gpt driver to use generated dts macros
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-14 11:10:27 -05:00
Maureen Helm
88fcded3b0 dts: boards: Define dts aliases at soc level for lpc socs
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all lpc socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-13 10:22:44 -05:00
Maureen Helm
ecd24bccd1 dts: boards: Define dts aliases at soc level for i.mx 6/7 socs
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx 6/7 socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-13 10:22:44 -05:00
Maureen Helm
201f8897cd dts: boards: Define dts aliases at soc level for i.mx rt socs
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx rt socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-13 10:22:09 -05:00
Maureen Helm
519661748e dts: boards: Define dts aliases at soc level for kinetis socs
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all kinetis socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-13 08:30:53 -06:00
Ioannis Glaropoulos
1e492b2b1d dts: arm: nrf5340: adding device_type property in sram nodes
Add device_type DTS property in sram0 and sram1 nodes,
for nRF5340 Application and Network CPU, respectively.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-01-13 12:48:46 +01:00
Ryan QIAN
7f75e4f83b soc: arm: nxp_imx: rt: add device support i.MX RT1010
- Add device support for i.MXRT1010

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2020-01-09 16:29:22 -06:00
Henrik Brix Andersen
85e1117e94 dts: nxp: kinetis-ftm: add PWM flags cell
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.

All in-tree clients of this PWM controller are active-low LEDs.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-07 18:13:18 +01:00
Stephanos Ioannidis
38f0b05b99 dts: xilinx_zynqmp: Fix incorrect RPU device tree specification.
This commit fixes the following problems with the RPU device tree:

1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
  Cortex-R4.

2. RPU and APU use different interrupt controllers (PL390 GICv1 and
  GIC-400 GICv2, respectively) mapped to the same CPU local bus address
  region but with different offsets for the distributor and CPU
  interrupt control register sets. The GIC address mapping specified by
  the current dts is that of an APU and does not apply to the PL390
  GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
  Reference" document from Xilinx for more information).

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Stephanos Ioannidis
8a29685a25 dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately.
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.

This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).

When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Henrik Brix Andersen
ebb4126cbe soc: nxp: ke1xf: rename ftm instances to pwm to match other SoCs
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-01-06 10:03:20 -06:00
Sahaj Sarup
4dca5285f0 arm: board: 96b_stm32_sensor_mez: enable USART3
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.

Changes:

- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.

Test: Tested USART3 as console at 115200 baud

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2020-01-03 09:37:08 -06:00
Jack Rosenthal
53ed9e57a2 soc: stm32f0: Add support for STM32F098xx SOC
This adds a Kconfig options and device tree configs for the STM32F098
series of SoC.

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
2019-12-20 20:27:20 -05:00
Filip Brozovic
e541e63653 soc: arm: stm32g0: add STM32G031 SoC series
This commit adds support for the STM32G031xx SoCs
by STMicroelectronics.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-12-18 22:06:39 +01:00
Filip Brozovic
fc2dfae64f drivers: i2c: add STM32G0X I2C support
Add I2C driver support for STM32G0X SoC series.

Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2019-12-18 22:06:27 +01:00
Sahaj Sarup
d072ab83ac arm: 96b_stm32_sensor_mez: spi: Enable SPI4
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.

Changes:

- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test

Test: spi_loopback test passed

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2019-12-18 07:34:37 -06:00
Martin Jaeger
3d1834e5d6 dts: arm: stm32l452 dtsi files updated
Fixed warning for uppercase hex addresses and added stm32l452Xe.dtsi

Signed-off-by: Martin Jaeger <17674105+martinjaeger@users.noreply.github.com>
2019-12-13 17:02:40 -06:00
Kwon Tae-young
a6f5c1bbf6 dts: arm: stm32: add dts support for EEPROM of STM32L1
Add eeprom to STM32L1 series.
Currently supported L1 series EEPROM size is 4Kbyte.

Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
2019-12-12 07:57:33 -06:00
Feng Cheng
ee57c8e749 drivers: flash: Add the flash driver of the stm32f1x family
Most of the code is copied from the stm32f0x family
Tested on stm32f103ze soc

Signed-off-by: Feng Cheng <i@fengch.me>
2019-12-11 12:40:33 -06:00
Maureen Helm
30415e9246 dts: Add spi bindings and nodes for lpc socs
Adds spi device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new spi driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-12-10 08:48:56 -06:00
Carlo Caione
7baf3f74a9 interrupt_controller: gic: Support PPIs
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.

This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.

SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].

This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.

The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-12-10 06:59:55 +01:00
Emil Obalski
95c41b11a7 soc: arm: nordic: adding ipc aliases for nRF53
This commit adds ipc-0 aliases in the DTS framework
for nRF5340 Application and Network MCU.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-20 19:29:06 +01:00
Christian Taedcke
6486c429f1 dts: silabs: Define all available gpio ports for efr32mg12p
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
a0f011b2fb dts: lpc devices allocate all gpio interrupts
Allocate all 8 PINT interrupts to ports 0 and 1, allocate 4 to each.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Andrei Gansari
2e27363e67 dts: NXP LPC gpio updates
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-11-13 12:05:48 -06:00
Stanislav Poboril
aef4541475 dts: nxp_imx6sx_m4: fix gpio5 int num
Fix interrupt number for gpio5

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2019-11-13 12:05:48 -06:00
Emil Obalski
3747fd0a68 soc: nordic: Add support for nRF52833
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
 - architecuture files (dtsi)
 - configuration of nrfx drivers
 - adaptation of inclusions based on chosen SoC
 - configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.

Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
2019-11-13 10:33:38 -06:00