dts: bindings: dma controller supports mem2mem transfer
This checks if the DMA controller supports or not the memory-to-memory transfers. For DMA Version1, in the stm32f2xx, stm32f4xx, stm32f7xx series, only DMA instance 2 is able to transfer mem-to-mem. For other series, with DMA Version2, there is no such a limitation. Signed-off-by: Francois Ramu <francois.ramu@st.com>
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7 changed files with 3 additions and 7 deletions
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@ -257,12 +257,14 @@ static int dma_stm32_configure(struct device *dev, u32_t id,
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return -EINVAL;
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}
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#ifdef CONFIG_DMA_STM32_V1
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if ((stream->direction == MEMORY_TO_MEMORY) &&
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(!dev_config->support_m2m)) {
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LOG_ERR("Memcopy not supported for device %s",
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dev->config->name);
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return -ENOTSUP;
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}
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#endif /* CONFIG_DMA_STM32_V1 */
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if (config->source_data_size != 4U &&
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config->source_data_size != 2U &&
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@ -317,7 +317,6 @@
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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interrupts = <9 0 10 0 10 0 11 0 11 0>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_1";
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};
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@ -265,7 +265,6 @@
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_1";
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};
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@ -322,7 +322,6 @@
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_1";
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};
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@ -186,7 +186,6 @@
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reg = <0x40020000 0x400>;
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interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_1";
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};
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@ -316,7 +316,6 @@
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reg = <0x40020000 0x400>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_1";
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};
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@ -327,7 +326,6 @@
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reg = <0x40020400 0x400>;
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interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
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st,mem2mem;
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status = "disabled";
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label = "DMA_2";
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};
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@ -16,7 +16,7 @@ properties:
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st,mem2mem:
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type: boolean
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description: If the controller supports memory to memory transfer
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description: If the DMA controller V1 supports memory to memory transfer
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"#dma-cells":
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const: 4
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