MCUBOOT requires LTO to be enabled, while using code relocation
forces switching it off. When `__ramfunc` is used, LTO can also
be used. Then the `cache_retain_and_sleep` function will work
correctly, but slightly slower.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Retrieve the value of SYS_CLOCK_HW_CYCLES_PER_SEC from the osc node in
the RZ/A3UL devicetree.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Set SL_SI91X_BT_BLE_STACK_BYPASS_ENABLE in ble_ext_feature_bit_map to
support host-driven BT/BLE stack operation on SiWx91x devices.
When enabled:
- Events are delivered directly to the host, bypassing internal stack
processing
- Ensures critical events like CARD_READY reach the host reliably
- Allows external host stack to control BT/BLE operations
- Provides more memory to the application, as the internal stack is
bypassed
This change enables direct event packet delivery from the firmware event
handler, ensuring proper operation when the internal BT stack is
bypassed.
Required for BT/BLE tester and host-controlled stack configurations.
Signed-off-by: Arun Kumar Nagelly <arnagell@silabs.com>
Add configuration for BLE
Add 32KHz Osc clock needed by BLE
Move nxp_nbu.c include to be shared on mcxw7x and mcxw2x
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Both MCXW2xx and MCXW7xx now share the same SoC family
(CONFIG_SOC_FAMILY_MCXW).
Isolate mcxw7xx-specific module/code from mcxw2xx.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This is a SOC based on AE350. In addition to the core, some
modifications have been made to the peripheral functions,
including the integration of built-in USB.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
Added driver and bindings for the coresight nrf submodule.
add integrated it for the nrf54h20.
The coresight subsystem is a combination of ARM Coresight peripherals
that get configured together to achieve a simplified configuration based
on a desired operating mode.
This also replaces the previous handling in the nrf54h20 soc.c which was
powering the subsystem up but not configuring it.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Moved the nrf_etr driver from the drive/misc folder into the recently
established driver/debug folder where it is a better fit. Moved the
associated files such as bindings and headers accordingly as well.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
This commit introduces a new function to verify the firmware version of
the SiWX917 network coprocessor. It checks the expected version (updated
manually after each bump of Wiseconnect SDK in hal_silabs) against the
actual version retrieved from the device.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Retrieve the value of SYS_CLOCK_HW_CYCLES_PER_SEC from the osc node in
the RZ/N2L, T2M devicetree.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add a first region in the MPU to disable all access to the whole
memory range. With that ensure that the MPU will block all
access to regions that aren't defined in further regions.
Ensure as well that the peripheral area is accessible.
This handles the errata 2.1.1 PLD might perform linefill to address
that would generate a MemManage Fault of the STM32H7Rxx / STM32H7Sxx
device errate ES0596 - Rev 6.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The update will fail if the address is outside of this range.
This failure might trigger a bad state where the device is
non-trivial to recover.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Move the option to force constant latency mode outside of nRF54l, since
it is an option applicable to most Nordic SoCs.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Adds snippets-text-sections.ld to ACE linker scripts.
For now, this is for the memory mapping test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There were some corner cases and stress test could fail. Reworking
tail bits handling to make the stress test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Fix an incorrect interpretation of the chip select signal
for the SPIM instances. If cs-gpios is used then the chip
select pin is used as a GPIO, and should have CTRLSEL=0.
Only when NRF_FUN_SPIM_CSN is used should CTRLSEL
be configured to enable hardware control of the pin.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Provide PM support, specifically suspend-to-ram, for STM32WB0x.
Enable STM32_RADIO_TIMER Kconfig parameter when PM is set.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Use radio timer as the system timer when Bluetooth is used.
Modify CMakeLists.txt to compile radio timer driver when
STM32WB0_RADIO_TIMER is enabled.
Remove the common parts from hci_stm32wb0.c that are present
in the radio timer driver.
Set and retrieve the appropriate value for SYS_CLOCK_TICKS_PER_SEC and
SYS_CLOCK_HW_CYCLES_PER_SEC respectively.
Define radio_timer node and its properties.
Enable radio_timer node in nucleo_wb0x boards.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add the #include <snippets-sections.ld> directive
to include a linker file automatically.
This file defines additional linker sections that
are dynamically added during the build process.
It is placed at the very end of the SECTIONS block,
ensuring that any sections it defines appear after
all standard sections.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Use CONFIG_STM32_FLASH_PREFETCH config option to enable flash prefetch
in C0/F0/F1/F2/F3/F4/F7/G4/L0/L1/L4/U0/U3/WB/WBA/WBL for consistency
with other SoCs that use this configuration switch, default enabled
at SoC default config level.
Add SoC hidden config option HAS_STM32_FLASH_PREFETCH enabled for
SoCs that support the feature. STM32_FLASH_PREFETCH is default
enabled for all SoC that have HAS_STM32_FLASH_PREFETCH unless target
specific constraints (as for G0Bx/G0Cx SoCs).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
An uninitialized variable was returned on success which could led by
init_nrfs.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The default log process thread stack size needs to be increased to
account for the recursion into resuming power domains, which
may happen within char_out for some backends like uart.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
siwx91x require a specific API to communicate with the bootloader in order
to achieve firmware upgrade. This commit introduces the configuration
symbol to import the helper library.
[Jérôme: split commits, reword the commit log]
Co-authored-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Signed-off-by: Rahul Gurram <rahul.gurram@silabs.com>
Add an early init hook to check the boot mode and reset into the RP2 USB
bootloader if requested. Includes a snippet to use with any RP2040/RP2350
board to enable the necessary DTS/Kconfig to use the functionality, and
easy DTS includes for boards to use explicitly.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Default disable flash prefetch on G0Bx/G0C1 to prevent issues
described by errata ES0548 2.2.10. Project can still enable
the config if applicable.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit adds support using pm_s2ram for 54H when the
MPU is disabled. This is the case for the out of tree
sample `sdk-nrf/samples/nrf54h/empty_app_core`.
Without this commit the linker will fail to link
`z_arm_mpu_init` and `z_arm_configure_static_mpu_regions`.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
This commit adds cache handling for Hifi4 core on RT700.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Add cpuclk driver for mt8188 platform. Note that the cpuclk driver is
not yet ported, it works only with mt8188.
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
On MT8188 platform timer interrupts must also be enabled/disabled in
MTK_ADSP_IRQ_EN register in addition to xtensa_irq_enable(),
xtensa_irq_disable()
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
Add 'ax' flags for .sof_entry ELF section so it merges properly with
.z_xtensa_vectors ELF section
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
Boot ROM will by default set on/off delays to 0ms before jumping to
firmware. This patch adds an option to to configure the on/off delays to
non-zero values. A flash power cycle guarantees to put the external
flash into a known state before executing code from it. This is required
if using 4-byte address mode in the external flash, as the boot ROM will
always use 3-byte address mode when reading from external flash, causing
a potential deadlock situation requiring a power-cycle (known errata).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
