With -Hccm, the linker automatically moves stuff in RODATA
section into DATA section. Our current kobject related
scripts cannot accommodate this, resulting in space not
being reserved correctly. So for now, disable -Hccm
compiler option if userspace is enabled.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- The RX Message Descriptor in CANXL on newer SoC such as
the S32K5 supports receiving both classic and FD frames,
so enable the RX FIFO only for S32ZE SoC.
- The CANXL bare-metal driver has significant changes, the
current codebase for S32ZE need to be guarded and modified
to support newer SoC
- Expand the peripheral region to 1G to include the CANXL
area.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
cy8ckit_062_wifi_bt board requires NMI handler to point to
the prefefined address 0x0000000D in order to correctly run
system calls. This can be achieved by specifying the runtime
nmi configuration and hardcoding the address in soc.c.
With the introduction of this change the system calls can
correctly be executed correctly thus resolving open
issue #99642 .
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Move the multicore middleware to the new mcux-sdk-ng integration from
hal_nxp, instead of using the legacy integration method.
This will allow for easier integration of future releases.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add invisible RENESAS_PN config to reflect the SoC hardware
information and provide input for hal_renesas
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Replaced the previous struct layout with a union
type. This change exposes all register fields that were hidden
for pinctrl, but now they are useful for gpio to reuse.
- Remove `_t` suffix from struct tag to avoid duplication with
typedef alias.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Implement power management with IDLE, STOP, PSTOP1, and PSTOP2 modes.
- Add power state definitions with timing parameters
- Implement pm_state_set() with proper SLEEPDEEP handling
- Add XIP-safe WFI execution from RAM
- Enable SMC driver and power mode protection
- Remove forced timer Kconfig defaults
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This is to start the process of fixing the issue of the SoC series
not matching the value in the soc.yml file, which is needed to
support future build system features for automatically creating
SoC Kconfigs by the build system.
This also fixes some oddities with how the Kconfigs were set out,
which included duplicated Kconfigs and duplicate selections and
having them in the wrong (or differing) files, to actually follow
how HWMv2 should define these Kconfigs.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the boards in zephyr meaning it should not cause
any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the boards in zephyr meaning it should not cause
any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the boards in zephyr meaning it should not cause
any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the 2 boards in zephyr meaning it should not
cause any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds cache handling for Hifi4 core on RT600.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
This is required for proper data coherency when the DSP shares memory
with other cores (e.g., Cortex-M33) or DMA peripherals.
With this change, applications can now use sys_cache_data_flush_range()
and sys_cache_data_invd_range() to ensure cache coherency in shared
memory scenarios.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Fixes using a dt function which suffered from firstly trying to
take the value from a variable that isn't defined, and which if is
ignored, was entirely invalid due to supplying a chosen node, not
a path as the dt function explicitly requires
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes Kconfig naming to be properly set as required by HWMv2, to
allow for future build system features to work
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes a wrongly added SoC feature which should not have been
accepted in the original way it was added, by correctly adding a
Kconfig to select an optional build configuration for this SoC
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The Versal RPU uses Arm Cortex-R5F cores, which implement VFPv3-D16
(single and double precision with 16 double-word registers):.
Select VFP_DP_D16 to describe the available VFP configuration for this SoC.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Adding support for running Zephyr OS as a guest virtual machine
in the QNX Hypervisor environment.
This change introduces a new board configuration for ARM64-based
QNX Hypervisor VM.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
STM32H5, STM32L5, STM32U5, and STM32WBAX series MCUs have external
ICACHE/DCACHE with a cache line size of 16 bytes. The previous
configuration incorrectly set the cache line size to 32 bytes (the
default cache line size for Cortex-M cores).
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Introduce the NRF_DT_IRQ_DIRECT_DEFINE and NRF_DT_IRQ_CONNECT macros
which reduce provide a common way for nordic drivers to adapt to the
presence of the SW ISR table which is commonly excluded as it is not
required for nordic socs. Also adds device driver inst variants of
the macros.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
1. This commit converts the 'XIP_BOOT_HEADER_DCD_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_DCD_ENABLE' flag is only used in
hal_nxp/rtxxxx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rtxxxx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. This commit converts the 'XIP_BOOT_HEADER_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_ENABLE' flag is only used in
hal_nxp/rt11xx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rt11xx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
For RT10xx and RT11xx, flag 'BOARD_FLASH_SIZE' is only used
in hal_nxp fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the SoC layer CMake
using zephyr_library_compile_definitions() to limit its scope.
Normally, 'BOARD_FLASH_SIZE' should not be used elsewhere.
If an out-of-tree user uses this flag elsewhere, please define
the flag yourself.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Create a dedicated Zephyr library for the imxrt11xx and
imxrt10xx SoC in CMakeLists.txt and move soc.c into it
(zephyr_library() + zephyr_library_sources(soc.c)).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
We modified the Microchip MEC UART driver to be HAL
independent and be usuable on all MEC SoCs. The only
hardware difference is an extra register in the MEC174x/5x
family providing TX FIFO full and current byte count.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The TI AM62L is a low-power ARM Cortex-A53 based SoC with display for
IOT, HMI and general purpose applications. More information here:
https://www.ti.com/product/AM62L
Add initial SoC and DTS support here.
Signed-off-by: Andrew Davis <afd@ti.com>
Add DT properties to select CK48M source for GD32 RCU.
Apply CK48M source selection during early SoC init.
Signed-off-by: Aleksandr Senin <al@meshium.net>
The ARC IoT SoC (used on iotdk board) has a hardware limitation where
entering CPU sleep mode causes some peripherals (e.g., UART) to lose
power, preventing the board from waking up via peripheral interrupts.
Add a configurable custom CPU idle option (CONFIG_ARC_IOT_CUSTOM_CPU_IDLE)
that enables interrupts without executing the sleep instruction. This
allows the system to remain responsive while keeping peripherals powered.
The option defaults to disabled (n) to preserve normal CPU sleep behavior
for most use cases. Tests that require continuous UART operation during
idle (pytest/shell harnesses) can enable it via platform-specific
extra_configs.
This approach allows timer-based idle to work correctly by default while
providing a workaround for tests that need UART retention.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
Add linker script support for CONFIG_USERSPACE:
- MPU alignment macros for PMP granularity
- User stacks section in noinit area
- Application shared memory partitions
- Kernel object sections (text, rom, data, priv-stacks)
- ROM region size symbol for PMP configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Replace some manually-defined DT_COMPAT_<> Kconfig macro variables with
their automatically generated counterparts. In most cases, this is
straightforward as the manually defined macro is named identically to the
one generated by the build system.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
xt-clang seems to generate some memory access patterns which
result in the simulator accessing incorrect memory and/or
messing with cached TLB entries when spinlock validation
is enabled. Not exactly sure what's going on here due to
the core of the simulator is built on top of pre-built
binaries provided by the toolchain without any sources so
debugging would be nearly impossible. But at least we have
an easy workaround by disabling spin lock validation.
Fixes#100885
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Set default values for BLE HCI buffer configuration that match
the ESP32 controller requirements:
- BT_BUF_ACL_RX_COUNT=24: Match controller's ACL buffer count
- BT_BUF_EVT_RX_COUNT=30: Match controller's event buffer count
Enable BT HCI node in device tree for all ESP32 SoCs that
support BLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The data is updated by both local domains (cpuapp/cpuapp) and
IronSide SE (cpusec), so disable caching to avoid coherency issues.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
