soc: st: stm32: Provide basic support for STM32MP13 series

Enable basic support to STM32MP13, in single core configuration (A7)
with I and D cache enabled.

Signed-off-by: Julien Racki <julien.racki@st.com>

soc/st/stm32/common/soc_config.c

@@ -76,6 +76,8 @@ static int st_stm32_common_config(void)
 	LL_DBGMCU_EnableDebugInStopMode();
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
 	LL_PWR_EnableDEEPSTOP2();
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	LL_DBGMCU_EnableDebugInLowPowerMode();
 #else /* all other parts */
 	LL_DBGMCU_EnableDBGStopMode();
 #endif
@@ -90,6 +92,8 @@ static int st_stm32_common_config(void)
 	LL_DBGMCU_DisableDebugInStopMode();
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
 	LL_PWR_DisableDEEPSTOP2();
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	LL_DBGMCU_DisableDebugInLowPowerMode();
 #else /* all other parts */
 	LL_DBGMCU_DisableDBGStopMode();
 #endif

soc/st/stm32/soc.yml

@@ -187,6 +187,9 @@ family:
   - name: stm32mp1x
     socs:
     - name: stm32mp157cxx
+  - name: stm32mp13x
+    socs:
+    - name: stm32mp135fxx
   - name: stm32n6x
     socs:
     - name: stm32n657xx

soc/st/stm32/stm32mp13x/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32mp13x/Kconfig

@@ -0,0 +1,14 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32MP13X
+	select ARM
+	select CPU_CORTEX_A7
+	select HAS_STM32CUBE
+	select CPU_HAS_FPU
+	select SOC_EARLY_INIT_HOOK
+	select ARM_ARCH_TIMER
+	select SYS_CLOCK_EXISTS
+	select XIP

soc/st/stm32/stm32mp13x/Kconfig.defconfig

@@ -0,0 +1,20 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STM32MP13X
+
+rsource "Kconfig.defconfig.stm32mp13_a7"
+
+config CACHE_MANAGEMENT
+	default y
+
+DT_STM32_CPU_CLOCK_PATH := $(dt_nodelabel_path,cpusw)
+DT_STM32_CPU_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_CPU_CLOCK_PATH),clock-frequency)
+
+# For STM32MP13, override the default value defined in STM32 Kconfig
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(DT_STM32_CPU_CLOCK_FREQ) if $(dt_nodelabel_enabled,cpusw)
+
+endif # SOC_SERIES_STM32MP13X

soc/st/stm32/stm32mp13x/Kconfig.defconfig.stm32mp13_a7

@@ -0,0 +1,11 @@
+# STMicroelectronics STM32MP13_A7 MPU
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32MP135FXX
+
+config NUM_IRQS
+	default 181
+
+endif # SOC_STM32MP135FXX

soc/st/stm32/stm32mp13x/Kconfig.soc

@@ -0,0 +1,18 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32MP13X
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32mp13x" if SOC_SERIES_STM32MP13X
+
+config SOC_STM32MP135FXX
+	bool
+	select SOC_SERIES_STM32MP13X
+
+config SOC
+	default "stm32mp135fxx" if SOC_STM32MP135FXX

soc/st/stm32/stm32mp13x/soc.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32MP13 processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
+
+#include <stm32_ll_bus.h>
+#include <cmsis_core.h>
+
+#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
+
+void relocate_vector_table(void)
+{
+	write_sctlr(read_sctlr() & ~HIVECS);
+	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
+	barrier_isync_fence_full();
+}
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+
+void soc_early_init_hook(void)
+{
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	SystemCoreClock = 1000000000U;
+
+	/* Clear TE bit to take exceptions in Thumb mode to fix the DDR init */
+	write_sctlr(read_sctlr() & ~SCTLR_TE_Msk);
+	barrier_isync_fence_full();
+}
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("APB1", 0x40000000, 0x19400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB2", 0x44000000, 0x14000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB2", 0x48000000, 0x1040000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB6", 0x4C000000, 0xC400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB4", 0x50000000, 0xD400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB3", 0x50020000, 0xA400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("DEBUG APB", 0x50080000, 0x5D000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB5", 0x54000000, 0x8000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AXIMC", 0x57000000, 0x100000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB6", 0x58000000, 0x10000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB4", 0x5A000000, 0x7400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB5", 0x5C000000, 0xA400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("GIC", 0xA0021000, 0x7000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("vectors", 0xC0000000, 0x1000, MPERM_R | MPERM_X | MT_NORMAL),
+
+	MMU_REGION_FLAT_ENTRY("DAPBUS", 0xE0080000, 0x5D000, MPERM_R | MPERM_W | MT_DEVICE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/st/stm32/stm32mp13x/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32MP13SOC_H_
+#define _STM32MP13SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32mp13xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32MP13SOC_H_ */