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soc: ITE: ilm: Enable instruction memory for it51xxx series

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Enable instruction memory for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2025-03-18 08:59:59 +08:00 • committed by Benjamin Cabé
commit d9571f6412
10 changed files with 132 additions and 49 deletions
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5
dts/riscv/ite/it51xxx.dtsi
View file

@ -61,6 +61,11 @@
reg = <0x800000 DT_SIZE_K(128)>;
};
ilm: ilm@f01040 {
compatible = "ite,it8xxx2-ilm";
reg = <0xf01040 3>; /* SCAR0 */
};
gpiogcr: gpio-gcr@f01600 {
compatible = "ite,it51xxx-gpiogcr";
reg = <0x00f01600 0x100>;

2
soc/ite/ec/it51xxx/CMakeLists.txt
View file

@ -1,6 +1,8 @@
zephyr_sources(soc.c vector.S)
zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_SOC_IT51XXX_USE_ILM ../it8xxx2/ilm.c ilm_wrapper.c)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld
CACHE INTERNAL "SoC Linker script ${SOC_NAME}"
)

14
soc/ite/ec/it51xxx/Kconfig
View file

@ -30,4 +30,18 @@ config SOC_IT51XXX_CPU_IDLE_GATING
gated by individual drivers. When this option is disabled, CPU idle
mode is always permitted.
config SOC_IT51XXX_USE_ILM
bool
default y
help
If enabled, Instruction Local Memory (ILM) will be configured to execute
code placed in the .__ram_code section out of RAM. This consumes RAM in
blocks of 4 kilobytes, but performance of code in ILM is much more
predictable than executing from Flash directly, and some code (such as code
that writes to the internal Flash) must execute out of RAM.
config ILM_MAX_SIZE
int "ILM Size in kB"
default 4
endif # SOC_SERIES_IT51XXX

15
soc/ite/ec/it51xxx/chip_chipregs.h
View file

@ -69,6 +69,9 @@ struct smfi_it51xxx_regs {
#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
/* Enable EC-indirect page program command */
#define IT51XXX_SMFI_MASK_ECINDPP BIT(3)
/* 0x42: Scratch SRAM 0 address high byte */
#define SCARH_ENABLE BIT(7)
#define SCARH_ADDR_BIT19 BIT(3)
/**
*
@ -269,8 +272,14 @@ struct gctrl_it51xxx_regs {
volatile uint8_t reserved_21_37[23];
/* 0x38: Special Control 9 */
volatile uint8_t GCTRL_SPCTRL9;
/* 0x39-0x84: reserved_39_84 */
volatile uint8_t reserved_39_84[76];
/* 0x39-0x46: reserved_39_46 */
volatile uint8_t reserved_39_46[14];
/* 0x47: Scratch SRAM0 Base Address */
volatile uint8_t GCTRL_SCR0BAR;
/* 0x48: Scratch ROM 0 Size */
volatile uint8_t GCTRL_SCR0SZR;
/* 0x49-0x84: reserved_49_84 */
volatile uint8_t reserved_49_84[60];
/* 0x85: Chip ID Byte 1 */
volatile uint8_t GCTRL_ECHIPID1;
/* 0x86: Chip ID Byte 2 */
@ -298,6 +307,8 @@ struct gctrl_it51xxx_regs {
#define IT51XXX_GCTRL_LRSIPGWR BIT(0)
/* 0x38: Special Control 9 */
#define IT51XXX_GCTRL_ALTIE BIT(4)
/* 0x48: Scratch ROM 0 Size */
#define IT51XXX_GCTRL_SCRSIZE_4K 0x03
/* Alias gpio_ite_ec_regs to gpio_it51xxx_regs for compatibility */
#define gpio_ite_ec_regs gpio_it51xxx_regs

16
soc/ite/ec/it51xxx/ilm.h Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
/* Places code in the section that gets mapped into ILM */
#define __soc_ram_code __attribute__((section(".__ram_code")))
#ifndef _ASMLANGUAGE
void custom_reset_instr_cache(void);
bool it8xxx2_is_ilm_configured(void);
#endif

19
soc/ite/ec/it51xxx/ilm_wrapper.c Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <ilm.h>
#include <soc_common.h>
#include <zephyr/kernel.h>
void __soc_ram_code custom_reset_instr_cache(void)
{
struct gctrl_it51xxx_regs *const gctrl_regs = GCTRL_IT51XXX_REGS_BASE;
/* I-Cache tag sram reset */
gctrl_regs->GCTRL_SCR0BAR = 0;
/* Make sure the I-Cache is reset */
__asm__ volatile("fence.i" ::: "memory");
}

22
soc/ite/ec/it51xxx/linker.ld
View file

@ -179,6 +179,17 @@ SECTIONS
*(".text.*")
*(.gnu.linkonce.t.*)
#include <zephyr/linker/kobject-text.ld>
. = ALIGN(0x1000);
/* Mapping base address must be 4k-aligned */
__ilm_flash_start = .;
/* Specially-tagged functions in SoC sources */
KEEP(*(.__ram_code))
*(.__ram_code.*)
__ilm_flash_end = .;
/* ILM mapping is always a multiple of 4k size; ensure following
* sections won't incorrectly redirect to RAM. */
. = ALIGN(0x1000);
} GROUP_LINK_IN(ROMABLE_REGION)
__text_region_end = .;
@ -242,6 +253,17 @@ SECTIONS
GROUP_START(RAMABLE_REGION)
. = RAM_BASE;
/* Claim RAM for ILM mappings; must be 4k-aligned and each mapping is 4k in size */
SECTION_PROLOGUE(ilm_ram,(NOLOAD),ALIGN(0x1000))
{
__ilm_ram_start = .;
. += __ilm_flash_end - __ilm_flash_start;
__ilm_ram_end = .;
/* Aligning 4k ensures ILM doesn't overwritte RAM. */
. = ALIGN(0x1000);
} GROUP_LINK_IN(RAMABLE_REGION)
_image_ram_start = .;
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.

3
soc/ite/ec/it51xxx/soc.c
View file

@ -105,6 +105,9 @@ void soc_prep_hook(void)
/* Scratch ROM0 is 4kb size */
gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
/* Scratch ROM0 is 4kb size */
gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
/* bit4: wake up CPU if it is in low power mode and an interrupt is pending. */
gctrl_regs->GCTRL_SPCTRL9 |= IT51XXX_GCTRL_ALTIE;

3
soc/ite/ec/it8xxx2/chip_chipregs.h
View file

@ -922,6 +922,9 @@ struct smfi_it8xxx2_regs {
/* Host RAM Window x Write Protect Enable (All protected) */
#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
/* 0x42: Scratch SRAM 0 address high byte */
#define SCARH_ADDR_BIT19 BIT(7)
#define SCARH_ENABLE BIT(3)
/**
*

82
soc/ite/ec/it8xxx2/ilm.c
View file

@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc_common.h>
#include <stdbool.h>
#include <stdint.h>
@ -46,9 +47,6 @@ BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must
#define ILM_NODE DT_NODELABEL(ilm)
#define SCARH_ENABLE BIT(3)
#define SCARH_ADDR_BIT19 BIT(7)
/*
* SCAR registers contain 20-bit addresses in three registers, with one set
* of SCAR registers for each ILM block that may be configured.
@ -158,51 +156,41 @@ static int it8xxx2_ilm_init(const struct device *dev)
#define SCAR_REG(n) (volatile struct scar_reg *)DT_REG_ADDR_BY_IDX(ILM_NODE, n)
static const struct ilm_config ilm_config = {
.scar_regs = {
/* SCAR0 SRAM 4KB */
SCAR_REG(0),
SCAR_REG(1),
SCAR_REG(2),
SCAR_REG(3),
SCAR_REG(4),
SCAR_REG(5),
SCAR_REG(6),
SCAR_REG(7),
SCAR_REG(8),
SCAR_REG(9),
SCAR_REG(10),
SCAR_REG(11),
SCAR_REG(12),
SCAR_REG(13),
SCAR_REG(14),
/*
* Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX
* maximum ILM size are 60KB, the ILM size of other varients
* are equal to the SRAM size.
*/
.scar_regs = {/* SCAR0 SRAM 4KB */
SCAR_REG(0),
#if (CONFIG_ILM_MAX_SIZE > 4)
SCAR_REG(1), SCAR_REG(2), SCAR_REG(3), SCAR_REG(4), SCAR_REG(5), SCAR_REG(6),
SCAR_REG(7), SCAR_REG(8), SCAR_REG(9), SCAR_REG(10), SCAR_REG(11),
SCAR_REG(12), SCAR_REG(13), SCAR_REG(14),
#endif
/*
* Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX
* maximum ILM size are 60KB, the ILM size of other variants
* are equal to the SRAM size.
*/
#if (CONFIG_ILM_MAX_SIZE == 256)
/* SCAR15 SRAM 4KB */
SCAR_REG(15),
/* SCAR16 SRAM 16KB */
SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
/* SCAR17 SRAM 16KB */
SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17),
/* SCAR18 SRAM 16KB */
SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18),
/* SCAR19 SRAM 16KB */
SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19),
/* SCAR20 SRAM 32KB */
SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
/* SCAR21 SRAM 32KB */
SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
/* SCAR22 SRAM 32KB */
SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
/* SCAR23 SRAM 32KB */
SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23),
SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23)
/* SCAR15 SRAM 4KB */
SCAR_REG(15),
/* SCAR16 SRAM 16KB */
SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
/* SCAR17 SRAM 16KB */
SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17),
/* SCAR18 SRAM 16KB */
SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18),
/* SCAR19 SRAM 16KB */
SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19),
/* SCAR20 SRAM 32KB */
SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
/* SCAR21 SRAM 32KB */
SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
/* SCAR22 SRAM 32KB */
SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
/* SCAR23 SRAM 32KB */
SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23),
SCAR_REG(23), SCAR_REG(23), SCAR_REG(23)
#endif
}};
BUILD_ASSERT(ARRAY_SIZE(ilm_config.scar_regs) * ILM_BLOCK_SIZE == KB(CONFIG_ILM_MAX_SIZE),