1. the three boards share the same board schematic
- frdm_mcxa266, frdm_mcxa346, frdm_mcxa366
2. board dts,kconfig and cmake file could share
3. add MCXA366 soc and frdm_mcxa366 board
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Add initial power management support for i.MX943 M-core (M33/M7)
This lays the foundation for multi-core PM handling on i.MX943
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Improve how segment information looks like for MCUboot and SimpleBoot.
* silently igonore padding segments (if VMA is 0x0)
* do not duplicate mapped segments lines (IROM and DROM)
* fix IROM segments taht was incorrectly labeled as IRAM
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This reworks the Intel audio DSP host IPC driver as a backend of
the IPC service. This is the first step to rework IPC in SOF
(Sound Open Firmware) into using a more generic IPC API instead
of a SoC specific one.
For now, it keeps the old interface to maintain usability
as it is going to be a multiple process to rework IPC
over there.
Also, the structure of the new IPC backend resembles
the SoC specific driver to make it easier to compare
between them at this first iteration. Future optimizations
will probably be needed once we start modifying the SOF
side to utilize the IPC interface.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC specific IPC driver is for host IPC, and not IDC (which
is between CPUs). So there is no need to use the IDC devicetree
binding to enable the kconfig.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add micro heap implementation which is using one or more 32 bit masks
to allocate quickly blocks. It is significantly better than using
sys_heap. Difference is especially big on RAM3 heap because heap
control data is in RAM3 space so operations there were extremely
slowly (15 us to allocate a buffer).
Simplified implementation of the heap requires DMM API change as
release functions need to know the length of the allocated buffer as
simple heap requires that (buffer address is enough for the standard
heap).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Default memcpy used in zephyr is not optimized and performs simple
byte by byte copying. Using double word or word access can significantly
reduce copying time especially for RAM3 (slow peripheral RAM).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The RP2350 SoC series contain two Hazard3 cores, which use the RISC-V
instruction set. Define a new CPU cluster (`hazard3`), which is intended
to be used with the two Hazard3 cores 'plugged in' to the two 'sockets'
in the RP2350 series SoCs.
Update the linker script to support linking against the correct
(ISA-specific) linker script, and to generate a correct IMAGE_DEF for
the target ISA.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
The RP2350 uses the Xh3irq interrupt controller, which supports nested
and prioritised interrupts. This adds initial support, configuring the
controller in 'direct' (non-vectored) mode.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Before re-entering Power Mode 3, we should disable the GET
sensor and reinitialize the power rails.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add the mapping for the GRTC_CLKOUT_FAST pinctrl mapping to the
periphconf generation. This allows clocking out the 16MHz clock with a
user selectable divider.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch
for developer if they want to use private mpu settings
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific
- Use DT function to get memory base address and region size for cm7
- CM33 use dts to set mpu settings
- Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways
to map actual memory_size_kb to "region_size"
- The settings of the unified memory on cm33/cm7 cores:
ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR
ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR
flexspi/itcm -> REGION_FLASH_ATTR
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit adds multicore support to copy CM33 CPU1 image
from flash to RAM where it will boot from.
Also added NXP_IMXRT_BOOT_HEADER=y for CPU0 so it can be booted
from FlexSPI Flash.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Sets the default of this Kconfig for the SoC itself as a default,
rather than each board setting it, which minimises the change
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixed the include directive for mchp_pinctrl_pinmux_sam.h
by replacing quotes with angle brackets.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
- Update the path of pinctrl.h in sama7g54_ek.dts
- Select CONFIG_MICROCHIP_SAM for sama7g5 family devices
- Add SAM group Kconfig symbol for proper family grouping
- Rename PIC32C Kconfig symbol to MICROCHIP_PIC32C
and update references
- Update west.yml for hal-microchip re-organization
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
The config PM_S2RAM_CUSTOM_MARKING is not an optional config for a
user to select, it is required by some soc implementations of S2RAM,
in which case it must be selected by the soc.
Refactor the configuration to be HAS_PM_S2RAM_CUSTOM_MARKING, and
make the currently only soc which needs it select it. Then update
samples which previously had to select this option for this soc.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Select ARM_ARCH_TIMER when RZ_OS_TIMER is not selected
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This commit should deal with updating the re-configuration of the
I-cache controller when buidling for mcuboot. Previously, the whole
controller was updated, given that a slot entry adheres to controller's
peculiarities (that is an image should be aligned to specific image sizes
i.e. 256kB, 512kB, etc). However, that approach should adversely affect
flash memoy layout. The proposed scheme now imposes that images be aligned
to minimum cache-able area, that is 64KB.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
- Add SOC interrupt properties and interrupt-names ("reset_prep", "pcidev",
"pmu2ioapic") to intel_ish5 DTS files so PM IRQs are discoverable via DT.
- Move SEDI PM initialization and IRQ setup into ISH SOC PM init:
- Remove the direct call to sedi_pm_init() from soc_early_init_hook in
soc.c.
Previously SEDI code has those IRQ numbers hard coded and calls Zephyr APIs
to connect IRQs, which should be avoided.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
- cleanup header files included.
- Rename LOG_MODULE_REGISTER from pm_service to ish_pm and use
CONFIG_PM_LOG_LEVEL.
- Guard verbose debug traces so they only print for suspend-to-RAM/long
idle states, reducing runtime noise.
- Promote an unsupported power state message from LOG_DBG to LOG_ERR.
No functional change to power handling; changes are limited to logging
and verbosity control.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Select ARM DWT feature to suppress build warning related to null pointer
detection mechanism.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add UICR.SECURESTORAGE configuration based on device tree partitions.
Validates partition layout and populates size fields in 1KB units.
Handles missing partitions gracefully.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Switch to using the new NXP_ENABLE_WAKEUP_SIGNAL and
NXP_DISABLE_WAKEUP_SIGNAL macros to avoid adding
platform specific calls in the Zephyr drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The SDK code to handle managing Wakeup IRQ's for low power mode
varies between SoC's.
Add a MACRO that can be called by the Zephyr drivers so we
can manage these variations without adding SoC specific code
to the drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Using WDT_DISABLE_AT_BOOT instead of WDOG_ENABLE_AT_BOOT prevents the
definition of z_arm_watchdog_init, which is important because the COP
watchdog configuration register can only be configured once.
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
Ensuring flash region has been erased before writing to avoid
inconsistences and force expected erased value (0xFF) into
flash when erasing a region when Hardware Flash Encryption is
enabled
This is handled on this implementation because MCUboot's state
machine relies on erased valued data (0xFF) readed from a
previously erased region that was not written yet, however when
hardware flash encryption is enabled, the flash read always
decrypts whats being read from flash, thus a region that was
erased would not be read as what MCUboot expected (0xFF).
Signed-off-by: Almir Okato <almir.okato@espressif.com>
