Currently the RAM allocated for the bootloader is not
enough to use MCUBoot with crypto signatures.
This commit bumps the #defines accordingly to fix
compile errors with ecdsa_p256 and RSA.
Signed-off-by: Brandon Allen <brandon.allen@exacttechnology.com>
Devicetree should be used instead. Example DT snippets are provided to
ease with the transition.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Update CONFIG_ESP_SIMPLE_BOOT to exclude if CONFIG_MCUBOOT=y
Fix usage of the config according to actual definition.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Timer/PWM Module (TPM) initial clock source is not selected.
Add initial clock source selection based on Devicetree configuration.
Rename clock sources definitions from LPUART specific to general names
usable by several modules on the SoC.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
cavs15, cavs18 and cavs20 were removed from Zephyr there is no
need to handle those platforms in the tool.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix USB w/ SPEED_OPTIMIZATIONS for LPC55xxx SoCs
Root cause was non-volatile register access,
which could get optimized by the compiler
(by -fschedule-insns, specifically)
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Imply CONFIG_INIT_AUDIO_PLL on nxp,dmic driver selection on
mimxrt685s/cm33. Make DMIC clock config dependent on the use of the
RT685's audio PLL.
Fixes a regression described in #77851.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The STM32WB06 and STM32WB07 SoCs do not support SMPS output current limit.
This makes the LL_PWR_SetSMPSPrechargeLimitCurrent function and all the
LL_PWR_SMPS_PRECH_LIMIT_CUR_xxx defines not visible when one of these SoCs
is selected, resulting in a build failure.
Fix this by only handling SMPS current limit when the feature is available.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
On platforms with enforced memory access modes, .text is read-only.
Move hpsram_mask to a cached data section to fix PTL.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Rework how flash is initialized in esp32 SoC.
"esp_flash_app_init()" will make sure proper cache handling
will be set in place.i
Fixes#77551
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Generic hook infrastrucutre was added to Zephyr, but NXP MCXC SoCs
were not updated accordingly.
Use generic hook infrastrucutre for MCXC SoCs.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
This patch addresses an issue in the ACE platform power management code
where the HST domain suspend operation was performed after the IMR
context save. This resulted in the power management context being
restored with outdated values upon wake-up from D3 state, leading to a
failure to resume the HST domain correctly.
By moving the `pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV)` call
before the IMR context save, we ensure that the HST domain is suspended
with the current context, and upon resume, the power management context
has the correct information to restore the HST domain state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
check if two or three I2C instances with same irq are enabled
at same time then enable shared_interrupt handler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
