Replaces hard-coded memory addresses and sizes with macros that retrieve
such values from the device tree.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding
Note that for PDRV type pins, this commit effectively switches their
drive strength setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The MT8196 device has a newer interrupt controller that acts like the
legacy ones once initialized (see intc_mtk_adsp.c). But it has some
(only slightly) more complicated routing control that must be
initialized on reset, as the default is "don't deliver any interrupts
at all". Previous versions of the device integration worked becuase
they relied on a SOF binary to be loaded at boot, but obviously that
doesn't work for a Zephyr-based SOF firmware image.
Signed-off-by: Andy Ross <andyross@google.com>
This driver forgot to enable its interrupt, but has been working
becuase Zephyr apps were always run in a context where the interrupt
controller had been initialized by a SOF binary at boot.
Signed-off-by: Andy Ross <andyross@google.com>
This got missed. Set it correctly for hygiene, though very few things
use it. There is a spot in SOF where it's helpful to have a number for
"fasted cpu clock rate" and this is the best candidate.
Signed-off-by: Andy Ross <andyross@google.com>
I thought I was being clever letting the linker place the entry point
arbitrarily (since the hardware can set it to any value).
But it turns out that the upstream Linux SOF loader code is hard-wired
to start the DSP only at the first byte of SRAM, always, no matter
what entry point is listed in the rimage file. So until/unless this
is fixed, we need to add a trampoline at the start of SRAM (and
frustratingly that needs to be 1024 bytes long becuase of the
alignment requirements of the vector table that follows it, sigh...)
Signed-off-by: Andy Ross <andyross@google.com>
This is mostly a cut/paste copy of similar code in intel_adsp and imx,
which sadly can't be shared given the way the design works. Also
includes a bonus, slightly-passive-aggressive description of why that
is.
Signed-off-by: Andy Ross <andyross@google.com>
APPROTECT symbols were already aligned to nRF54L15,
but did not take into account similar SoCs like nRF54L05 or L10.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Many NXP socs had the following defconfig:
```
config PINCTRL_IMX
default y if HAS_IMX_IOMUXC
depends on PINCTRL
```
However, the PINCTRL_IMX option already has:
```
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
default y
help
Enable pin controller driver for NXP iMX series MCUs
```
So the soc level defconfigs are redundant.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This definition is deleted in the follwoing commit;
8233b70
as a part of "cleanup", however this definition is
used by smp_log
Signed-off-by: Arif Balik <arifbalik@outlook.com>
Correctly selects the Kconfig symbols for viper CPU clusters
instead of having a reverse hwmv1 setup where the symbol has
a choice
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
check if multiples UART instances with same irq are enabled
at same time then enable shared_interrupt handler.
set the default value of SHARED_IRQ_MAX_NUM_CLIENTS config if
we have more than 2 usarts instances enabled.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
- Move selection of CONFIG_PINCTRL from soc to individual
drivers
- in accordance with issue #78619
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Gap filling in hex files are now disabled per default, and therefore
there is no reason to explicitly disable gap filling.
It has never been possible to disable gap filling in binary files.
Disabling gap filling would just result in the binary file to be gap
filled with the tool's default value, objcopy=0x00.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fixes a wrong placement of a Kconfig which was put into the
wrong file and was bleeding through to every board
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This reverts commit 3d3ffa2c05.
The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.
Reverting this commit restores access to these critical registers and
resolves the regression issue.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Release HSI CLK48 semaphore when going to sleep to allow C2 (M0)
core to start and stop clock as needed while C1 core is not running.
CLK48 is shared between RNG and USB. RNG is needed by M0 during BLE
advertisement. If semaphore is locked, C2 core can start it when it
needs to but not stop it.
Fixes zephyrproject-rtos#69955.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
These devices have an architecturally fixed 13 MHz clock device. But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.
Signed-off-by: Andy Ross <andyross@google.com>
Add Zephyr support for the Audio DSP on the MT8196 SOC. This is a
very similar device to previous designs. Most of this patch is just
DTS.
The biggest delta is the more complicated second level interrupt
controller, though it is still able to be represented using some
vaguely clever DTS config over the older intc_mtk_adsp driver.
Also the memory layout is slightly different, requiring a little
indirection to set the initial boot stack address and log output
buffer. And the timer "irq_ack" register bits moved.
Signed-off-by: Andy Ross <andyross@google.com>
New platform has different mappings. Auto-detect rather than parse
dts or similar, as this is is really just a simple format for testing.
Signed-off-by: Andy Ross <andyross@google.com>
The early boot function got renamed to a pseudo-standard "z_prep_c",
but this isn't an actual API and doesn't have a prototype in the
headers anywhere, so the compiler started whining about an undeclared
function.
Signed-off-by: Andy Ross <andyross@google.com>
These are very similar devices to mt8195, minimal changes needed
beyond boilerplate configuration.
In the process, this reworks the board/soc layout to be HWMv2
compliant, with "adsp" becoming a CPU cluster beneath the SOC. So the
name of the boards to west become e.g. "mt8195/mt8195/adsp" (which can
be shortened to "mt8195//adsp" if desired).
Note that the cpuclk driver is not yet ported, it works only with 8195
(the clocking/power architecture seems similar between the parts, but
the graph of wells and clocks is different and historically these have
been three separate drivers in SOF). The biggest changes are in the
image/loader scripts, which needed some rework for cross-device
portability.
Signed-off-by: Andy Ross <andyross@google.com>
This is a feature of the 8195 DSP only, which is used only vestigially
by SOF to store data that nothing reads. The Linux kernel on the
other side uses a shared driver for all 81xx devices, which does not
expose the feature. It seems to work, but it's not worth maintaining
a driver in tree for legacy hardware that will never use it.
Signed-off-by: Andy Ross <andyross@google.com>
Wire the default printk output to the console at boot, just to be sure
we have stdio output good enough to get tests to pass.
Signed-off-by: Andy Ross <andyross@google.com>
Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.
To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.
`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Silicon Labs Series 2 and newer devices do alternate function
configuration fundamentally differently from Series 0 and 1. Pin routing
is done in a centralized fashion in the GPIO peripheral, as opposed to
having ROUTE registers in every peripheral. The concept of alternate
function location numbers also does not exist, functions are directly
assigned to GPIOs by their port and pin number.
This commit adds a new pinctrl driver for devices that use DBUS. It fully
makes use of pinctrl design principles as outlined in the Zephyr
documentation. The previous driver hard-codes pin properties such as filter
and pull-up/down in the driver itself, while the new driver leaves this up
to the user as configurable DeviceTree properties. The previous driver has
hard-coded support for UART, SPI and I2C, while the new driver has generic
support for all DBUS signals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
FH4X SoC type contains improvements in ROM code that
can save up to 35kB of memory.
Update hal_espressif in order to select proper linker
file based on upon SoC model.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Disables on reset NMI and EzPort.
- Fixes possible reset and power-on issues.
- Already applied for K64, now applying for the rest of Kinetis.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
- Trace32 runner: no need to configure TE bit in CFG_CORE
register in the cmm start-up script, it can be configured
at Zephyr start-up code when required (via SCTRL register)
- MPU static regions also needs to be updated for XIP and
non-XIP
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Use Zephyr cache API to initialize cache as done for
various platforms. Enabling CACHE_MANAGEMENT by default
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Due to the possibility of simultaneous accesess to LRCCONF registers,
additional management is required.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
