Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The i.MX95 applications processor features advanced graphics and
video cores, powerful vision and machine learning acceleration,
efficient CPU performance, real-time processing, and advanced
security with the integrated EdgeLock® secure enclave to support
energy-efficient edge computing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Get console baudrate property from device tree to allow
proper configuration for 26 and 40 Mhz devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The custom linker script was required because SOF needed
some extra linker sections. Other than that, the custom linker
script was identical to the common architecture script. This
commit removes the custom linker script because:
* keeping the custom linker script in sync with the
common one is troublesome.
* application-specific linker sections shouldn't be
included in the generic soc linker script. Instead,
they should be handled at the application level
(i.e: via cmake commands if additional sections are
needed or via a new, custom linker script if more
changes are needed)
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add condition for KConfig Renesas FSP hal module
Move the DUAL_BANK_MODE from SOC to flash driver KCONFIG
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Fix flexspi xip configuration issue regarding code relocation
due to the order of kconfig defaults being sourced
The flexspi setup was not being relocated to an on chip location
Also remove rt1060 conf file in flash common test which changes the
code relocation location to RAM, just keep as ITCM for all M7 which
as of now all have ITCM from NXP with flexspi.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
VPR addresses are platform-dependent, so let's use a common symbol -
CONFIG_NRF_PLATFORM_HALTIUM - to cover both nRF54H and nRF92 series.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
PMIC service should be supported on Application and Radiocore, whereas
DVFS service is currently unsupported.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Booting VPRs requires changing the default value of CONFIG_RV_BOOT_HART.
This must be reverted (back to zero) for a future nRF9230 SoC revision,
which will align more closely with the RISC-V spec.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Production version of the nRF54L15 SoC needs reset reason
to be cleared before going into system off.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Assembly in power_down() in power_down.S already defines data and
code to be locked in cache when powering down SRAM. Instead of adding
another such location in power.c, move the hpsram_mask[] array into
power_down.S. This fixes hard to debug failures when shutting down
the ADSP.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARC.
Replace soc_early_asm_init_percpu() with platform_reset()
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Include compile of the flash file when FlexSPI_XIP is enabled
even when the FlexSPI driver is not enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)
Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In order to get all data from STMESP written to ETR and processed
on time we need to write dummy data before sleep.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add functions for local domain suspend to RAM. Add matching resume
procedure. Add pm_s2ram function for determining source of reset.
Add preserving NVIC and MPU state in retained RAM when CPU is powered off
during S2RAM procedure.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
CLOCK_CONTROL subsystem is expected to be enabled systematically on all
STM32 devices.
Make it a series default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Use the correct define for checking if the DCDC converter shall be
enabled.
This resolves the opposite behavior where boards that enable the DCDC
converter uses the LDO and boards where LDO is used they enable the
DCDC.
Fixes: e189fb0720 ("soc: nordic: nrf52: add support for DT-based
regulators config")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Add custom clock_control API for nRF platforms that allows requesting
clocks with specified minimal required attributes (accuracy, precision,
and frequency). Provide an implementation of this API for FLL16M, HFXO,
HSFLL, and LFCLK controllers in the nRF54H20 SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This commit introduces a new Kconfig option `CONFIG_SRAM_RETENTION_MODE`
that allows the configuration of SRAM retention mode during the
initialization phase of the firmware boot-up process. By default, the
retention mode is enabled to maintain the existing behavior. However,
this option provides the flexibility to disable the retention mode if
needed, without modifying the Zephyr codebase.
The SRAM initialization functions `hp_sram_init` and `lp_sram_init` in
`sram.c` have been updated to conditionally set the retention mode based
on the value of this Kconfig option.
Additionally, an unused macro `DELAY_COUNT` has been removed from
`sram.c` to clean up the code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adds support for settings/getting RTC time and using alarm/update feature.
The alarm option needs all fields to be set due to a hardware limitation.
RTC shares the same interrupt with the watchdog. Thus shared
interrupts must be enabled when WDT and RTC both need to trigger the ISR.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Prevent `warning: orphan section `.note.GNU-stack'` when building using
`west build -b xt-sim samples/hello_world`
Signed-off-by: William Tambe <williamt@cadence.com>
The ringbuffer availability check is subject to race with regards to
update of BF (Buffer Full) and BNE (Buffer Not Empty) bits in DGCS
register, and status of RP (Read Position) and WP (Write Position).
Following sequence is observed without this patch when
calling dma_get_status() on multiple Intel ADSP platforms:
iter 154 pending 1536 RP 768 WP 768, BNE 1, BF 1
-> dma_reload for 384
iter 155 pending 1536 RP 1152 WP 1152, BNE 1, BF 1
-> dma_reload for 384
iter 156 pending 0 RP 0 WP 0, BNE 1, BF 0
Value of pending is not expected to go from 1536 to zero if only 384
bytes have been consumed via dma_reload() since last call to
dma_get_status().
Change the logic to read DGCS register later, after the WP and RP have
been already read, and only check the BNE bit if Read and Write
Positions are equal.
Link: https://github.com/thesofproject/sof/issues/9418
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Co-developed-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Xtensa toolchains also contain a profile for sample_controller.
So if compiling for it, skip the Xtensa HAL module in Zephyr
tree so the toolchain can use the one included in the toolchain.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
So far 10 kHz tick rate was used but it has 2 drawbacks:
- kernel timer precision is limited to 100 us which is worse compared
to 30 us on platforms which use RTC (which had 32768 Hz tick rate)
- GRTC has 1 MHz frequency so tick rate requires dividing by 100 during
timeout calculation. When 31250 Hz is used (which is 1000000 / 32)
then dividing can be done with bit shifting and it is faster (> 2 times
faster on Cortex-M33 and >8 times faster on VPR - RISCV).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
With ACE2/3 the HDA DMA includes registers to read the Linear Link
Position.
Previous platforms (CAVS, ACE1) was able to report the LLP for GPDMA. Since
ACE2 all links are handled with HD-DMA, hence the new register has been
added for the firmware to report the LLP to the host.
Set the total_copied to 0 for older ACE1/CAVS platforms and in case of
host DMA on ACE2/3 since the informatiojn is not available.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add nrf5x binding header, as NRF5X_REG_MODE_DCDC is used in a macro
comparison. Missing header prevented evaluation to become true and so
enable DC/DC module.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP
is implemented, causing issues related to included Zephyr linker files.
Flash code still resides in flash for execution, but MMU/Cache handles it
in such way that XIP might not (or should not) be used with current Zephyr
approach. To address this problem, XIP configuration option is being
removed from Espressif targets.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
RT1011 expects it's flash configuration block at a different offset than
the rest of the RT10xx series. Add default to fix the platform not
booting.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
