The lfrccal takes the two properties tempMeasIntervalSeconds and
tempDeltaCalibrationTriggerCelsius which are in steps of 0.25.
The bicrgen.py script incorrectly treated these values as steps
of 1, so the actual values written to (and read from) bicr where
scaled incorrectly.
This commit fixes the scaling for those two props.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This brings CMSIS HAL glue code, which is required if we want to enable
any HAL module without everything blowing up. cmsis_core_m_defaults.h
cannot be used once we enable HAL. CMSIS is that nice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SF32LB52x is a SoC from SiFli Technologies(Nanjing) Co., Ltd, based on
Arm Star-MC1 core (Cortex-M33 compatible).
For more details, see:
https://wiki.sifli.com/en/hardware/SF32LB520-3-5-7-HW-Application.htmlhttps://wiki.sifli.com/en/hardware/SF32LB52B-E-G-J-HW-Application.html
0-3-5-7 are powered using a Lithium battery and support USB charging.
B-E-G-J are powered at 3.3V and do not support charging.
Other termination codes indicate what type of memory and size is
embedded in the package (QSPI NOR or PSRAM).
Other families exist within the SF32LB family, like SF32LB56x,
SF32LB58x, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Currently, the DMA on several Renesas boards is failing due to
the security attribution of DMA.
As a solution: Enable secure security attribution
for DMA module for:
- RA6: ra6e1, ra6e2, ra6m4, ra6m5
- RA4: ra4c1, ra4e1, ra4e2, ra4l1, ra4m2, ra4m3
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Enable CONFIG_PM_DEVICE_RUNTIME_DEFAULT_ENABLE by default for all
nordic SoCs if CONFIG_PM_DEVICE_RUNTIME is used. This will ensure
consistent behavior across all nordic SoCs and remove the need
for pasting the devicetree propert zephyr,pm-device-runtime-auto
everywhere.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add support for BGM220P modules. Enable oscillators in SoC DTS
since the necessary crystals are present in the modules.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add missing EUART0 peripheral to devicetree for xg22.
Fix NUM_IRQS, there are 64 external interrupts on xg22.
Remove `select` of UART_INTERRUPT_DRIVEN at SoC level, this doesn't
belong here, since it prevents disabling the UART. This should be a
board or application level decision.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Because generation and programming of UICR + PERIPHCONF artifacts
depend on the 'uicr' image which in turn must be included by Sysbuild,
many if not most nrf54h20 applications will need to be built using
Sysbuild to function as intended.
To make this known to the user, print a CMake warning whenever
CONFIG_NRF_PERIPHCONF_SECTION=y but Sysbuild is not being used.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add build system support for populating the PERIPHCONF
(global domain peripheral configuration), based on nodes and properties
found in the devicetree. This should make it so all samples and tests
that were broken by the move to IronSide SE now function correctly
without workarounds or manual steps.
When enabled, a new python script called gen_periphconf_entries.py is
run when building. The script iterates over nodes and properties in the
devicetree and generates a C file called periphconf_entries_generated.c
in the build directory, which is added as a source file. The C file
uses the macros from uicr.h to configure the global domain according
to the devicetree.
The PERIPHCONF entry generation is enabled by default when building
for nrf54h20dk/nrf54h20/cpuapp and nrf54h20dk/nrf54h20/cpurad.
It will also be used on nrf9280 soon, therefore it is placed
in the common uicr directory.
This new feature does the same job as nrf-regtool did when building
for nrf54h20 before, and is compatible by the bindings that were used
by nrf-regtool.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
In !XIP case, provide RAM_RO and RAM_RW regions with their
respective MPU configurations.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Co-authored-by: Sudan Landge <sudan.landge@arm.com>
MCU_GAP_FILLING is advised on ARMv8 based platforms to prevent from
against attacks that attempt to execute malicious code from SRAM.
It is enabled by default when USERSPACE is disabled, enable it
also when enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Originally the driver is selected if `HAS_MCUX_SRC_V2` is
selected in SOC level kConfig.
Change to use dts to mark the driver is avaiable for some SOC.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Added support for sys_poweroff on ADL and ATOM socs based on
acpi_poweroff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Add linker support for OpenAMP sample on Renesas RZ/V2L
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Create separate memory regions for each OFS register. With a single
region the linker will gap fill the load segment with zeros between
each option setting section that gets placed in the region when
generating the .elf file.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
This commit updates the GDMA register definitions to align with the
specifications of the chip series.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
The .bin file is huge (>1GB) and will probably not be used by anyone if
there are much smaller alternatives. Because of that, disable it by
default for this soc. There is also no support for generating the
CRC32 checksum for the ccfg section in the binary.
Signed-off-by: Fabian Pflug <fabian.pflug@gumulka.eu>
As stated in [0] section 9.2 Customer Configuration:
There are four different CRCs used to validate the CCFG data.
One of the CRCs, the user record CRC, is optional and is the
last four bytes of the 128B user record. The data over which
the CRC is calculated starts at “Data Start Offset” from Table
9-2 and ends at the "CRC Offset". CRC field width is 4 bytes.
Meaning the MCU will not start if the CRC fields are not correct.
TI's tools will automagically set these fields, but other tools have to
do it by hand. Therefore a new post-build-command is introduced to set
the fields at least in the .hex file by generating a new _crc32.hex
file.
[0] https://www.ti.com/lit/ug/swcu193a/swcu193a.pdf
Signed-off-by: Fabian Pflug <fabian.pflug@gumulka.eu>
Although not reproducible locally, it has been observed in CI that the
uicr image will not always be the last image to be run.
To ensure it is the last image to be run we have it depend on the
'image' image when defined.
The uicr image is generated based on all other images in the build and
must therefore run last.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Remove hp_sram_init() call from boot_d3_restore() as it's redundant and
causes TLB access errors. The TLB driver's adsp_mm_restore_context()
already handles all HPSRAM power management and content restoration.
The removed code was attempting to zero memory regions that are
intentionally unmapped by the TLB driver for power optimization, causing
access to disabled TLB entries during D3→D0 transitions.
Additionally, hp_sram_init() powers up all memory banks while the TLB
restore function correctly enables only the banks that were actually
used, maintaining proper power optimization.
Current flow causes errors in simulation which revealed this incorrect
double initialization in test scenarios with minimal firmware
configurations.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adds initial SoC-level support for the Microchip
PIC32CM JH series, including SoC definition files.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add stm32l083xx SoC variants that are similar to stm32l073xx with an added
AES accelerator.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.
Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add I2C_TARGET_ALLOW_POWER_SAVING config. Enable this config makes I2C
target device can enter Doze/Deep doze states while the bus is idle.
Ongoing transfers will block low-power entry until they are completed,
ensuring correct communication while still reducing overall power
consumption.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Ensure sw_isr_common, dynamic_isr, and init routines are executed from IRAM
by relocating libarch__common.a section.
Running these from flash prevents the board from booting properly, as flash
access is not available during early initialization.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add FPU power management for suspend to RAM procedures.
Add FPU save/restore procedures when `FPU_SHARING` feature
is disabled.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
- Add ``R_BSP_SecondaryCoreStart`` for the primary core to start
the secondary core
- Disable ``clock_init`` for the secondary core
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
