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soc: ite: ilm: it51xxx: Support RAM code size up to 4K

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Previously, the RAM code size was limited to 1K, causing issues when the
code exceeded this limit. This update modifies the implementation to
support RAM code sizes up to 4K

test: zephyrproject/zephyr/tests/drivers/flash/common --> pass

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2025-03-25 13:24:21 +08:00 • committed by Benjamin Cabé
commit f3ddb06028
5 changed files with 19 additions and 10 deletions
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2
soc/ite/ec/it51xxx/chip_chipregs.h
View file

@ -307,6 +307,8 @@ struct gctrl_it51xxx_regs {
#define IT51XXX_GCTRL_LRSIPGWR BIT(0)
/* 0x38: Special Control 9 */
#define IT51XXX_GCTRL_ALTIE BIT(4)
/* 0x47: Scratch SRAM0 Base Address */
#define IT51XXX_SEL_SRAM0_BASE_4K 0x04
/* 0x48: Scratch ROM 0 Size */
#define IT51XXX_GCTRL_SCRSIZE_4K 0x03

4
soc/ite/ec/it51xxx/ilm_wrapper.c
View file

@ -10,10 +10,6 @@
void __soc_ram_code custom_reset_instr_cache(void)
{
struct gctrl_it51xxx_regs *const gctrl_regs = GCTRL_IT51XXX_REGS_BASE;
/* I-Cache tag sram reset */
gctrl_regs->GCTRL_SCR0BAR = 0;
/* Make sure the I-Cache is reset */
__asm__ volatile("fence.i" ::: "memory");
}

2
soc/ite/ec/it51xxx/linker.ld
View file

@ -257,6 +257,8 @@ SECTIONS
/* Claim RAM for ILM mappings; must be 4k-aligned and each mapping is 4k in size */
SECTION_PROLOGUE(ilm_ram,(NOLOAD),ALIGN(0x1000))
{
/* On IT51XXX chip, scratch RAM must start at RAM_BASE+0x1000 */
. += 0x1000;
__ilm_ram_start = .;
. += __ilm_flash_end - __ilm_flash_start;
__ilm_ram_end = .;

7
soc/ite/ec/it51xxx/soc.c
View file

@ -102,11 +102,8 @@ void soc_prep_hook(void)
struct gpio_ite_ec_regs *const gpio_regs = GPIO_ITE_EC_REGS_BASE;
struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
/* Scratch ROM0 is 4kb size */
gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
/* Scratch ROM0 is 4kb size */
gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
/* Scratch SRAM0 uses the 4KB based form 0x801000h */
gctrl_regs->GCTRL_SCR0BAR = IT51XXX_SEL_SRAM0_BASE_4K;
/* bit4: wake up CPU if it is in low power mode and an interrupt is pending. */
gctrl_regs->GCTRL_SPCTRL9 |= IT51XXX_GCTRL_ALTIE;

14
soc/ite/ec/it8xxx2/ilm.c
View file

@ -80,8 +80,13 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
if ((uintptr_t)ram_addr < RAM_BASE) {
return -EFAULT; /* Not in RAM */
}
const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;
#ifdef CONFIG_SOC_IT51XXX
/* Since IT51XXX only supports one 4KB ILM block (SCAR0), set dirmap_index to 0 directly. */
const int dirmap_index = 0;
#else
const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;
#endif
if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) {
return -EFAULT; /* Past the end of RAM */
}
@ -101,8 +106,10 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
int irq_key = irq_lock();
#if !defined(CONFIG_SOC_IT51XXX)
/* Ensure scratch RAM for block data access is enabled */
scar->h = SCARH_ENABLE;
#endif
/* Copy block contents from flash into RAM */
memcpy(ram_addr, flash_addr, copy_sz);
/* Program SCAR */
@ -116,6 +123,11 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
}
scar->h = scarh_value;
#ifdef CONFIG_SOC_IT51XXX
struct gctrl_it51xxx_regs *const gctrl_regs = GCTRL_IT51XXX_REGS_BASE;
/* Scratch ROM0 is 4kb size */
gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
#endif
irq_unlock(irq_key);
return 0;
}