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soc: nordic: Disable cache for soft peripheral RAM region in nRF54H/nRF92

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Add an entry for the RAM region assigned to soft peripherals that will
disable caching for that region. Without this, communication with the
FLPR coprocessor cannot be performed correctly.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2025-04-04 14:58:21 +02:00 • committed by Benjamin Cabé
commit 4dded19ad7
1 changed files with 7 additions and 0 deletions
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7
soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
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@ -18,6 +18,9 @@
#define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \
DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can)
#define SOFTPERIPH_BASE DT_REG_ADDR(DT_NODELABEL(softperiph_ram))
#define SOFTPERIPH_SIZE DT_REG_SIZE(DT_NODELABEL(softperiph_ram))
static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
@ -40,6 +43,10 @@ static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE,
REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)),
#endif
#if DT_NODE_EXISTS(DT_NODELABEL(softperiph_ram))
MPU_REGION_ENTRY("SOFTPERIPH_RAM", SOFTPERIPH_BASE,
REGION_RAM_NOCACHE_ATTR(SOFTPERIPH_BASE, SOFTPERIPH_SIZE)),
#endif
};
const struct arm_mpu_config mpu_config = {