Add CPU PLL initialization, configuration, and clock gating for BL808.
The CPUPLL uses the same WAC PLL register layout as AUPLL, located at
CCI_BASE + 0x7D0 with CCI_CPUPLL_* field prefixes.
Config tables provide per-crystal analog parameters and SDMIN values
for the 480 MHz reference frequency. CPUPLL is the default root clock
source in bl808.dtsi at 320 MHz, with BCLK at 80 MHz. Boards can
override up to 480 MHz via DTS overlay.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add Audio PLL initialization, configuration, and clock gating to the
BL808 clock controller. The AUPLL uses the CCI register block at
offset 0x750 with the same WAC PLL layout as WIFIPLL.
Config tables provide per-crystal analog parameters and SDMIN values
targeting 442.368 MHz (48 kHz audio family). BFLB_MUL_CLK scales to
other frequencies such as 451.584 MHz for the 44.1 kHz family.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add support for the TI TMP451 remote and local temperature sensor.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Kurtis Dinelle <kurtisdinelle@gmail.com>
The pinmux controller for the aesc silicon platform is a simple
controller to mux differnt input outputs to one output option.
Since this is an internal controller, pull, drive strength and slew
rate are not implemented due missing IO pad features.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add out of band reset gpio pin in host platform.
Toggle this pin when about to reset Wi-Fi firmware from out of band.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
Add a driver for the WIZnet W6300 stand-alone Ethernet controller
with SPI interface. The driver operates in MACRAW mode using Socket 0
to send and receive raw Ethernet frames via Zephyr's Ethernet L2 layer.
PHY link state is monitored via the W6300 interrupt pin combined with
a periodic polling thread. The SPI protocol uses a 4-byte command
frame (instruction + address high + address low + dummy) for both
read and write operations, as required by the W6300 hardware.
Signed-off-by: Manjae Cho <manjae.cho@samsung.com>
Add initial support for nuvoton numaker m031x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
STM32F302xB/C/D/E devices have ADC1 and ADC2 as per RM0365.
Add missing ADC2 node to stm32f302Xc.dtsi only, stm32f302X8.dtsi
is not modified as x6/x8 variants have only ADC1.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
KSO16 and KSO17 may be used as GPIO function,
so the property can't be claimed "required: true".
Also, add the condition, if kso16/kso17 is used as kbs function,
then switch pin function to output temporarily before pin control
to kbs mode.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Add nxp,crc devicetree nodes for NXP SoCs that ship the standard
NXP CRC peripheral, and mark the CRC instance as the Zephyr CRC
device on the corresponding boards.
This extends the existing NXP CRC driver coverage without changing
the driver implementation.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add nxp,lpc-crc devicetree nodes for NXP SoCs that expose
MCUX_HW_IP_DriverType_MCO_CRC in the MCUX SDK, and mark the CRC
instance as the Zephyr CRC device on the corresponding boards.
This extends the existing LPC CRC driver coverage without changing
the driver implementation.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add SPI driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master and Slave operation modes
- Polling, Interrupt, and DMA transfer modes
- Transmit (TX) and Receive (RX) functionality
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add the `DT_NODELABEL_C_TOKEN` and
`DT_NODELABEL_C_TOKEN_BY_IDX` macros to retrieve
the C symbolic name of a node.
Signed-off-by: James Roy <rruuaanng@outlook.com>
Use the min/max properties instead of an enum for the st,csbound property
in multiple bindings files.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Replace the large enum containing all values from 104 up to 208 with
simpler min/max properties.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Remove the 'andestech,qspi-nor-xip' compatible string and unify both
flash_andes_qspi.c and flash_andes_qspi_xip.c flash drivers use
'andestech,qspi-nor' compatible string.
The driver selection is now handled via Kconfig logic.
CONFIG_FLASH_ANDES_QSPI_XIP is strickly depends on XIP is enabled and
the 'zephyr,flash' chosen node is compatible with 'andestech,qspi-nor'.
Since these two driver variants cannot coexist, the application is
responsible for enabling the appropriate driver Kconfig.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Add the pwm-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_pwm.c. The PWM channel period sets the audio
frequency and the duty cycle sets the perceived volume (50% is
loudest for piezos; the driver maps the linear 0..100% volume
percentage to a triangular 0..50% duty curve so 100% volume gives
maximum loudness).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add the gpio-buzzer compatible and the corresponding driver in
drivers/buzzer/buzzer_gpio.c. Active buzzers contain their own
oscillator and produce a fixed tone whenever they are powered.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Allow nxp,lpc-iocon to declare clocks and wire the RT7xx IOCON
nodes to the MCUX SYSCON clock controller in the common and CPU0
devicetree descriptions.
This lets the pinctrl driver request the correct gate for each
RT7xx IOCON instance through the common clock control path.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Allow nxp,kinetis-gpio to declare clocks and wire the RT7xx GPIO
nodes to the MCUX SYSCON clock controller in the CPU0 and CPU1
devicetree descriptions.
This lets the GPIO driver request the correct gate for each RT7xx
port through the common clock control path.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Added autanalog CTB support for PSE84 device.
This implementation uses the autnonomous controller (MFD)
that is shared with other autanalog drivers.
The CTB stands for Continuous Time Block. It is a set of opamps
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
Each CTB block contains two opamps, which need to be configured
together and accessed using the AC. A CTB MFD is used to bring
together the two opamp configurations. AC MFD then references the
combined CTB MFD configuration, and brings together all other
autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add missing SAI2 nodes in root DTSI for STM32H5 series. SAI2 is present
in the same devices as SAI1.
While at it, fix the default clock configuration of existing SAI1 nodes:
SAIn_SEL(0) corresponds to pll1_q_ck, not pll1_p_ck.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Fix the SoC DTSI file against flash size assigned to Zephyr that is
876kByte, not 808kByte.
Since commit d00f8505bf ("boards: nucleo_wb55rg: Update regarding
supported M0 BLE f/w"), Zephyr can use the first 876kB of the flash
memory. This commit updated nucleo_wb55rg board DTS file accordingly
but not the flash device 'reg' property and recently added 'ranges'
property uses a wrong value leading to access issues as for example
all storage tests on that board.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use LL_PWR_* APIs to handle UCPD_DBDIS flags in portable way.
Fix ucpd_params.psc_ucpdclk value.
Signed-off-by: Vladimir Zidar <vladimir.zidar@ars-es.com>
Nordic's nPM10 Series PMIC watchdog driver implementation and devicetree
bindings.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Move the inline comments of clocks enums to the related descriptions
so that they are visible in the generated online documentation.
Signed-off-by: Brenden Adamczak <cerebralasylum1@gmail.com>
Select CPU_HAS_DCACHE on ESP32-S2, S3 and C5 and auto-enable
CACHE_MANAGEMENT in each defconfig when ESP_SPIRAM is selected.
This activates the cache_esp32 driver where it is useful, so
portable sys_cache_data_* calls keep PSRAM and DMA buffers
coherent.
The L1 dcache line size is declared via the cpu@0 devicetree
node so the generic DCACHE_LINE_SIZE Kconfig default picks it
up automatically. SoCs without writeback cache (ESP32, C2, C3,
C6 and H2) are left untouched.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
