On Intel ADSP platforms startup of secondary cores must be deferred
till the IPC communication with the host driver. Previously this was
achieved through SMP_BOOT_DELAY option. Recently this option has been
removed. This change is aimed at maintaining legacy behavior by using
new, more granular dts approach.
Signed-off-by: Wojciech Jablonski <wojciech.jablonski@intel.com>
For all H5 SoCs, add the power node and the wake up pins.
Wake-up pins 1, 2, 4 and 5 are common for all H5 SoCs.
Pin 3 is available on H503 (PC1) and on H562 and higher (PI8).
Pin 6, 7 and 8 (respectively PC1, PD2 and PD3) are available on all SoCs
apart from H503.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On SoCs that route the DesignWare GPIO signals through a pin
controller, the pins must be muxed to their GPIO function before
the controller can drive them. Add an optional "default" pinctrl
state to the binding and apply it during initialization. Everything
is conditional on at least one enabled instance having a pinctrl-0
property, so existing users that do not describe pin muxing are
unaffected.
Signed-off-by: Aravind Krishnan <aravind.krishnan@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Generates periodic CNV trigger pulses at a configurable rate and duty
cycle to drive ADC conversions, exposed through the standard Zephyr PWM
API. Supports both v1 and v2 register layouts.
CONFIG_PWM_ADI_AXI_PWMGEN is auto-selected when
DT_HAS_ADI_AXI_PWMGEN_ENABLED.
Signed-off-by: Iustin Stolniceanu <iustin.stolniceanu@analog.com>
With the size of both memory banks on the dual core MCUs being derived
from the flash device node's respective size cell, there is no longer
any need for the bank2-flash-size property. Remove it from the relevant
dtsi files and deprecated it.
Signed-off-by: Vilhelm Engström <vilhelm.engstrom@tuta.io>
The IT51XXX SMBus controller does not support SMBALERT#.
To support this feature, a GPIO interrupt is configured through a
devicetree property and used as the SMBALERT# notification source.
When the GPIO interrupt is triggered, the driver performs the SMBus Alert
Response Address (ARA) procedure to identify and process the alerting
device.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The newly added PCA9530, PCA9531 and PCA9532 have a reset gpio pin. This
patch handles it, if set in device tree.
Signed-off-by: Juergen Werner <j.werner@aduart.de>
Splitting off the includable part for the NXP PCA953x led dimmer series
as further preparation for the implementation of other devices in this
series.
Signed-off-by: Juergen Werner <j.werner@aduart.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. The CH32V307 and CH32V317 have a
64 bin hash table and 4 MAC address entries.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. The EMAC of the M460 and M55M1
has a 64 bin hash table and 16 MAC address entries.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. The Cyclone V EMAC has a 256 bin
hash table and 128 MAC address entries, matching the Linux
devicetree.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet node. The XMC4xxx has a 64 bin hash
table and 4 MAC address entries.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. The EMAC of the MCXE31x and
S32K344 has a 64 bin hash table and 3 MAC address entries. The
ENET-QOS of the MCXA5x and MCXN94x has no hash table and only the
single MAC address entry holding the station address.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,perfect-filter-entries property to the ethernet nodes.
The EMAC of the ESP32 and ESP32-P4 does not implement the multicast
hash table, but has 8 MAC address entries besides the station
address.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. All series have a 64 bin hash
table and 4 MAC address entries.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties known from the Linux binding, to describe the multicast
filter capabilities of the MAC.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Remove the deprecated "owner-id", "perm-read", "perm-write",
"perm-execute", "perm-secure" and "non-secure-callable" properties from
the nordic,owned-memory binding, which nordic,owned-partitions inherits.
They were deprecated no later than Zephyr 4.2 in favour of the
"nordic,access" array of (owner-id, permission-flags) pairs.
All in-tree nordic,owned-memory nodes already use nordic,access. Nothing
in Zephyr consumes either form, so this needs Nordic platform maintainer
confirmation for the downstream UICR generation, and the migration guide
entry is the first written notice downstream gets.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Sleep durations below 1 ms can cause the CPU to HardFault or enter an
unrecoverable state. Increase the minimum standby residency to 2000 us
to mitigate this issue.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The light sleep path in soc/espressif/common/power.c requires the
rtc_timer (LP timer) counter device as its wakeup timer. Without the
node, light sleep is silently skipped at runtime.
Add the node disabled, matching the layout used by esp32c5/c6/h2;
users enable it and set wakeup-source via overlay.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Adding a new DMA driver for the PSE84 AXIDMAC hardware based on the
Infineon PDL driver. The AXIDMAC is a high performance DMA controller
that uses the AXI bus. It is typically used for large memory-to-memory
transactions.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
Add a sensor driver for the SoC die temperature on Raspberry Pi
BCM283x devices. The temperature is read through the VideoCore
firmware GET_TEMPERATURE property tag -- the source behind
`vcgencmd measure_temp` -- over the rpi_fw mailbox property
interface, and exposed as SENSOR_CHAN_DIE_TEMP.
The sensor owns no MMIO of its own, so it is modelled as a child of
the raspberrypi,bcm283x-firmware node.
Wire up the VideoCore mailbox (brcm,bcm2711-mbox) on the BCM2710, and
put the firmware (raspberrypi,bcm283x-firmware) node with its
shared-memory property buffer on the board, matching where rpi_4b
keeps them. Enable the sensor on the Zero 2 W and the Pi 4 B.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
Add DT Binding for the DAC inside the HPPASS CSG. Each instance
represents the DAC inside a single slice of the CSG.
Each DAC instance is a childe ofd the hppass CSG MFD node, and drivers
the negative input of the paired comparator. There is no external
output, but the DAC can be routed to an ADC for observation.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
The i2s binding marks unit as required, so any build enabling one
of the esp32p4 i2s nodes failed devicetree validation. Number the
three controllers and add the i2s_api loopback overlay for the
function ev board that surfaced it.
Declare i2s in the board yaml as well, otherwise twister filters
the suite out before the overlay is ever consulted.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a WS2812 LED strip driver on top of the pulse_io subsystem.
Pixel data is encoded as fixed-period cells with per-bit duty and
sent through a pulse_io transmit channel, so the driver runs on
any SoC with a pulse_io backend. Add a led_strip sample overlay
driving the on-board WS2812 of the esp32s3_devkitc through the
RMT backend, selected with the pulse_io file suffix.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the RMT peripheral node to ESP32, ESP32-S2, ESP32-S3,
ESP32-C3, ESP32-C5, ESP32-C6 and ESP32-H2 devicetrees, with a
pulse_io controller binding. Channels are selected through
pinctrl and consumers reference the controller with a single
channel cell. The ESP32-P4 node already exists and only gains
the pulse_io channel cells property.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a functional loopback backend that loops transmitted symbols
back on receive, with deferred async transmit completion and a
streaming receive path. Add ztest suites covering capabilities, the
channel lifecycle, configuration, codec encode/decode, sync and
async transfer, streaming receive, and the userspace syscall path.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the pulse_io subsystem API: the public header with the driver
vtable, capability and configuration structs, the SYMBOL and CELL
submission descriptors, sync and async transmit and receive entry
points, and the byte/symbol encoder and decoder helpers.
The channel lifecycle and transfer calls are exposed as syscalls
with userspace verification handlers. Includes the controller
binding, subsystem documentation, release note and maintainer entry.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The hardware default SDA hold time is only 1 clock cycle (~10ns),
which is often too short for slower I2C devices to properly sample
the data.
This commit sets the `i2c-sda-hold-time-ns` property to 300ns by
default to provide a sufficient hold margin and ensure reliable
data reception for these devices.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
The nrf54l has high speed pad ctrl (slew rate) of the fast GPIO port
(P2), configurable through registers sharing the address space of the
GPIO port.
Extend the nordic,nrf-gpio devicetree binding with a property
indicating if hspadctrl is available for a port, and add an optional
property for setting the optional HSBIAS value of the GPIOHSPADCTRL
BIAS register. The datasheet recommends always setting HSBIAS to its
highest value (3), which will now be set by the nrf gpio device
driver on init, unless the user specifies otherwise in the
devicetree.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add page-size to the JEDEC MSPI NOR property allow list and honor
it in FLASH_PAGE_SIZE_INST(): when the property is present, it
overrides the SFDP-derived or default page size.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We added a MSPI device binding for Microchip XEC MSPI driver using
the QMSPI controller. This binding is useful if we do not want to
use the Zephyr MSPI-NOR flash driver. It includes standard MSPI
device, JESD216, and custom QMSPI timing properties. The QMSPI
controller has a chip select timing register with four timing
fields and a TAP register for adjusting signal tap points when
QMSPI is used at maximum frequency (96 MHz). The tap points can
compensate for timing issues caused by board layout.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add an MSPI controller driver for Microchip MEC174x/5x/MEC165x
based on the QMSPI controller.
The driver uses the QMSPI local-DMA (LDMA) channels for the data path
when CONFIG_MSPI_MCHP_XEC_QMSPI_LDMA is enabled and the request
specifies a DMA-mode transfer; otherwise it uses the PIO FIFO. Note
the LDMA engine is internal to the QMSPI block and is independent of
the central DMA controller.
Both synchronous and asynchronous transfers are supported in PIO and
DMA modes. The driver operates in controller mode and supports
half-duplex transfers only; full-duplex is not implemented.
Initial PM_DEVICE support is added using the PM subsystem calls during
driver init, as recommended by the Zephyr PM_DEVICE documentation.
The driver supports the QMSPI hardware chip enables only; GPIO chip
enables are not supported. A controller configuration that specifies
GPIO CEs (num_ce_gpios != 0) is rejected with -ENOTSUP.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Remove the "prescaler" property from the nxp,lptmr binding. It was
deprecated in Zephyr 4.3 in favour of "prescale-glitch-filter" and
"prescale-glitch-filter-bypass", and has been functionally inert since
then: the driver never read it.
No in-tree lptmr node sets it. Note that it was "required: true" as
recently as v4.2.0, so out-of-tree board devicetrees are likely to still
carry it; this is the first written notice they get, hence the
migration guide entry.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Remove the seven "nxp,"-prefixed properties of the nxp,kinetis-acmp
binding, deprecated in Zephyr 4.0 in favour of the un-prefixed
enable-pin-out, use-unfiltered-output, enable-high-speed-mode,
filter-enable-sample, filter-count, filter-period and enable-window-mode
properties declared in the same binding.
The MCUX_ACMP_DT_INST_PROP()/_OR() compatibility shims in the sensor-class
driver existed only to fall back to the old names, so they collapse to
plain DT_INST_PROP()/DT_INST_PROP_OR() at the instance definition. The
comparator-class driver already used the new names only.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
This commit adds support for counter PM in MAX32657 SoC. It enables the
necessary PM configurations.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Add the FlexCAN-FD controller nodes (flexcan1, flexcan2, flexcan3)
to the i.MX952 SoC device tree so boards can enable CAN.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add the LPI2C controller nodes (lpi2c1 through lpi2c8) to the
i.MX952 SoC device tree so boards can enable I2C.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add the GPIO2 port pinmux settings to the i.MX952 SoC device tree so
the GPIO driver can select the GPIO mux options during configuration.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The SDHCI reference clock is generated by the Versal PMC clock
controller rather than supplied directly by a board.
Define its fixed-clock representation at the SoC level and connect both
SDHCI controllers.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add the SDIF node and attach its source clock: the main clock, divided to
stay within the controller's maximum source frequency. The divider follows
the cpu node's clock-frequency, as the rest of this file does.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Add support for the Fitipower EK79007 1024x600 MIPI-DSI panel.
The driver performs the vendor initialization sequence over DCS,
attaches to the host in video mode, and drives the reset and
backlight pins. Pixels are streamed by the display controller the
panel is wired to, so the driver reports the panel geometry and
handles blanking only.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the USB0 full-speed and USB1 high-speed IP3511 device-controller
nodes and the dedicated 8K USB SRAM region, bring up the USB PHYs and
device clocks in clock_init(), and link the USB stack's buffers into the
dedicated RAM (usb.ld) as the IP3511HS controller requires.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
