Add support for the Renesas RA Direct Memory Access Controller,
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA DMAC driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA DMAC
- Update module Kconfig to include the new driver
This enables DMA functionality on Renesas RA series MCUs.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Add stm32l083xx SoC variants that are similar to stm32l073xx with an added
AES accelerator.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.
Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add dts for stm32c051.
STM32C051 is just an STM32c071 w/o USB and different memory configuration.
Therefore STM32C091 can directly include STM32C051 and no longer needs
to delete the usb nodes.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add a UART driver for the VIRTIO console device.
This driver has support for both polling- and interrupt-based i/o,
as well as interacting with up to 32 console ports (disabled by
default). Based on the Xen HVC driver.
Tested with the console subsystem sample programs. Aside from
enabling CONFIG_PCIE, setting CONFIG_HEAP_MEM_POOL_SIZE to a
high enough value (for example 100000) is necessary -- as is done
in the virtiofs sample.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Add support for clock subsystem configuration and pinctrl in the
DesignWare I3C driver to enable proper clock control and pin
management on platforms that require them.
Changes include:
- Add clock_subsys field to dw_i3c_config structure.
- Update clock_control_get_rate() and clock_control_on() calls to use
the configured clock subsystem instead of NULL.
- Use COND_CODE_1 with DT_INST_PHA_HAS_CELL to conditionally extract
clock subsystem ID from devicetree, providing backward compatibility
for platforms without clkid cell.
- Include pinctrl-device.yaml in devicetree binding to enable pinctrl
support for platforms that need pin configuration.
- Gracefully fallback to NULL behavior when clkid is not specified.
This follows the same pattern used by other I3C drivers (mcux, renesas_ra)
and enables proper clock management for SoCs that require clock subsystem
identifiers while maintaining compatibility with existing devicetree
configurations.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
add range of cpu power states (run/sleep, stop and standby) for MSPM0
series. add exit latencies ranging from 1.5-15.7µs and minimum
residency times of 5-10ms for optimal power management transitions.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Extend vpr_launcher and device tree bindings to support configuring
the DMA secure attribute.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Use both cores for Zephyr by default. I did enable SMP, however forgot
to enable PSCI to turn on the other cores in the initial PR.
Tested with samples: `tests/arch/arm64/arm64_psci/` and
`samples/arch/smp/pi`
Requires [0].
[0]: https://github.com/zephyrproject-rtos/zephyr/pull/95325
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
* Changes driver naming to reflect hardware IP being used (TCPWM)
instead of referencing cat1. Cat1 is an internal infineon
reference which has little meaning to users and is being phased
phased out.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit introduces the FoBE Quill nRF52840 Mesh board configuration,
including device tree files, Kconfig settings, and necessary
documentation. It also adds GPIO header definitions
and updates vendor prefixes for proper identification.
Signed-off-by: Chiho Sin <chihosin@icloud.com>
Add support for supplying power to the flash chip by activation of
a GPIO specified through the "supply-gpios" property. Implementation
of gpio_reset() is also slightly modified so that it is consistent
with soft_reset() and the new power_supply() and so that all these
functions can use a common routine that performs a reset recovery
delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add implementation of the most common Soft Reset routine (sequence of
reset enable instruction 0x66 and reset instruction 0x99).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Use standard operation codes and parameters from SFDP for handling
the used flash commands (allow to override some of them through dts
with the `read-command`, `write-command`, and `rx-dummy` properties)
- Use all available erase types as specified by SFDP
- Allow using all IO modes
- Add support for switching to 4-byte addressing mode
- Use common functions for reading and writing of status registers
and for enabling write operations
- Switch IO mode (between the target one and Single IO) in a common
function that performs transfers and do it only when required for
a given command
- Make checking of JEDEC ID at initialization optional
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Get parameters for used flash commands and requirements for enabling
Quad and Octal modes from dts uint8-arrays containing data read from
SFDP tables for particular flash chips.
Also introduce `pre_init` quirk that allows alteration of the above
parameters or complementation of them in a specific way for particular
flash chip families.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The pipe nodes are not video interfaces. Describe them as normal child
nodes instead of using port/endpoint.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
After PR 79683, DTSI files were full of U-suffixed constants in the
clock configurations. This was copied verbatim in this file even
though the U prefix should not be used.
Remove the useless U suffixes in DT snippets of this binding.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
