Initial support Flash-LP driver for Renesas RA
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
*Separates AutAnalog and AutAnalog ADC in device tree.
*Makes AutAnalog SAR ADC a child of the AutAnalog system to reflect
hardware architecture.
*Adds binding file for AutAnalog SAR ADC driver.
Signed-off-by: John Batch <john.batch@infineon.com>
Add bindings for the power related modules. Use the bindings
Kconfig to pull in SDK drivers for cmc, spc, vbat and wuu.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This PR aligns all the bindings types for Nexus nodes.
Now all are the same as ./zephyr/dts/bindings/pwm/pwm-nexus.yaml
Signed-off-by: Kyle Bonnici <kyle.bonnici@nordicsemi.no>
Add device tree binding for HUB12 interface monochrome LED matrix
displays (32x16 pixels).
The HUB12 interface uses SPI for data transfer to shift registers,
with additional GPIO pins for row address selection (PA, PB),
output enable (PE), and data latching (PLAT).
Signed-off-by: Siratul Islam <sirat4757@gmail.com>
mcxw72 shared memory placement has been changed with MCUXSDK 25.09
update.
Moving the shared memory declaration to mcxw71 and mcxw72 specific dts
since the placement is now different.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
- Updated shield overlay file for RT1060 with sdio power and reset pins
- added device tree node in sdhc for sd reset pin
- added power gpio toggle logic
Signed-off-by: Abhinav Kulkarni <abhinav.kulkarni@nxp.com>
Add missing div-p division factor for pll clock and
respective tests in test/clock_control/stm32_clock_configuration
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The gpio pad groups are redundant if pin retention is handled per
pin, and the quirky cross domain feature is managed by the
application. Remove it entirely.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
All devices used in their "normal"/intended configuration do not
require management of the power domains, as the hardware itself will
request them automatically. Thus by default, don't specify the
power domains to avoid redundant resume/suspend cycles, which are
slow and require threading (IPC) making devices not isr ok.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Initial DMA support. DMA supports implementation of SSI IP but using vendor
specific DMA in the wrapper. The setup of the DMA is done in
mspi_dw_vendor_specific.h.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
MSPI slave mode is selected through devicetree using the
op-mode property. Mode selected by SSIISMST bit in the
CTRLR0 register. EXMIF can only be Master (controller).
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
enum mspi_op_mode in mspi.h has different syntax to this binding.
Aligning these will allow for cleaner code in the implmented drivers.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The nrf-qspi-v2 peripheral is similar to EXMIF on nrf54h20
but supports DMA and slave-mode. The wrapper around
the SSI IP is also different with DMA features.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Add property for selecting the source for GMAC Reference Clock to dts
bindings yaml file.
Choose the source for the GMAC Reference Clock by GMAC_UR register.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add Himax HM01B0 camera sensor driver.
It depends on I2C and it is required to configure the camera.
Signed-off-by: Antonino Scarpaci <antonino.scarpaci@gmail.com>
Add device tree binding for TitanMicro TM1637 7-segment LED
display controller. The TM1637 uses a GPIO bit-banging protocol
with clock and data pins.
Properties:
- clk-gpios: Clock GPIO pin
- dio-gpios: Data I/O GPIO pin
- bit-delay-us: Bit delay for GPIO protocol timing
Signed-off-by: Siratul Islam <sirat4757@gmail.com>
- Add support Renesas r7ka8d2kflcac SoC.
- Move sdram-controller node from r7ka8p1kflcac.dtsi to ra8x2.dtsi
since this device node is available for all RA8x2 SoCs
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Fix the GPIO port "ngpios" for RA8x2 series SoCs to match
the values specified in the Hardware User’s Manual (HUM).
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
- add driver for Vishay VEML6046 RGBIR color sensor
- add new compatible "vishay,veml6046"
- support fetch and get sensor subsystem operations
- triggered mode and interrupts are not yet supported
Signed-off-by: Andreas Klinger <ak@it-klinger.de>
- Removal of double enum (by me) caused wrong later enum entries
- See commit 36abe5efecbc27963189880d7c426c50760bcd58
- Added the second power down state (but with different name)
-> This restores the old function but still fixes the double enum issue
- The second power down state equals a different valid value
in the mode register. Documentation does not state if they
are equal but it is likely that they only differ in readback value.
-> With this change all possible register values are mapped
-> The power down state values are 0b000 and 0b100
Signed-off-by: Martin Koehler <koehler@metratec.com>
One-shot reads through Read-Decode API matches functionality
from Fetch-Get API, but asynchronously.
Streaming mode supporting FIFO Watermark Interrupts. Works for both
Gyro and Accel drivers.
These changes are covered under the build-all test for sensor async
api.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
