soc: ti: k3: add AM2434 support
Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5 and M4 cores are supported here. Signed-off-by: Amneesh Singh <a-singh7@ti.com>
This commit is contained in:
Amneesh Singh
Daniel DeGrasse
parent
9814590eb3
commit
c7a21c3da5
10 changed files with 666 additions and 73 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2024 PHYTEC Messtechnik GmbH
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* Copyright (c) 2025 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,9 +8,9 @@
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include "am64x_main.dtsi"
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#include "am64x_mcu.dtsi"
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/ {
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@ -29,9 +30,9 @@
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reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */
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};
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sram1: memory1@40000 {
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sram1: memory1@30000 {
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compatible = "mmio-sram";
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reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */
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reg = <0x30000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */
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};
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sysclk: system-clock {
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@ -39,72 +40,6 @@
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clock-frequency = <DT_FREQ_M(400)>;
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#clock-cells = <0>;
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};
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mbox6: mailbox@29060000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29060000 0x200>;
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interrupts = <56 4>;
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interrupt-parent = <&nvic>;
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usr-id = <3>;
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#mbox-cells = <1>;
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};
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pinctrl: pinctrl@4084000 {
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compatible = "ti,k3-pinctrl";
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reg = <0x04084000 0x88>;
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status = "okay";
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};
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uart0: serial@4a00000 {
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compatible = "ns16550";
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reg = <0x04a00000 0x200>;
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interrupts = <24 4>;
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interrupt-parent = <&nvic>;
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clock-frequency = <DT_FREQ_M(96)>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@4a10000 {
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compatible = "ns16550";
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reg = <0x04a10000 0x200>;
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interrupts = <25 4>;
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interrupt-parent = <&nvic>;
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clock-frequency = <DT_FREQ_M(96)>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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i2c0: i2c@4900000 {
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compatible = "ti,omap-i2c";
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reg = <0x04900000 0x100>;
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interrupts = <17 4>;
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interrupt-parent = <&nvic>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@4910000 {
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compatible = "ti,omap-i2c";
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reg = <0x04910000 0x100>;
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interrupts = <18 4>;
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interrupt-parent = <&nvic>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpio0: gpio@4201000 {
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compatible = "ti,davinci-gpio";
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reg = <0x4201000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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status = "disabled";
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};
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};
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&nvic {
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@ -114,3 +49,33 @@
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&systick {
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status = "okay";
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};
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&mcu_uart0 {
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interrupts = <24 4>;
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interrupt-parent = <&nvic>;
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};
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&mcu_uart1 {
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interrupts = <25 4>;
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interrupt-parent = <&nvic>;
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};
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&mcu_i2c0 {
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interrupts = <17 4>;
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interrupt-parent = <&nvic>;
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};
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&mcu_i2c1 {
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interrupts = <18 4>;
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interrupt-parent = <&nvic>;
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};
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&mbox6 {
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interrupts = <56 4>;
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interrupt-parent = <&nvic>;
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};
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&mbox7 {
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interrupts = <57 4>;
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interrupt-parent = <&nvic>;
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};
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271
dts/arm/ti/am64x_main.dtsi
Normal file
271
dts/arm/ti/am64x_main.dtsi
Normal file
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@ -0,0 +1,271 @@
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/*
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* Copyright (c) 2025 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl: pinctrl@f4000 {
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compatible = "ti,k3-pinctrl";
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reg = <0xf4000 0x2ac>;
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status = "disabled";
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};
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timer0: timer@2400000 {
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compatible = "ti,am654-timer";
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reg = <0x2400000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer1: timer@2410000 {
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compatible = "ti,am654-timer";
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reg = <0x2410000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer2: timer@2420000 {
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compatible = "ti,am654-timer";
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reg = <0x2420000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer3: timer@2430000 {
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compatible = "ti,am654-timer";
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reg = <0x2430000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer4: timer@2440000 {
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compatible = "ti,am654-timer";
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reg = <0x2440000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer5: timer@2450000 {
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compatible = "ti,am654-timer";
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reg = <0x2450000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer6: timer@2460000 {
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compatible = "ti,am654-timer";
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reg = <0x2460000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer7: timer@2470000 {
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compatible = "ti,am654-timer";
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reg = <0x2470000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer8: timer@2480000 {
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compatible = "ti,am654-timer";
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reg = <0x2480000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer9: timer@2490000 {
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compatible = "ti,am654-timer";
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reg = <0x2490000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer10: timer@24a0000 {
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compatible = "ti,am654-timer";
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reg = <0x24a0000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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timer11: timer@24b0000 {
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compatible = "ti,am654-timer";
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reg = <0x24b0000 DT_SIZE_K(1)>;
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status = "disabled";
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};
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uart0: uart@2800000 {
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compatible = "ns16550";
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reg = <0x02800000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: uart@2810000 {
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compatible = "ns16550";
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reg = <0x02810000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: uart@2820000 {
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compatible = "ns16550";
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reg = <0x02820000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: uart@2830000 {
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compatible = "ns16550";
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reg = <0x02830000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: uart@2840000 {
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compatible = "ns16550";
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reg = <0x02840000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart5: uart@2850000 {
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compatible = "ns16550";
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reg = <0x02850000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart6: uart@2860000 {
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compatible = "ns16550";
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reg = <0x02860000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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reg-shift = <2>;
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status = "disabled";
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};
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i2c0: i2c0@20000000 {
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compatible = "ti,omap-i2c";
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reg = <0x20000000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c0@20010000 {
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compatible = "ti,omap-i2c";
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reg = <0x20010000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c0@20020000 {
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compatible = "ti,omap-i2c";
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reg = <0x20020000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c0@20030000 {
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compatible = "ti,omap-i2c";
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reg = <0x20030000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gpio0: gpio@600000 {
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compatible = "ti,davinci-gpio";
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reg = <0x600000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@601000 {
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compatible = "ti,davinci-gpio";
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reg = <0x601000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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adc0: adc@28001000 {
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compatible = "ti,am335x-adc";
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reg = <0x28001000 DT_SIZE_K(1)>;
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status = "disabled";
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#io-channel-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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/* users: r5f0_0, r5f0_1, r5f1_0, r5f1_1 */
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mbox0: mailbox@29000000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29000000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f0_0, r5f0_1, r5f1_0, r5f1_1 */
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mbox1: mailbox@29010000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29010000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f0_0, r5f0_1, a53 */
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mbox2: mailbox@29020000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29020000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f0_0, r5f0_1, a53 */
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mbox3: mailbox@29030000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29030000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f1_0, r5f1_1, a53 */
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mbox4: mailbox@29040000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29040000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f1_0, r5f1_1, a53 */
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mbox5: mailbox@29050000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29050000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f0_0, r5f0_1, a53, m4 */
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mbox6: mailbox@29060000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29060000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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/* users: r5f1_0, r5f1_1, a53, m4 */
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mbox7: mailbox@29070000 {
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compatible = "ti,omap-mailbox";
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reg = <0x29070000 0x200>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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};
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63
dts/arm/ti/am64x_mcu.dtsi
Normal file
63
dts/arm/ti/am64x_mcu.dtsi
Normal file
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@ -0,0 +1,63 @@
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/*
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* Copyright (c) 2025 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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mcu_pinctrl: pinctrl@4084000 {
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compatible = "ti,k3-pinctrl";
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reg = <0x04084000 0x88>;
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status = "disabled";
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};
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mcu_uart0: serial@4a00000 {
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compatible = "ns16550";
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reg = <0x04a00000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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mcu_uart1: serial@4a10000 {
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compatible = "ns16550";
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reg = <0x04a10000 0x200>;
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clock-frequency = <DT_FREQ_M(48)>;
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current-speed = <115200>;
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reg-shift = <2>;
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status = "disabled";
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};
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mcu_i2c0: i2c0@4900000 {
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compatible = "ti,omap-i2c";
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reg = <0x4900000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mcu_i2c1: i2c0@4910000 {
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compatible = "ti,omap-i2c";
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reg = <0x4910000 0x100>;
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clock-frequency = <DT_FREQ_K(100)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mcu_gpio0: gpio@4201000 {
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compatible = "ti,davinci-gpio";
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reg = <0x4201000 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <23>;
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status = "disabled";
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};
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};
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239
dts/arm/ti/am64x_r5.dtsi
Normal file
239
dts/arm/ti/am64x_r5.dtsi
Normal file
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@ -0,0 +1,239 @@
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/*
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* Copyright (c) 2025 Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
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#include "am64x_main.dtsi"
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#include "am64x_mcu.dtsi"
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||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-r5";
|
||||
reg = <0>;
|
||||
clock-frequency = <DT_FREQ_M(800)>;
|
||||
};
|
||||
};
|
||||
|
||||
atcm: memory@0 {
|
||||
device_type = "memory";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x0 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "ATCM";
|
||||
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
|
||||
};
|
||||
|
||||
btcm: memory@41010000 {
|
||||
device_type = "memory";
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x41010000 DT_SIZE_K(32)>;
|
||||
zephyr,memory-region = "BTCM";
|
||||
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
|
||||
};
|
||||
|
||||
sram: memory@70080000 {
|
||||
compatible = "zephyr,memory-region", "mmio-sram";
|
||||
reg = <0x70080000 DT_SIZE_K(256)>;
|
||||
zephyr,memory-region = "SRAM";
|
||||
};
|
||||
|
||||
vim: interrupt-controller@2fff0000 {
|
||||
#address-cells = <1>;
|
||||
compatible = "ti,vim";
|
||||
reg = <0x2fff0000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
|
||||
};
|
||||
};
|
||||
|
||||
&timer0 {
|
||||
interrupts = <0 152 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer1 {
|
||||
interrupts = <0 153 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer2 {
|
||||
interrupts = <0 154 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer3 {
|
||||
interrupts = <0 155 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer4 {
|
||||
interrupts = <0 156 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer5 {
|
||||
interrupts = <0 157 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer6 {
|
||||
interrupts = <0 158 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer7 {
|
||||
interrupts = <0 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer8 {
|
||||
interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer9 {
|
||||
interrupts = <0 161 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer10 {
|
||||
interrupts = <0 162 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&timer11 {
|
||||
interrupts = <0 163 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
interrupts = <0 210 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
interrupts = <0 211 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
interrupts = <0 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
interrupts = <0 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
interrupts = <0 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
interrupts = <0 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
interrupts = <0 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
interrupts = <0 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
interrupts = <0 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
interrupts = <0 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
interrupts = <0 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mcu_uart0 {
|
||||
interrupts = <0 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mcu_uart1 {
|
||||
interrupts = <0 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mcu_i2c0 {
|
||||
interrupts = <0 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mcu_i2c1 {
|
||||
interrupts = <0 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&adc0 {
|
||||
interrupts = <0 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox0 {
|
||||
interrupts = <0 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox1 {
|
||||
interrupts = <0 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox2 {
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox3 {
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox4 {
|
||||
interrupts = <0 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox5 {
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox6 {
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
||||
&mbox7 {
|
||||
interrupts = <0 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
|
||||
interrupt-parent = <&vim>;
|
||||
};
|
||||
|
|
@ -21,6 +21,7 @@ elseif(CONFIG_SOC_SERIES_AM6X_M4)
|
|||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "")
|
||||
elseif(CONFIG_SOC_SERIES_AM6X_R5)
|
||||
zephyr_sources(r5/soc.c)
|
||||
zephyr_sources_ifdef(CONFIG_ARM_MPU r5/arm_mpu_regions.c)
|
||||
|
||||
zephyr_include_directories(r5)
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ config SOC_SERIES_AM6X_R5
|
|||
select SOC_EARLY_INIT_HOOK
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "AM2434" if SOC_AM2434_M4 || SOC_AM2434_R5F0_0
|
||||
default "AM6232" if SOC_AM6232_A53
|
||||
default "AM6232" if SOC_AM6232_M4
|
||||
default "AM6234" if SOC_AM6234_A53
|
||||
|
|
|
|||
|
|
@ -43,6 +43,14 @@ config SOC_AM6442_M4
|
|||
bool
|
||||
select SOC_SERIES_AM6X_M4
|
||||
|
||||
config SOC_AM2434_M4
|
||||
bool
|
||||
select SOC_SERIES_AM6X_M4
|
||||
|
||||
config SOC_AM2434_R5F0_0
|
||||
bool
|
||||
select SOC_SERIES_AM6X_R5
|
||||
|
||||
config SOC_J721E_MAIN_R5F0_0
|
||||
bool
|
||||
select SOC_SERIES_AM6X_R5
|
||||
|
|
@ -59,6 +67,7 @@ config SOC_SERIES
|
|||
default "am6x" if SOC_SERIES_AM6X
|
||||
|
||||
config SOC
|
||||
default "am2434" if SOC_AM2434_M4 || SOC_AM2434_R5F0_0
|
||||
default "am6232" if SOC_AM6232_M4 || SOC_AM6232_A53
|
||||
default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
|
||||
default "am6442" if SOC_AM6442_M4
|
||||
|
|
|
|||
|
|
@ -17,19 +17,27 @@
|
|||
#define CTRL_PARTITION_SIZE (0x4000)
|
||||
#define CTRL_PARTITION(base, part) ((base) + (part) * CTRL_PARTITION_SIZE)
|
||||
|
||||
#if defined CONFIG_SOC_AM6442_M4
|
||||
#if defined CONFIG_SOC_AM6442_M4 || defined CONFIG_SOC_AM2434_M4
|
||||
#define MCU_PADCFG_BASE (0x4080000)
|
||||
#elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
|
||||
#define WKUP_PADCFG_BASE (0x4080000)
|
||||
#elif defined CONFIG_SOC_AM2434_R5F0_0
|
||||
#define MCU_PADCFG_BASE (0x4080000)
|
||||
#define MAIN_PADCFG_BASE (0xf0000)
|
||||
#endif
|
||||
|
||||
static const uintptr_t ctrl_partitions[] = {
|
||||
#if defined CONFIG_SOC_AM6442_M4
|
||||
#if defined CONFIG_SOC_AM6442_M4 || defined CONFIG_SOC_AM2434_M4
|
||||
CTRL_PARTITION(MCU_PADCFG_BASE, 0),
|
||||
CTRL_PARTITION(MCU_PADCFG_BASE, 1),
|
||||
#elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
|
||||
CTRL_PARTITION(WKUP_PADCFG_BASE, 0),
|
||||
CTRL_PARTITION(WKUP_PADCFG_BASE, 1),
|
||||
#elif defined CONFIG_SOC_AM2434_R5F0_0
|
||||
CTRL_PARTITION(MAIN_PADCFG_BASE, 0),
|
||||
CTRL_PARTITION(MAIN_PADCFG_BASE, 1),
|
||||
CTRL_PARTITION(MCU_PADCFG_BASE, 0),
|
||||
CTRL_PARTITION(MCU_PADCFG_BASE, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
|
|||
32
soc/ti/k3/am6x/r5/arm_mpu_regions.c
Normal file
32
soc/ti/k3/am6x/r5/arm_mpu_regions.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Texas Instruments
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/arch/arm/mpu/arm_mpu.h>
|
||||
|
||||
/* userspace threads require RO access to .text and .rodata */
|
||||
#ifdef CONFIG_USERSPACE
|
||||
#define PERM_Msk P_RW_U_RO_Msk
|
||||
#else
|
||||
#define PERM_Msk P_RW_U_NA_Msk
|
||||
#endif
|
||||
|
||||
static const struct arm_mpu_region mpu_regions[] = {
|
||||
#if defined CONFIG_SOC_AM2434_R5F0_0
|
||||
MPU_REGION_ENTRY("Device", 0x0, REGION_2G, {MPU_RASR_S_Msk | NOT_EXEC | PERM_Msk}),
|
||||
#endif
|
||||
|
||||
MPU_REGION_ENTRY(
|
||||
"SRAM", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE,
|
||||
{NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | PERM_Msk}),
|
||||
};
|
||||
|
||||
const struct arm_mpu_config mpu_config = {
|
||||
.num_regions = ARRAY_SIZE(mpu_regions),
|
||||
.mpu_regions = mpu_regions,
|
||||
};
|
||||
|
|
@ -14,6 +14,10 @@ family:
|
|||
- name: am6442
|
||||
cpuclusters:
|
||||
- name: m4
|
||||
- name: am2434
|
||||
cpuclusters:
|
||||
- name: m4
|
||||
- name: r5f0_0
|
||||
- name: j721e
|
||||
cpuclusters:
|
||||
- name: main_r5f0_0
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue