Commit graph

9459 commits

Author SHA1 Message Date
Felix Wang
193e9170bb drivers: Counter: FTM Support on Zephyr
1.Update dts bindings to move clock-source properties from
nxp,ftm-pwm.yaml to nxp,ftm.yaml.
2.Provide counter driver based on FTM driver from NXP mcux-sdk-ng

Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
2025-09-04 08:10:20 +02:00
Benjamin Cabé
a8b763fe3b doc: fix "buses" spelling
Plural of "bus" is "buses", not "busses".

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-09-03 17:04:13 +02:00
Jeremy Dick
ab7b60ca0f dts: arm: renesas: ra: Define vbatts pins on RA4 and RA6
Define the vbatts-pins for the RA4E1, RA4M1, RA4M2, RA4M3, RA4W1
RA6E1, RA6M1, RA6M2, RA6M3, RA6M4, and RA6M5

Signed-off-by: Jeremy Dick <jdick@pivotint.com>
2025-09-03 14:53:29 +03:00
Jamie McCrae
15744c2701 dts/boards: nordic: nrf5340: Split partition into s and ns versions
Splits up partition configuration for nrf5340-based cpuapp board
targets for secure and non-secure versions, the secure version now
has an extra 16KiB per slot which was previously wrongly reserved
for TF-M partitions which the secure board target does not use

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-09-03 11:02:52 +02:00
Tony Han
17981d2db9 dts: arm: atmel: refactor to use common parent nodes for sam ethernet
The ethernet mac and mdio share registers, refactor them to have common
parent nodes.

Signed-off-by: Tony Han <tony.han@microchip.com>
2025-09-03 08:56:44 +02:00
Benjamin Cabé
774271ad09 boards: infineon: increase boostrap size for cyw920829 soc
Fix CI issues whereby arch.arm.swap.common.no_optimizations test is
failing due to overlapping sections

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-09-02 19:19:40 -04:00
Benjamin Cabé
5b7bf2e68a include: drivers: rtc: counter: deprecate counter-based DS3231 driver
There is a "native" RTC driver for DS3231 now (maxim,ds3231-rtc, one of
the multiple functions implemented as MFD) so do all we can to
discourage the use of the legacy, counter-API based, driver.

Flag the compatible as deprecated.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-09-03 01:10:40 +02:00
Raffael Rostagno
1c0e877351 dts: esp32h2: Add peripherals
Add device tree entries for the following peripherals:

- ADC
- I2C
- I2S
- LEDC PWM
- MCPWM
- PCNT
- SPI
- DMA
- TWAI
- USB serial

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-09-02 21:41:09 +02:00
Liam Ogletree
97752191f4 drivers: flash: Add support for Atmel AT25 SPI flash variant
The AT25XV021A variant is a flash variant of Atmel's AT25 family
that adds extra protections, requiring additional writes to the
device to program or erase data.

This commit adds a flash driver for AT25XV021A devices instead of
modifying (1) the existing AT45 SPI flash driver or (2) the
existing AT24/25 EEPROM driver because this variant poses
fundamental changes that affect all aspects of the driver.

Notably,
 - AT25XV021A includes a second status register, and the format
	and functions of the existing status register is
	changed from the existing drivers.
 - AT25XV021A requires executing page or chip erase commands
	before writing, making it incompatible with the
	existing AT24/25 EEPROM driver.
 - AT25XV021A adds a software protection layer that requires
	extra writes before executing program or erase commands.

Tested writing to and erasing from an AT25XV021A device. Tested
reading from an AT25XV021A device across page boundaries. Tested
chip erase function. Tested driver initialization from varying
initial hardware states.

Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
2025-09-02 21:40:07 +02:00
Jordan Yates
611e14bd6d lora: lbm: enable SX126x RX boost option
Add the option to enable the RX boost mode in devicetree.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2025-09-02 18:41:44 +02:00
Luc BEAUFILS
f743822acc dts: arm: stm32mp2_m33.dtsi: add iwdg4 watchdog node
This is the independent watchdog for the non-secure world of M33 core.

Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
2025-09-02 15:53:41 +02:00
Luc BEAUFILS
dd86d70923 dts: arm: stm32mp2_m33: add wwdg1 node
Add the wwdg1 node, which is the wwdg for non-secure world.

Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
2025-09-02 15:53:41 +02:00
Tim Lin
d3d334c584 drivers/bbram: Enable bbram driver for it51xxx series
The BBRAM driver of it51xxx is compatible with it8xxx2.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-09-02 12:33:48 +02:00
cyliang tw
f33104e014 dts: arm: nuvoton: add support for m5531h2l
Add m5531h2l.dtsi to support chip m5531h2l of m55m1x SoC series.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-09-02 12:33:43 +02:00
Aksel Skauge Mellbye
962bdefd86 dts: arm: silabs: Add EM4 wakeup pins and power state
Add EM4 wakeup capable pin mapping to GPIO port node. Pins
capable of EM4 wakeup have dedicated interrupt flags.

Add EM4 as a soft-off power state that is disabled by default.
Marking it as disabled allows users to enter it with
`pm_state_force()`, while preventing the power management
subsystem from selecting the state automatically.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-09-02 11:10:33 +02:00
Tomasz Bursztyka
3d9fd26286 dts: mspm0g: Add timg 8/9/14 counter nodes for x51x series
TIMG8/9/14 added.

Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
2025-09-02 09:59:49 +02:00
Tomasz Bursztyka
5ca7ed3893 dts: mspm0g: Add timg 6/7/12 counter nodes
TIMG12 having a 32bits resolution

Signed-off-by: Dimitris Karnikis <dika@bang-olufsen.dk>
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
2025-09-02 09:59:49 +02:00
Tomasz Bursztyka
b81741519d dts: bindings: Fixing description of ti,msmpm0-pwm binding
Small typo.

Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
2025-09-02 09:59:49 +02:00
Tomasz Bursztyka
5e3f1611e1 dts: mspm0: Fix timer/counter/pwm names to enforce uniqueness
There are 14 TIMG and 2 TIMA, all which can be either a counter or a pwm,
so let's fix the names to avoid ambiguity and enforce uniqueness.

Rule applied here being:

tim<g/a><n>: tim<g/a><n>@<address> {
        ...

        counter<g/a><n>: counter<g/a><n> {
                ...
        };

        pwm<g/a><n>: pwm<g/a><n> {
                ...
        };
};

It will be much easier then once get the 16 timer nodes included.

Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
2025-09-02 09:59:49 +02:00
Erwan Gouriou
f0a585645d dts: arm: st: n6: Disable axisram3
Those memories should be disabled by default and enabled
at application level.

Incidentally, fix the way Kconfig symbol is enabled as
we should not parse status of ramcfg, but status of enabled
memory nodes.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-09-01 23:27:13 +02:00
Erwan Gouriou
7db506b8d0 dts: arm: st: n6: Add npu node and dts binding
Provide binding for `st,stm32-npu` compatible and node in SoC dtsi.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2025-09-01 23:27:13 +02:00
Immo Birnbaum
eff4ed0488 dts: arm: xilinx: zynqmp: remove sram0 declaration at SoC level
Remove the universal, unconditional declaration of the RAM area
at the SoC level, due to:

- the hardcoded base address 0 overlapping the exception vectors,
  the ATCM and the BTCM areas.
- the availability of the BTCM not being guaranteed unconditionally
  (config pin dependant)
- the possibility of having a 'black hole' between the ATCM and
  the BTCM depending on the operating mode of the R-cores cluster,
  which leads to a part of the text section being unavailable
- qemu not properly implementing the configuration-dependant
  behaviour of the ATCM and BTCM areas.

Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
2025-09-01 16:39:37 +02:00
Shontal Biton
799a3f9a4f soc: silabs: Add support for Silabs EFR32ZG28 SoC
Add support for Silicon Labs EFR32ZG28 SoC.

Signed-off-by: Shontal Biton <shontal1005@gmail.com>
2025-09-01 14:01:41 +02:00
Jun Lin
0d68cc39ac dts: npcx: re-arrange the default interrupt priority
Because the EC host command with SHI/SPI backend is timing sensitive, it
required the CPU to response the SHI interrrupt as soon as possible.
This commit re-arranges the default interrupt priority by:
1. keep the SHI's interrupt priority to 1.
2. Decrease the priority of the other peripherals by 1.
   (i.e. increase the priority `value` by 1)

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2025-09-01 07:44:23 -04:00
Emil Dahl Juhl
fddd6efb82 dts: arm: st: n6: correct sai1_a address
When compiling, the following warning occurs:

Warning (simple_bus_reg): /soc/sai1@452005804: simple-bus unit address
format error, expected "52005804"

Looking at table 3 in the reference manual[1] for the stm32n6 it seems that
the sai1_a address simply had a typo, where a "4" was added in front of the
correct address.

Fix the typo.

[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf

Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
2025-09-01 09:32:16 +02:00
Anisetti Avinash Krishna
e018a7e8dd drivers: pwm: Enable PWM support for PTL-h
Enable PWM support on PTL-h and add 64bit
address support for PWM driver.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2025-08-29 19:18:28 -04:00
Christian Rask
23157c10e5 drivers: display: ili9xxx: add tearing effect support
Add tearing effect support for better display synchronization. If
tearing effect is configured in the mipi_dbi device, the display
controller configures its tearing effect register.
Display orientation configuration is updated to also rotated the
direction of the display pixel vertical scanline, such that scan order
matches the display orientation.

Signed-off-by: Christian Rask <christianrask2@gmail.com>
2025-08-29 11:05:38 +02:00
Christian Rask
fe356031db drivers: mipi_dbi: spi: add tearing effect support
Add tearing effect support for better display synchronization. This
allows users to configure an external interrupt on falling/rising edges
of the gpio connected to the display controllers tearing effect pin.
See dt-bindings/mipi_dbi/mipi_dbi.h for details of how this works for
mipi_dbi display interfaces.

Signed-off-by: Christian Rask <christianrask2@gmail.com>
2025-08-29 11:05:38 +02:00
Duy Nguyen
84c2f87540 dts: renesas: rx: Change CPU compatible for RX dts
Change the compatible of CPU core for qemu_rx, rx130 and rx261
target accroding to the change of dt-binding for rx cpu core

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-08-29 09:00:50 +02:00
Quy Tran
8b4581ba1d arch: rx: Get swint register address from devicetree
Update irq_offload to get the swint register address from dts

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2025-08-29 09:00:50 +02:00
Duy Nguyen
8a0716de24 arch: rx: Add bindings for RX CPU core version
Adding bindings for rx cpu core version and remove the redundant
compatible in the qemu_rx and rsk_rx130 boards

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-08-29 09:00:50 +02:00
Aksel Skauge Mellbye
39e468b0f6 dts: arm: silabs: xg27: Fix wdog0 unit address
The wdog0 unit address and reg entry pointed to the secure
alias, while the SMU was configured to expect the non-secure
alias.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-08-28 00:40:04 +02:00
Aiden Hu
5d9353b1fa dts: arm: nxp: update nxp_rw6xx_common.dtsi for usb host.
Add usbh node.

Signed-off-by: Aiden Hu <weiwei.hu@nxp.com>
2025-08-27 16:35:52 +02:00
Qiang Zhang
55adebb51b dts: add KPP driver bindings.
add KPP driver bindings.

Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
2025-08-27 09:47:10 +02:00
Ephraim Westenberger
a7527b1bf7 soc: Add support for the bgm240sa22vna module
Silicon Labs controller with integrated radio each rely on a specific
binary blob (RAIL library) for using the EFR32 radio subsystem.
This commit adds support for the Silicon Labs BGM240SA22VNA SoC.

Signed-off-by: Ephraim Westenberger <ephraim.westenberger@gmail.com>
2025-08-26 23:49:37 +02:00
Raffael Rostagno
5bd4741c83 soc: esp32h2: Add initial support
Add initial support files for ESP32-H2 SoC.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-08-26 22:07:36 +02:00
Ioannis Damigos
4920a6d7b1 bluetooth: hci: Remove deprecated IPM HCI bus
Remove deprecated IPM HCI bus.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2025-08-26 04:07:10 +02:00
Ioannis Damigos
fe645cd346 dts/bindings/bluetooth: Use IPC instead of deprecated IPM
Use IPC in bt-hci-bus property instead of deprecated IPM.

Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
2025-08-26 04:07:10 +02:00
Alessandro Manganaro
8c11033f59 dts: arm: st: wba: temporary fix to build stm32wba5x boards
Due to a mismatch in naming of debug jtrst pin name
(compared to hal_stm32) all boards based on stm32wba5x
are not compiling.
This temporary fix will solve this issue until a systematic
approach will be put in place.

Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
2025-08-25 11:39:50 +02:00
Filip Stojanovic
034673bc89 dts: arm: st: add stm32h523Xe support
Provide support for STM32H523XE.

Signed-off-by: Filip Stojanovic <filipembedded@gmail.com>
2025-08-25 11:39:32 +02:00
Alen Karnil
4363d14bef dts: arm: st: stm32f303: fix I2C3 address in nodename
Correct stm32f303 I2C3 address in nodename.

Signed-off-by: Alen Karnil <alankarnil@gmail.com>
2025-08-25 09:12:23 +02:00
Camille BAUD
71be3c2823 dts: bflb: fix bad uart device address
4 didnt become a 2 like it should have

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-08-23 05:10:56 +02:00
Mario Paja
82ea32bd6e dts: st: use dma defines to describe sai dma configs
Use DMA defines to describe SAI DMA configuration.

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2025-08-22 14:50:47 +02:00
Mario Paja
3ef3de0d78 dts: st: n6: add SAI1 A/B & SAI2 A/B nodes
Add SAI1 & SAI2 nodes to STM32N6xx series

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2025-08-22 12:56:57 +02:00
Tanguy Raufflet
eb0f0530eb dts: arm: st: stm32mp2_m33.dtsi: add spi nodes
Add SPI nodes in non-secure context to dtsi.

Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
2025-08-22 12:35:56 +02:00
Taeyoun Park
7ccbd9f396 dts: arm: Add CAN1 and CAN2 nodes to stm32f207
Add CAN1 and CAN2 device tree nodes for STM32F207

Signed-off-by: Taeyoun Park <nvnv0422@gmail.com>
2025-08-22 12:35:50 +02:00
Yves Wang
d7b219cc34 dts: nxp: add ewm for mcxnx4x and ke1xz
Add ewm peripheral for nxp mcxnx4x and ke1xz.
Attach xtal32k to ewm for frdm_mcxn947.

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-08-22 09:45:18 +02:00
Yves Wang
201f70bfa9 drivers: watchdog: Make clock divider optional
Some SoCs did not provide ewm clock divider

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-08-22 09:45:18 +02:00
Declan Snyder
ee960a819e dts: nxp: rt7xx: Use DT spec recommended node names
Use node names as recommended by DT spec.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-08-22 06:52:51 +02:00
Zhaoxiang Jin
fa348d8e1b dts: bindings/regulator: Add new properties for nxp vref
1. Added new boolean type 'nxp,internal-voltage-regulator-en'
and 'nxp,chop-oscillator-en' properties for 'nxp,vref'.
The user can use these properties to improve the stability
and accuracy of the VREF output voltage.

2. Added properties 'nxp,current-compensation-en' and
'nxp,internal-voltage-regulator-en' and 'nxp,chop-oscillator-en'
for LPC55S3x, MCXN23x, MCXN94x, and MCXW7x VREF node.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
2025-08-22 06:52:21 +02:00