Add Devicetree binding for the NeoChrom GPU2D hardware accelerator.
This binding describes the required properties to enable GPU2D
support in Zephyr.
Signed-off-by: Radhika Changela <radhika.changela@siliconsignals.io>
There is no standard way to launch a secondary CPU out of its quiescent
state. While ARM Cortex-A cores use standardized secondary cpu launch
methods like PSCI or spin-tables, other multi-core SoC's (eg.
raspberrypi rp2350, nxp lpc55s69, etc) enable-methods are entirely
vendor-specific.
The devicetree specification section 3.8.1 describes the enable-method
property of a cpus/cpu* node. It may have the value "[vendor],[method]"
which describes the vendors-specific method by which a CPU is released
from a disabled state.
Remove enum from enable-method binding and update DT macros that relied
on enable-method being an enum type property.
Document the [vendor],[method] value in the enable-method property of
cpu.yaml.
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
Move dts parameters common to nrf7120 and nRF7120e into common file.
Add nrf7120e specific dts files.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Add the HCI driver that carries Bluetooth traffic over the
esp-hosted-mcu transport core, so Wi-Fi and Bluetooth share the
single link to the coprocessor. The driver asks the coprocessor
to initialise and enable its controller, then acts as a raw H4
bridge.
Received frames are copied into a slab slot on the shared receive
thread and rebuilt on a dedicated delivery thread, so waiting on
a host buffer pool cannot stall the Wi-Fi path. The framed
transport adds call depth on the tx processor thread, which runs
the driver send path, so its stack default is raised.
The coprocessor firmware advertises the controller to host flow
control commands but rejects them, so the binding sets the
no-flow-control quirk by default.
Extended advertising is left to the application. The coprocessor
is a separate part whose Bluetooth generation is not known when
the host is built: an esp32 provides Bluetooth 4.2 and has none,
while the riscv parts provide 5.0. Keep the legacy advertising
commands available so either generation works.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Some controllers advertise the controller to host flow control
commands in the supported commands mask but reject them, which
fails initialisation when host flow control is enabled. Add a
no-flow-control device tree quirk that makes the host skip the
flow control commands and treat the feature as not supported.
The quirk is a build time constant, so the unreachable flow
control paths are compiled out.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the Wi-Fi driver for an Espressif coprocessor running
esp-hosted-mcu firmware. The driver registers station and access point
interfaces with the network stack and carries their frames over the
esp-hosted-mcu transport core.
Management operations are driven over RPC against the coprocessor
esp_wifi API: scan, connect and disconnect, access point enable and
disable, mode and channel, power save, connected access point details
and station deauthentication. Connection results and station events
are reported asynchronously from the coprocessor event stream.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the transport core shared by the esp-hosted-mcu Wi-Fi and
Bluetooth drivers. The core owns the framing, the checksum, the
sequence counter and the RPC request and response matching, and it
demuxes received frames to the registered interface consumers.
Transports are pure byte movers behind a four function vtable, so the
protocol handling stays in one place. Both an sdio backend, driving
the coprocessor SLC register window, and a full duplex spi backend
with reset, handshake and data-ready lines are provided; the transport
is selected at build time from devicetree.
At init the core asks the coprocessor for its firmware version and
logs it, falling back to the version carried in the boot event when
the firmware is too old to answer. The expected version is only a
Kconfig declaration: the firmware is flashed to a separate chip, so
a mismatch is warned about and never fails init.
The boot event also carries the SDIO datapath mode. When the
coprocessor aggregates frames it pads each one to a four-byte
boundary, so the receive walk reads the advertised mode and steps by
the aligned stride; a byte-tight coprocessor is unaffected.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add board, SoC, and devicetree support for ElemRV-H, an open-source
RISC-V microcontroller built on the Hydrogen platform.
The Hydrogen SoC integrates a VexiiRiscv core (RV32I_Zicsr_Zifencei)
clocked at 50 MHz with UART, GPIO, and pin multiplexer peripherals.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add a driver for the Aesc Silicon SPI XIP controller, exposing the
execute-in-place mapped SPI NOR flash as a Zephyr flash device. The
flash region is a soc-nv-flash child of the "aesc,spi-flash-controller"
node.
Reads are served from the memory-mapped XIP window. Programming is not
supported yet, so write() and erase() return -ENOSYS.
When the "aesc,quad-mode" property is set, the driver switches the
controller and flash to quad read mode at init, skipping the
reconfigure when a bootloader already enabled it.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Microchip MEC5 SoCs use the same Synopsys DWC_mipi_i3c IP as other
supported platforms, wrapped with XEC-specific interrupt routing and
a HOST_CFG port-select register. Reuse the existing DW I3C driver by
adding a microchip,xec-i3c compatible and binding for MEC5 I3C nodes.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Assisted-by: Claude:claude-opus-5
Unlike STM32H503, STM32H52xx/H53xx and STM32H56xx/H7xx lines which have
one instance of the in-house `USB` IP with compatible `st,stm32-usb`,
the STM32H5E/F line is equipped with an instance of the OTG_FS IP.
Additionally, the STM32H5E5 and STM32H5F5 SoCs also have an instance of
the OTG_HS IP and a corresponding internal HS PHY.
Update the STM32H5E/F SoC DTSI to expose the proper USB nodes instead of
the `USB` nodes it inherited from inclusion of `stm32h5.dtsi`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The HSI48 generator on STM32H5 series supports trimming via CRS. Use the
compatible which corresponds to this hardware: `st,stm32-hsi48-clock`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a devicetree binding for the Microchip G1 SUPC (Supply
Controller) peripheral and instantiate the corresponding supc
node for the pic32cm_jh family.
The microchip,supc-g1 binding exposes standby-regulator-sel,
vref-on-demand, and vref-standby-mode properties to configure the
voltage regulator and voltage reference behavior in standby sleep
mode from devicetree. The supc node is added disabled by default,
to be enabled and configured per board.
Signed-off-by: Syed Maaz <Syed.Maaz@microchip.com>
Enable the on-board self-capacitive touch electrode E2 on
frdm_mcxa577 by wiring up the existing nxp,tsi-input driver,
following upstream commit that added TSI to the mcx_n9xx/n5xx boards.
Add a tsi0 node to the shared MCXA5x SoC devicetree (base offset
0xc3000, End-of-Scan / Out-of-Scan IRQs 124/125, MCUX_TSI_CLK),
disabled by default. On the board, add the TSI0_CH0 (P5_3) pinctrl
group, enable &tsi0 mapping E2 -> INPUT_KEY_A, set up the TSI clock
in board_early_init_hook (attach kFRO_HF_DIV_to_TSI0, divider 4),
and mark tsi as supported.
The clock_control mcux_syscon driver previously enabled only the
MCXN TSI gate (kCLOCK_Tsi). MCXA uses kCLOCK_GateTSI0, so make the
gate enable family-aware; without it the peripheral is unclocked and
the driver's init-time calibration faults the CPU before the console
comes up.
Tested on frdm_mcxa577 with samples/subsys/input/input_dump:
touching E2 emits INPUT_KEY_A press/release events.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Cortex-A53 SBC on the Broadcom BCM2710 (BCM2837 die). Adds the
soc/brcm/bcm2710 SoC with the native BCM283x interrupt controllers
(no GIC), booting single-core with the mini-UART console at 115200.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
Exposes the FPGA System ID build-info ROM (board / product / git
data) through the standard Zephyr OTP API as a read-only device.
otp_read() returns the raw ROM bytes; knowledge of the ROM format is
intentionally left to the consumer.
CONFIG_OTP_ADI_AXI_SYSID is auto-selected when
DT_HAS_ADI_AXI_SYSID_ENABLED.
Signed-off-by: Iustin Stolniceanu <stolniceanuiustin@gmail.com>
The USBFS peripheral on Renesas RA6E2 has 5 pipes:
pipe 0 (control), pipes 4-5 (bulk) and pipes 6-7 (interrupt), with no
support for isochronous transfer. Set num-bidir-endpoints to 5 for
boards using this variant to correctly reflect the available pipe
configuration.
Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>
The renesas RA2A1 contains an usbfs peripheral with 5 endpoints.
For which the hal driver has now been upstreamed.
To make it work with the driver a usbfs and usbfs-phy dts node
had to be added to the soc dts.
The changes within this commit have been tested and confirmed
working on ek-ra2e1.
Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>
The USBFS peripheral on Renesas RA4E2 has 5 pipes:
pipe 0 (control), pipes 4-5 (bulk) and pipes 6-7 (interrupt), with no
support for isochronous transfer. Set num-bidir-endpoints to 5 for
boards using this variant to correctly reflect the available pipe
configuration.
Remove the /delete-node usbfs and usbfs-phy lines from the RA6E2
SoC DTS to allow use of the usbfs peripheral with the driver
proposed in zephyrproject-rtos/hal_renesas#208.
Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>
Add devicetree node for the MXCRYPTO crypto engine and
TRNG to the PSE84 SoC DTS includes. This node references the
new infineon,mxcrpto, infineon,mxcrypto-crypto, and
infineon,mxcrypto-trng bindings.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
- infineon,mxcrypto: mfd parent for crypto and trng nodes
- infineon,mxcrypto-crypto: main crypto engine
- infineon,mxcrypto-trng: true random number generator
These bindings describe the register base address and interrupt
configuration for the MXCRYPTO IP block found in several
Infineon SoCs, including PSE84
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Enable the RP2350 on-die temperature sensor at SoC level.
The RP2350A and RP2350B devicetrees provide their respective ADC
channels, so board-specific sample overlays are no longer needed.
Remove the redundant RP2350 die_temp_polling sample overlays.
Signed-off-by: Ara Gevorgyan <aragev@gmail.com>
Add the XBAR1 mux controller node and EQDC1-4 sensor nodes to the
RT118x SoC dtsi, all disabled by default. The EQDC instances share
a single combined IRQ per instance; interrupt-names = "index" is set
to satisfy the eqdc_mcux driver's DT_INST_IRQ_BY_NAME lookup.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add board support for the Quectel KG100S Radio Board (BRD4332A), featuring
the EFR32BG21B010F1024IM32 SoC and a Semtech SX1262 LoRa transceiver for
Sub-GHz operation.
Signed-off-by: Martin Moya <martin.moya@focus.uy>
Add DTS and Kconfig support for the Silicon Labs EFR32BG21 (Blue Gecko)
series, introducing the EFR32BG21B010F1024IM32 variant.
Temporarily point `hal_silabs` to `pull/183/head` to pull in the
required HAL support for this SoC.
Signed-off-by: Martin Moya <martin.moya@focus.uy>
Use the chosen zephyr,system-timer property to indicate which timer is used
as system timer and move the timer selection from the board to the SoC
itself.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Use the chosen zephyr,system-timer property to indicate which timer is used
as system timer and move the timer selection from the board to the SoC
itself.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Extend the TI BQ24295 battery charger driver to support additional
BQ2429x family devices.
Introduce variant-specific configuration to handle differences in
register fields and parameter ranges while maintaining a common driver
implementation across the supported devices.
Signed-off-by: Priyadharsan Saravanan <priyadharsan@sacrasys.com>
Create a driver implementation for the battery charge controller
TI BQ24295.
The driver supports enabling and disabling charging, configuring charge
current and charge voltage limits at initialization and runtime, and
setting input current regulation.
It also provides charger status and fault reporting through the Zephyr
charger API.
Signed-off-by: Priyadharsan Saravanan <priyadharsan@sacrasys.com>
nrf7120 cpu DTS node is missing of clock source causes it is not
referencing the clock-frequency attribute for SystemCoreClock variable.
The SystemCoreClock variable fallbacks to 16MHz causing clock scaling
issues for some timer tests.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Add the NXP LPC54628 (Cortex-M4F, 512 KB flash, 200 KB SRAM) as a second
SoC in the existing lpc54xxx series, alongside the LPC54114. The series
already provides the shared soc.h, linker script and IOCON pinctrl
header, so only the LPC54628-specific parts are added: the soc.yml and
Kconfig entries, the system PLL clock init in soc.c (clocked from the
external crystal, up to 220 MHz) selected by CONFIG_SOC_LPC54628 in
clock_init(), and the SoC devicetree with syscon/reset, IOCON pinctrl,
GPIO, PINT, GINT, the FLEXCOMM instances, the on-chip IAP flash, and the
two M_CAN instances. SystemInit is provided by the MCUXpresso SDK; the
LPC54628 has no startup assembly and runs it from soc_reset_hook.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
The TSTMR is a read-only timestamp counter, but its clock source is
SoC-specific: on some SoCs (e.g. i.MX RT118x) it is a read-only view of
the System Counter (SYS_CTR) and depends on it being enabled, while on
others (e.g. MCXW or i.MX8ULP) it is a standalone counter that free-runs
from reset and has no SYS_CTR dependency at all.
On i.MX RT118x, where the TSTMR is backed by the SYS_CTR, the driver
reported a hard-coded 1 MHz rate and never enabled the SYS_CTR, so
counter_get_value() returned a frozen or wrongly-scaled count and
tests/drivers/counter/counter_basic_api (test_valid_function_without_
alarm) failed. On RT118x the SYS_CTR (and thus the TSTMR) runs at a
fixed 24 MHz.
Gate the SYS_CTR handling behind a new hidden Kconfig,
COUNTER_MCUX_TSTMR_SYSCTR_BACKEND, selected automatically when the TSTMR
driver is built on a SoC that also has an nxp,sysctr node enabled. On
those SoCs the TSTMR shares the SYS_CTR hardware, so the driver drives
the SYS_CTR_CONTROL registers directly:
- start() sets the count-enable bit (CNTCR.EN) when the counter is off;
- get_freq() returns 0 while the SYS_CTR is disabled so callers can tell
the counter is not yet running;
- the register accesses are compiled out entirely on standalone TSTMR
SoCs (e.g. MCXW or i.MX8ULP), which free-run from reset and do not
depend on SYS_CTR.
In the CCM rev2 clock driver, the IMX_CCM_SYSCTR_BASE_CLK case now also
covers the TSTMR backend and reports the fixed 24 MHz rate, while
IMX_CCM_SYSCTR_SLOW_CLK returns -ENOTSUP for the TSTMR backend: the
SYS_CTR slow-clock path is unreliable for timestamp reads on
RT1180/RT1189, so surfacing the error at init time is safer than
silently producing inaccurate timestamps.
The counter_basic_api test now treats a reported frequency of 0 as
"cannot set a millisecond period", so a not-yet-running counter is
skipped rather than mis-evaluated.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The counter_basic_api test set run-mode = "free-run" on every GPT node
in its per-board overlays for the i.MX RT10xx, RT11xx and RT118x EVKs.
free-run is not board-specific: it is how the GPT counter is expected
to behave (compare events do not reset the counter), so repeating it in
each test overlay duplicated the same setting across many boards.
Move the property onto the GPT nodes in the NXP i.MX RT SoC devicetree
so it becomes the SoC-level default, and drop the now-redundant per-board
overrides from the counter test overlays. This also removes a duplicate
&gpt2 override in the RT1180 CM33 overlay.
The binding default stays "restart"; only these RT SoCs opt into
free-run. i.MX8M (arm64) GPT nodes are left unchanged.
Verified with west build -p always of tests/drivers/counter/
counter_basic_api on frdm_imxrt1186/mimxrt1186/cm33 and
mimxrt1170_evk/mimxrt1176/cm7; both build clean and the generated
devicetree shows run-mode sourced from the SoC dtsi.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
declare the erase-block-size property used by the flash_mspi_nor
driver to configure the address and size alignment required by
erase operations
Signed-off-by: Mohammad Odeh <zephyr@exalt.ps>
In Multi-LED mode, nothing prevents adding zeros between numbers in
the slot sequence. This is not recommended by the datasheet and can
actually render the translation map unusable because a shift appears
when reading the sensor FIFO data register. To prevent this, additional
build asserts have been added to check the slot sequence at compile time.
The default led-slot from bindings has been corrected: each type of
sensor will make all accessible LEDs available to the user by default.
Signed-off-by: Alban Chauvel <a.chauvel@catie.fr>
Enable on such boards
- lpcxpresso55s36 (LPC55S36)
- lpcxpresso55s59 (LPC55S6x)
- frdm_mcxn947 (MCXN947)
- frdm_rw612 (RW612)
- rd_rw612_bga (RW612)
For LPCXpresso55S69 board. The PowerQuad uses SRAM4 as private
working memory when enabled.
RT595 and RT685 can't be tested with the tests/subsys/dsp/basicmath/
because the source data is placed in flexspi Flash which can't
be accessed by PowerQuad.
Assisted-by: Claude Code:claude-opus-4-6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Add a DSP backend that offloads element-wise math operations to the
NXP PowerQuad hardware coprocessor found on LPC55S6x and similar SoCs.
Unsupported operations fall back to CMSIS-DSP software implementations.
Accelerated operations: add, sub, mult, scale, negate, and dot_prod
for f32, q31, and q15 types. The implementation uses PowerQuad's
matrix engine with three-tier chunking: full 16x16 blocks, partial
rows of 16, and a CMSIS-DSP tail for remainders under 16 elements.
The backend is enabled via Kconfig (DSP_BACKEND_POWERQUAD) and is
auto-selected when the nxp,lpc-powerquad devicetree node is present.
Assisted-by: Claude Code:claude-opus-4-6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Add a devicetree binding for the NXP LPC PowerQuad DSP coprocessor.
The binding requires reg and clocks properties, allowing the driver
to locate the peripheral and manage its clock through the clock
control subsystem.
Assisted-by: Claude Code:claude-opus-4-6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
The ST Zio connector extends the ARDUINO Uno V3 connectivity through four
female headers (CN7, CN8, CN9 and CN10) available on STM32 Nucleo-144
boards.
Add a generic "st-zio-header" GPIO nexus binding and the matching ST_ZIO_*
pin constants so boards can expose the Zio connector pins with convenient,
silkscreen-aligned names. This mirrors the existing st-morpho-header
binding.
Signed-off-by: Michele Vaccari <michele.vaccari@outlook.com>
Reassign IRQs so that none are of level 3. Modify peripheral mapping
through INPUTMUX and modify IRQ numbers in SoC's DT.
This is due to the fact that the default exception handling level
of the DSP (EXCM_LEVEL) is 2, thus L3 IRQs can't be masked during
critical sections.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Assisted-by: Claude:claude-opus-4.8
Reassign IRQs so that none are of level 3. Modify peripheral mapping
through INPUTMUX and modify IRQ numbers in SoC's DT.
This is due to the fact that the default exception handling level
of the DSP (EXCM_LEVEL) is 2, thus L3 IRQs can't be masked during
critical sections.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Assisted-by: Claude:claude-opus-4.8
By default, the UART RX FIFO is configured to trigger an interrupt
when it is half full. This end up breaking implementations that
assumed a per-byte interrupt delivery. These changes make these
properties adjustable in the DTS for RX and TX FIFOs.
Signed-off-by: Steven Macías <esmu@bang-olufsen.dk>
