Add the SMC devicetree binding and describe the SMC blocks needed by the
existing Kinetis K2x and KE1xZ SoCs.
Add the MCXC SMC and LLWU nodes, including the wakeup controller cell
information required for LLWU-based wakeup routing. The LLWU node is
disabled by default and must be explicitly enabled by a board or overlay.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
CS40L26/27 is a family of haptics drivers designed for mobile
applications.
This PR provides basic functionality for ROM features and serves
as a starting point for the upstream driver. Notably, RAM firmware,
SPI, and certain ROM features (e.g., GPIO triggers and custom PCM
and PWLE effects) are not supported.
Tested I2C and all included features with both device variants (A1
and B2), including ROM and buzz playback, calibration, and gain
configuration.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Update the Devicetree bindings documentation URL in
dts/binding-template.yaml to point to the correct path.
The original link pointed to a location that no longer
exists in the Zephyr documentation.
Fixes#108393
Signed-off-by: Bana Tawalbeh <banabilalt@gmail.com>
Support setting desiered SPI communication frequency via configuring
the SCLK_DIV divisior in IFTIM register.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
For mapped-partition and non-zero start address of flash node,
to adjust m5531 & m55m1 ranges to get correct mapping address.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Allow RISC-V machine timer nodes to describe their input clock frequency.
Some integrations use an mtimer clock that is independent of the CPU clock,
so the timer frequency needs to be described on the timer node itself
rather than derived from the CPU node.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add the System Counter (SYS_CTR) device tree node for the i.MX RT118x
SoC family. The node exposes the three register blocks (control, read,
compare) and the shared interrupt, with status set to disabled by
default.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add device tree binding for the NXP MCUXpresso System Counter
(SYS_CTR). SYS_CTR is a 56-bit free-running counter with three
separate register blocks (control, read, compare) and two compare
frames that share a single interrupt.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add DMA driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Memory to Memory transfer
- Peripheral to Memory transfer
- Memory to Peripheral transfer
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
In the stm32l4 family, the mcu with AES peripheral include
a new stm32l4_crypt.dtsi instead of repeating the same node
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Implement AUPLL management in the BL61x clock control driver,
following the same pattern as the existing WIFIPLL implementation.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add support for issuing a software reset sequence (RSTEN 0x66 followed
by RST 0x99) to the flash device during initialization, before reading
SFDP parameters.
The feature is controlled by a new devicetree property
'initial-soft-reset'. When enabled, the driver sends the reset
sequence using temporary LUT entries to avoid flash data
access during XIP critical sections.
An optional 't-reset-recovery' property specifies the minimum time in
nanoseconds the flash needs after reset before accepting new commands.
If provided, the driver will busy-wait(self defined) for the
specified duration.
Suggested-by: Sanjay Varghese <Varghesemela@gmail.com>
Link: https://github.com/zephyrproject-rtos/zephyr/pull/105891
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Replace the `no-disconnect` property with enum `zephyr,suspend-action`
which aims to be more flexible. The enumeration currently has three
values: two replicate the old behavior when `no-disconnect` was absent
and present (respectively `disconnect-with-pupd` and `none`) and the
third is introduced to tackle the issue below.
The core issue is that the current implementation of the input_gpio_keys
driver will forward GPIO_PULL_DOWN/GPIO_PULL_UP flags from Devicetree to
the GPIO driver when disabling the pin, which is not really sensible...
...but works anyways: most drivers seem to ignore these flags if pin is
configured as GPIO_DISCONNECTED! The correct interpretation per GPIO API
seems to be `pin in Hi-Z/"floating" state with PD/PU resistor enabled`
which is not supported by some hardware; compliant drivers should return
-ENOTSUP which would bubble up and prevent the input_gpio_keys device
from suspending. The new enumeration's third value, `full-disconnect`,
is designed for such controllers (although really, it should be used in
most if not all cases): when selected, the Devicetree PD/PU flags are
explicitly masked out when calling gpio_pin_configure(GPIO_DISCONNECTED)
which should then succeed on more hardware than currently. One effect is
that the GPIO pin should enter a Hi-Z/"floating" state without PD/PU but
this ought to be fine, as the input_gpio_keys driver does not read the
state of the GPIO line state while suspended (and reconfigures pin as
GPIO_INPUT during resume, which enables the PD/PU again if any).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
- Adds the common dtsi files based on memory configuration and pin
configuration
- Adds the gpio nodes in pic32cm_sg_gc series
- Adds the list of supported socs
Signed-off-by: Niyas Hameed <niyas.hameed@microchip.com>
Adds common and SoC-specific .dtsi files for the Microchip
PIC32CK GC family. These files define core peripherals,
address maps, and interrupt controller structure shared
across the PIC32CK GC variants.
Signed-off-by: Hariharan Arumugam <hariharan.arumugam@microchip.com>
Enable use of the WM8904 driver on platforms that do not provide
direct access to the MCLK signal. Introduce fs-ratio, which is used
to derive the MCLK value from the selected frame sync (FS) rate.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add Vddcore sensor to STM32H5 series. This allows monitoring
the core voltage. The sensor is connected internally to the ADC.
The exact channel depends on the specific STM32H5 variant.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add a binding for the Vddcore voltage sensor present on
certain STM32. The sensor is connected to a internal ADC
channel.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
In the stm32h5 family, the stm32H533/573 or stm32H5f4/f5 have AES
The stm32H562/563 do not.
This commit change the AES node definition for the mcu by
creating a h5_crypt dtsi file.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Convert ADC devicetree nodes to use MCHP_XEC_ECIA_GIRQ_ENC() and
MCHP_XEC_SCR_ENCODE() macros for GIRQ and PCR sleep clock register
encoding across MEC150x, MEC172x, and MEC175x SoC series.
Update the ADC binding to add pcr-scr property and channel-count
property for runtime channel configuration.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Provide Bluetooth LE support.
Change the ADC4 input channel to avoid a conflict with LED0.
Enable ADC4 and die_temp to have linklayer calibration based on the
temperature.
Add "bluetooth" term to supported features.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add the AES node in the board.dtsi file for STM32WBA52.
Inherit the AES node for STM32WBA55 and STM32WBA65.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add initial board support for the Trenz Electronic TE0950-02. The hardware
is based on an AMD Versal AI Edge and a AMD Artix 7. This Zephyr port runs
on the Versal device’s Real-Time Processing Unit (dual Arm Cortex-R5F).
This commit is the first in the series and only supports the basic devices
needed to run samples/hello_world and samples/philosophers. Specifically,
it adds the Cortex-R5F, UARTs, and the GIC interrupt controller.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
The default DTCM size is 64 KB which can be increased using
Option Bytes. In that case, the DTCM size will have to be
overwritten by an application overlay.
Signed-off-by: Gaétan Froissard <gaetan.froissard@marshmallow.kids>
The tsen (Thermal Sensor) and bt-hci (Bluetooth) nodes do not use standard
memory-mapped registers, so they do not have 'reg' properties. Because they
were placed inside the /soc node (which is a simple-bus), the Devicetree
compiler threw 'simple_bus_reg' warnings during compilation.
This commit moves these logical/blob-controlled nodes to the root level
to comply with Devicetree specifications and clear the compiler warnings
for all bflb family SoCs.
Fixes#108714
Signed-off-by: T Madhusudhan Rao <tetakalam@aerlync.com>
Use compatible which allows to set nfct-pins-as-gpios property
for nrf54l and nrf71 series.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Disable GPIO interrupts for the nRF54H20 FLPR core,
as it doesn't support GPIO interrupts by design.
Signed-off-by: Paweł Pelikan <pawel.pelikan@nordicsemi.no>
This adds STM32U5F7/STM32U5G7 which are basically U5F9/U5G9
respectively with LQFP100 packages without DSI.
Also adds missing STM32U5F9xJ DTS and updates Kconfig file.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Add a generic GPIO driver for a memory-mapped output latch register.
Include the driver implementation and devicetree binding.
Also add the required Kconfig and CMake integration.
Signed-off-by: Zhaoming Li <lizhaoming634@gmail.com>
Convert tachometer devicetree nodes to use MCHP_XEC_ECIA_GIRQ_ENC()
and MCHP_XEC_SCR_ENCODE() macros for GIRQ and PCR sleep clock
register encoding across MEC150x, MEC172x, and MEC175x SoC series.
Add tach0-3 nodes in mec5.dtsi with encoded girqs and pcr-scr,
following the MEC5 convention of omitting compatible at SoC level.
Update the tach binding to use pcr-scr encoded property and include
the GIRQ binding fragment.
Co-authored-by: Andy Chang <andy.chang@microchip.com>
Signed-off-by: Andy Chang <andy.chang@microchip.com>
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Convert PWM devicetree nodes to use MCHP_XEC_SCR_ENCODE() macro
for PCR sleep clock register encoding across MEC150x and MEC172x
SoC series.
Update the PWM binding to replace pcrs array with pcr-scr encoded
integer property.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
