- Moved PSE84 power states generic to the dts
rather that only supporting CM55 on the board
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Added PTComp support to PSE84.
This implementation uses the shared autonomous controller (MFD)
with other autanalog drivers.
The PTComp is a programmable threshold comparator inside the
autonomous (aut) analog subsystem. It is controlled using the
autonomous controller (AC), which is a programmable state machine.
The AC is shared across all autonomous analog peripherals including
the SAR, PRB, PTComp, CTB, and CTDAC.
The PTComp block contains two comparators for edge detection and
with a capability for boolean post-processing. These two comparator
instances need to be configured together and accessed using the AC.
A PTComp MFD is used to bring together the two comparator
configurations. AC MFD then references the combined PTComp MFD
configuration, and brings together all other autanalog peripherals
into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add DAC driver for the Analog Devices AD5529R 16-channel, 16-bit
voltage output DAC. The driver supports multiple output voltage
ranges, SPI communication, and optional reset/LDAC/clear GPIOs.
Signed-off-by: Robert Budai <robert.budai@analog.com>
Co-authored-by: Radu Ciobanu <raduciobanu096@gmail.com>
Replace the SDL display driver's default pixel format Kconfig
selection with a devicetree property and initialize the display
using the DT-provided format.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add `Trasna` to the list of vendor prefixes, which is already used
in-tree for the `lexi-r10` LTE modem.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Follow the pattern used by other PHY drivers and expose the
RTL8211F RGMII clock delay mode in devicetree.
Some MAC drivers, such as Renesas RA RMAC, can provide part of
the RGMII delay themselves. Boards then need a way to avoid
enabling the same delay in the PHY.
Keep the fallback at RX and TX delay enabled, matching the old
driver behavior for existing users.
Signed-off-by: Shan Pen <bricle031@gmail.com>
Reserve zb_settings & zb_secured in the Information Flash Region 0
(IFR0) node to the MCXW7x common devicetree include file.
These factory settings are accessed using nvmem to soc independant.
Signed-off-by: Guillaume Legoupil <guillaume.legoupil@nxp.com>
The IEEE 802.15.4 address is moved from flash hw_params_partition
to internal IFR0.
Abstraction layer is done by using CONFIG_NVMEM.
Signed-off-by: Guillaume Legoupil <guillaume.legoupil@nxp.com>
Add the Information Flash Region 0 (IFR0) node to the MCXW7x common
devicetree include file.
The IFR0 region is located at offset 0x2000000 with a size of 32KB.
This node uses the nxp,mcxw-ifr binding.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add CPU clock-frequency to the bcm2711 device tree and use it to
derive SYS_CLOCK_HW_CYCLES_PER_SEC instead of relying on a
hard-coded value.
Also enable cache management by default for the BCM2711 SoC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The firmware provides an interface between the ARM CPU and the
VideoCore GPU for system management and platform services on
Raspberry Pi devices. It allows the ARM to communicate with the
VideoCore firmware through mailbox property channels to perform
operations such as framebuffer allocation, display configuration,
clock and power management, thermal queries, memory configuration,
and other board-specific services.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add support for Broadcom VideoCore mailbox controller driver
for BCM2711 (Raspberry Pi 4). This driver exposes two mailbox
instances, mbox0 and mbox1, where mbox0 is used by the VideoCore
GPU to signal the ARM CPU, and mbox1 is used by the ARM CPU to
signal the VideoCore GPU.
Parts of the driver is based on Yoan Dumas pull request that was
https://github.com/zephyrproject-rtos/zephyr/pull/88501
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Signed-off-by: Yoan Dumas <yo_dumas@hotmail.fr>
Factorize aes node that is present on all WBAxx series with same resources
but the NVIC line that is 58 on WBA5xx and WBA6xx, and 52 on WBA2xx.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add the PMUC peripheral LDO regulators as a child 'regulators' node.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Signed-off-by: Zhengyu Yan <859361238@qq.com>
Rename PMUC compatible to be SF32LB52x specific.
Add devicetree bindings and dt-bindings
helpers for the SF32LB52x peripheral LDO regulators
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Signed-off-by: Zhengyu Yan <859361238@qq.com>
Describe the RT7xx LCDIF clock connection in devicetree and allow
both DCNano LCDIF bindings to carry a clocks property.
This wires the LCDIF node to the shared MCUX SYSCON clock control
provider so the drivers can request the gate directly.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Currently there are a handful of inconsistencies between DTS for SOCs
in this series. Adds a new common peripheral file with /delete-node/
used to remove inactive peripherals.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
This commit introduces a new clock control driver for NXP MCXW series
microcontrollers, replacing the previous hardcoded clock initialization
in soc.c with a devicetree-based approach.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Implementation of a DALI driver for mcus
that provide a PWM interface for zephyr.
The Zephyr specific PWM, counter, and gpio
nodes handle the work. Hence, the `zephyr`
vendor prefix is used for the binding.
The code is tested for the STM32F091 mcu and
for the nRF52840 mcu.
Signed-off-by: Sven Hädrich <sven.haedrich@sevenlab.de>
The streaming code previously hard-coded the INT pin as active-high
push-pull when writing INT_CONFIG. Add two boolean DT properties,
int-active-low and int-open-drain, and thread them through
bmp581_config so boards with active-low or open-drain INT wiring can
be supported without patching the driver.
Defaults preserve the previous hard-coded behavior (active-high,
push-pull) so existing in-tree boards do not need DT changes. Boards
with active-low INT wiring set int-active-low, which programs
BMP5_INT_POL_ACTIVE_LOW into INT_CONFIG. Note that the GPIO flags on
int-gpios must agree with the chip-side polarity setting.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The BMP581 driver previously only supported I2C. Add SPI and I3C
transports by extending the existing RTIO-based bus abstraction with
two new bus types (BMP581_BUS_TYPE_SPI, BMP581_BUS_TYPE_I3C),
following the pattern established by the icm45686 driver.
For SPI, the read register address is OR'd with bit 7 (BMP5_SPI_RD_MASK)
per the datasheet, and bmp581_init() performs the SPI activation dummy
read both before and after soft-reset (the device boots and reverts to
I2C/I3C mode on reset and requires a 16-SCK transaction with CSB
asserted to switch to SPI). For I3C, RTIO_IODEV_I3C_STOP/RESTART flags
are set on the read/write SQEs.
The BMP581_INIT macro now uses COND_CODE_1 to dispatch on the bus type
and instantiate the appropriate I2C/SPI/I3C iodev. Kconfig selects
I2C/SPI/I3C and the corresponding *_RTIO option conditionally based
on which buses the matching DT nodes use.
The original bosch,bmp581.yaml is split into a common binding plus
per-bus bindings (bosch,bmp581-i2c.yaml, bosch,bmp581-spi.yaml,
bosch,bmp581-i3c.yaml) that include the bus-specific yaml. Test nodes
for SPI and I3C are added to the build_all sensor test.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
On STM32N6, the USB-related clock mux is in front of USBPHYC rather than
OTGHS. Move the `clocks` cell related to mux configuration to the proper
node in SoC DTSI files.
While at it, change the default OTGPHYnCKREF_SEL(1) to OTGPHYn_SEL(3) as
the former macro cannot really be used for clock configuration with the
current implementation. Both the old and new configuration are equivalent
and select `hse_div2_osc_ck` as USBPHYC clock source. Also, update the
example DTS snippet in the binding file to use OTGPHYn_SEL().
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Lines ending with \ are not needed unless when used in #define.
This commit removes all cases of \ where this is not needed in
devicetree files.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
Linter not ensures that > and ] have no white spaces when these are
preceded with a block comment.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
The LEx10Q1 Telit family (LE910Q1 and LE310Q1) comprises ultra-compact
LTE Cat 1 bis modules designed for IoT and M2M applications, featuring
a full IP networking stack and are designed to support data‑centric
applications requiring reliable cellular connectivity, low power
consumption, and long product lifecycle.
The LE910Q1 and LE310Q1 share Telit’s unified xE910/xE310 form‑factor
concept, enabling pin‑to‑pin and footprint compatibility across
multiple Telit cellular modules, thereby simplifying hardware design
reuse and migration between form factors.
The binding identifies the UART device, the power GPIO and the reset
GPIO lines.
Signed-off-by: Luca Impagliazzo <Luca.Impagliazzo@telit.com>
Add missing #address-cells = <0> property to all IRQSTEER
interrupt-controller master nodes to eliminate devicetree warnings.
The devicetree compiler warns about missing #address-cells in
interrupt provider nodes across M33, M7_0 and M7_1 variants.
Adding #address-cells = <0> indicates that interrupt specifiers do
not contain address information, only interrupt number and flags.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add missing #address-cells = <0> property to all IRQSTEER
interrupt-controller master nodes to eliminate devicetree warnings.
The devicetree compiler warns about missing #address-cells in
interrupt provider nodes:
- irqsteer_master
- disp_irqsteer_master
Adding #address-cells = <0> indicates that interrupt specifiers do
not contain address information, only interrupt number and flags.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add support for IT8951 EPD controller, tested on reTerminal E1003
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Cursor:composer-2
All supported controllers (ILI9340/9341/9342C/9163C/9488) use
identical MADCTL register bit definitions. Hence the current separate
command sets CMD_SET_1/CMD_SET_2 is unnecessary. Remove it and
implement a single, datasheet-compliant orientation mapping for all
ILI9xxx controllers.
Replace rotation logic with the universal datasheet mappings:
- 0°: 0x00
- 90°: MV + MX
- 180°: MX + MY
- 270°: MV + MY
Add devicetree properties for panel-specific corrections:
- h-mirror/v-mirror: for mirroring variations
- bottom-top-refresh/right-left-refresh: for non-standard scan
directions
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/105521 and
https://github.com/zephyrproject-rtos/zephyr/issues/106489
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add a driver for the TM6605 haptic motor driver IC from Titan Micro
Electronics, found on the DFRobot DRI0056 Gravity module. The device is
a write-only I2C peripheral exposing 44 pre-programmed effects selected
through an effect register and triggered via a control register.
The driver implements the haptics subsystem start_output/stop_output
callbacks and adds a tm6605_select_effect() extension API to choose the
active effect at runtime. A devicetree binding is included.
Tested on Seeed XIAO nRF54L15.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Add power management support for MCXE24x SoC series with
four power states defined in device tree (runtime-idle and
three suspend-to-idle substates: STOP, PSTOP1, PSTOP2).
Implement pm_state_set() to handle state transitions using
the SMC (System Mode Controller) for STOP mode configuration.
When CONFIG_XIP=y, the WFI is executed from a __ramfunc so the
core does not fetch instructions from internal program flash
across the low power entry boundary.
Implement pm_state_exit_post_ops() to restore normal operation
after wakeup. No wake-up controller is required to wake the
core from these substates on this part.
Enable HAS_PM capability for the SoC series. Applications that
opt in to PM should also designate lptmr0 as the system timer
via the 'zephyr,system-timer' chosen property and enable the
node, so the LPTMR tickless driver keeps time across
STOP/PSTOPx without needing a SysTick + LPTMR companion-timer
arrangement.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
- Adds node in dts
- Updates the binding yaml of tcc driver with the supported tcc ip
version
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Found by dtc: "unit address and first address in 'reg' (0x46004000)
don't match for /soc/peripherals@40000000/rtc@6004000"
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The RTC hardware is compatible with the it82xx2 series, so it reuses
the same compatible and driver implementation.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add optional devicetree properties to configure SEDI I2C bus timing and
program those values during driver initialization.
Update the binding with standard, fast, fast-plus, and high-speed timing
properties so boards can provide bus-specific values from DTS instead of
relying only on built-in defaults.
Also update hal_intel revision in west.yml to get code for new changes in
the driver to work properly.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add a driver for the Diodes/Pericom PI4IOE5V6408 8-bit I2C-bus I/O
expander.
The chip provides eight independently configurable GPIO lines, each
with optional pull-up or pull-down resistor and an interrupt source
that fires on transitions away from a programmable default state.
Link: https://www.diodes.com/datasheet/download/PI4IOE5V6408.pdf
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
nxp_lpc11u6x interleave gpio0-2 in same base address
so fake the nit address as the base to avoid build
warning
fixes: #107642
Signed-off-by: Hake Huang <hake.huang@nxp.com>
- Add RTC node in am62-main.dtsi which can also be
used as a counter
- Add child counter_rtc node which can be used as a
virtual rtc.
- Add interrupts in am62x_a53.dtsi
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
When writes are issued to the mram controller without verifying that it
is ready, it can cause the reads to be stalled until all writes finish.
Fix this by adding a wait busy loop before each MRAM_WORD aligned write
and disable autopowerdown before starting the write.
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
Add devicetree API coverage for DT_(INST_)DESCENDANT_NUM_ON_BUS() and
DT_(INST_)DESCENDANT_NUM_ON_BUS_STATUS_OKAY().
The test topology validates that:
- devices nested below non-bus container nodes are still counted for the
parent controller bus
- child nodes that are bus controllers are counted for the parent bus
- devices behind child buses are excluded from the parent count
- status-okay filtering matches generated *_STATUS_OKAY macro values
Update overlay comments to document the expected counting behavior.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add a new DT binding for the MAX30102 (two LED channels: Red + IR;
no Green/LED3) and extract shared properties from both max30101 and
max30102 into a maxim,max3010x-common.yaml base binding to eliminate
duplication and simplify future MAX3010x variants.
Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
