Added Driver support for LTC4286 Hot-Swap Controller and Power Monitor.
Supports power telemetry and interrupt support to alert host device of
fault and warning events.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Move the ite,it8xxx2-pinctrl container node from the /soc node to the
root / node.
The pin-controller node is a logical container for pin configuration
states rather than a memory-mapped bus peripheral on the SoC bus. When
located inside /soc, DTC treats its children as addressable by the SoC
bus address/size cells, triggering avoid_unnecessary_addr_size
warnings/errors. Moving it to the root matches the convention used across
other SoC families in Zephyr (such as npcx and rp2040).
Assisted-by: Antigravity:gemini-1.5-pro
Signed-off-by: Jeremy Bettis <jbettis@google.com>
By default the autanalog and ctb nodes had status set
to okay for the pse84 boards. It makes more sense for
the default status to be disabled and for the specific
tests/samples to enable them as needed.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The mux subsystem rework converted the PWM and qdec INPUTMUX consumers
to mux-states and deleted the #inputmux-cells specifier space, but this
driver was left behind on inputmux-connections, so enabling capture now
fails at devicetree parse time (counter_capture on frdm_mcxa153).
Convert it the same way as pwm_mcux_ctimer: mux-states in the binding
and test overlay (same cells, renamed), a mux_state_apply() loop in the
driver with its error propagated out of init, select MUX in Kconfig,
and the missing Counter entry in the 4.5 migration guide.
Fixes#115616
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Describe I2S0 and its TX and RX DMA request slots in the common
MAX32690 devicetree. Select the EV kit pin routing and document the
onboard MAX9867 audio connections.
Signed-off-by: Shan Pen <bricle031@gmail.com>
Drop all properties related to wake-up pins from the `st,stm32-pwr`
binding as they have been migrated to `st,stm32-pwr-wkupctrl`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Migrate all existing STM32 wake-up pin DTSI implementations towards the
new `st,stm32-pwr-wkupctrl` binding. For compatibility, also update the
DTS of a few STM32C0-based boards, which have to define some of the
wake-up pins because the mapping is package-specific on this series,
as well as all overlays for `samples/boards/st/power_mgmt/blinky`.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add new bindings for the wake-up lines control logic integrated inside
the STM32 Power Controller (PWR). There is one main binding with most
of the properties, as well as two derivatives for a few series where
the available features differ from "the majority":
- st,stm32f1-pwr-wkupctrl for series where wake-up pins are forced into
input pull-down configuration, rising edge polarity whenever enabled
(no configurable polarity or pull-up/pull-down selection)
- st,stm32f7-pwr-wkupctrl for STM32F7 series on which it isn't possible
to enable the internal pull-up/pull-down resistors for wake-up pins
All other series share the same feature set covered by the main binding:
- configurable polarity: rising or falling edge detection
- configurable resistor: pull-up/pull-down/no-pull
Availability of some additional features is indicated by the presence of
vendor-specific properties declared in the main binding instead of using
dedicated bindings.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
For migration towards the new binding, allow the PWR nodes to get rid of
the #address-cells and #size-cells properties, which become unnecessary
as wake-up pin nodes are no longer direct children of the PWR node.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The Power Controller is memory-mapped so it should go inside /soc.
However, for some reason, the node was present in the root node instead
for STM32F1 and STM32F4 series.
Move the PWR node of these series inside /soc where it really belongs.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adds bindings for the Infineon HPPASS CSG comparator device. Each CSG
slice exposes an independent comparator with configurable inputs,
edge-detect trigger, and hardware output routing. The interrupts are
shared and handled by the parent MFD driver.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
xspim node use io-port-x properties to document mux configuration,
which would create a link in the dependency graph.
Thought, xspim should run before so this dependency should not be taken
into account.
Set dependency-mode as "ignore" for these props.
Note: "reverse" mode couldn't be used neither, it would be more adapted,
but in some case, dependency graph doesn't apply (flash_xspi_stm32.c case,
where the device node isn't the xspi controler, but the flash device)
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Describe all six ENETC Virtual Station Interfaces (enetc{0,1,2}_vsi{0,1})
on the i.MX95 M7 with their SI/port register windows, mac-index, si-index
and the shared NETCMIX block clock, all disabled by default.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Add a NETC Virtual Station Interface (VSI) driver and its binding so Zephyr
can drive an ENETC virtual function while a separate OS owns the PSI/PF.
The driver brings the SI up off the boot path in a service thread, gating
first access on the NETC clock and the PF's SR-IOV VF-enable bit so it
can't fault on a not-yet-decoding SI. It programs its own unicast MAC and
multicast-promiscuous mode through VSI->PSI messages.
Note: the current Zephyr NETC PSI driver implements neither SR-IOV nor
PSI<->VSI messaging, so only the Zephyr-VSI-to-Linux-PSI path is tested.
Rework the shared Tx datapath for throughput: coalesced Tx-completion
interrupts (frame-threshold + timer), a per-slot buffer ring so frames
aren't serialised on one buffer, and backpressure that blocks on a full
ring instead of dropping. PTP egress timestamps are read with a bounded
busy-wait.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
With the deprecation of fixed-partition, updated all mpns and board
to migrate to new binding mapped-partition.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
With the deprecation of fixed-partition, updated all mpns and board
to migrate to new binding mapped-partition.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Pull the Nordic Wi-Fi RF board parameters and the 6 GHz transmit power
ceiling bindings into the nRF7120 Wi-Fi binding, so a board can describe
the antenna fitted to it and the power it may transmit at the edges of
each band, across all three bands.
The DK is characterised with a net antenna gain of 0 dB in 2.4 GHz and
5 GHz. Its edge ceilings stay at the default of 31 dBm, which places no
restriction beyond the transmit power ceiling of the band, and its 6 GHz
values stay at the conservative binding defaults until the DK is
characterised.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-5
The Wi-Fi transmit power ceilings were set in the nRF7120 SoC dtsi,
which presents them as a property of the SoC. They are not. The silicon
ceilings live in the ICR region, and the devicetree value is the further
restriction the board imposes on top of them, so two boards built around
the same SoC need different values and a board had no obvious place to
override them.
Move them to the nRF7120 DK, the only board that enables the Wi-Fi node.
Boards that leave the node disabled are unaffected, as edtlib only
enforces required properties on nodes with status "okay".
The values are carried over unchanged, so behaviour on the DK is
preserved.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-5
Antenna gain and band edge ceilings describe the antenna fitted to a
board, the loss of the RF path to it, and the power the board may
transmit at the edges of each band to stay within the spectral emission
mask. All of them are per-board values and none is a property of the
SoC, so devicetree is the right home for them, next to the transmit
power ceilings that live there already.
Add an include-only binding holding them. Antenna gain is a signed net
figure, so a board whose RF path loses more than its antenna gains
states a negative value, and there is no separate PCB loss property.
Band edge ceilings are absolute limits in dBm and default to 31, which
places no restriction beyond the transmit power ceiling of the band.
The sub-band boundaries deliberately differ between the antenna gain and
the edge ceiling properties, and the 6 GHz band is split into six
sub-bands for antenna gain but only two, UNII-5 and UNII-6, for the edge
ceilings, so each property documents its own frequency range rather than
sharing one definition.
Add the 6 GHz transmit power ceilings as a separate include alongside
the existing 2.4 GHz and 5 GHz ones, so a tri-band part can pull them in
without affecting the dual-band parts.
The properties follow the layout of the Nordic Wi-Fi RF parameters and
so are vendor prefixed rather than presented as a cross-vendor
interface. The include is not tied to a single part: nRF70 keeps
equivalent values in Kconfig today and can be migrated onto it
separately.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-5
Eight of the nine transmit power ceiling properties were marked
'required'; wifi-max-tx-pwr-5g-high-mcs7 was not, which is a bug rather
than a decision. Requiring them also means a board cannot build until it
states a value for every rate and sub-band, with no way to say "use a
safe default" for a rate it has not characterised yet.
Drop 'required' and give each property a conservative default instead,
matching the values currently used for the Sheliak DK, so a board that
has not been characterised transmits too little rather than risking a
regulatory limit. These can be revisited once the DK is characterised.
This also scales better to parts with more sub-bands, where requiring
every property would oblige a dual-band board to describe a band it does
not operate.
No board changes behaviour: every board in tree sets all of the
properties that apply to it, so the defaults are not reached today.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-5
The flexcomm0..flexcomm3 nodes declared their two clocks as a single
phandle-array cell block:
clocks = <&clkctl1 MCUX_FLEXCOMMx_CLK &clkctl1 MCUX_FLEXCOMMx_LP_CLK>;
A phandle-array entry has a fixed shape <&phandle specifier...> where
the number of specifiers is fixed by the referenced node's #clock-cells.
Two phandle groups therefore cannot share one < > block; the combining
of < > groups is only valid for plain integer arrays. Each phandle plus
its specifier must be its own cell block.
Split the two clocks into separate cells so the property is a valid
phandle-array:
clocks = <&clkctl1 MCUX_FLEXCOMMx_CLK>, <&clkctl1 MCUX_FLEXCOMMx_LP_CLK>;
flexcomm14 has a single clock and is unchanged.
Signed-off-by: Allen Zhang <chunfeng.zhang@nxp.com>
Follow the family layout that already exists under soc/nxp/lpc/ and
move the LPC LPC84X family dtsi files (2 files) into a matching
lpc84x/ subdirectory. This keeps the dts layer aligned with the soc
layer.
Updated the board dts callers (lpc845brk) and any internal
cross-references. No functional change; the resulting devicetree is
byte-identical before and after this move.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Follow the family layout that already exists under soc/nxp/lpc/ and
move the LPC LPC55XXX family dtsi files (12 files) into a matching
lpc55xxx/ subdirectory. This keeps the dts layer aligned with the soc
layer.
Updated the board dts callers (lpcxpresso55s06 + 55s16 + 55s28 + 55s36 +
55s69) and any internal cross-references. No functional change; the
resulting devicetree is byte-identical before and after this move.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Follow the family layout that already exists under soc/nxp/lpc/ and
move the LPC LPC54XXX family dtsi files (3 files) into a matching
lpc54xxx/ subdirectory. This keeps the dts layer aligned with the soc
layer.
Updated the board dts callers (lpcxpresso54114 (m0 and m4)) and any
internal cross-references. No functional change; the resulting devicetree
is byte-identical before and after this move.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Follow the family layout that already exists under soc/nxp/lpc/ and
move the LPC LPC51U68 family dtsi files (1 file) into a matching
lpc51u68/ subdirectory. This keeps the dts layer aligned with the soc
layer.
Updated the board dts callers (lpcxpresso51u68) and any internal
cross-references. No functional change; the resulting devicetree is
byte-identical before and after this move.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Follow the family layout that already exists under soc/nxp/lpc/ and
move the LPC LPC11U6X family dtsi files (4 files) into a matching
lpc11u6x/ subdirectory. This keeps the dts layer aligned with the soc
layer.
Updated the board dts callers (lpcxpresso11u68 + faze) and any internal
cross-references. No functional change; the resulting devicetree is
byte-identical before and after this move.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
The shared nxp_rt10xx.dtsi places the DCP crypto engine at
0x402fc000, which is correct for RT105x/RT106x but wrong for
the RT1011. On RT1011 the DCP is located at 0x400f0000.
Accessing 0x402fc000 during DCP_Init() hits an unimplemented
AIPS slot and triggers an imprecise data bus fault (Zephyr
fatal error 26) before main(), e.g. running samples/drivers/
crypto on mimxrt1010_evk/mimxrt1011.
Relocate the DCP node to 0x400f0000 for RT1011. Verified on
hardware: boot now proceeds past crypto_dcp_init into main().
Assisted-by: GitHubCopilot:claude-opus-4.8
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Add missing `clocks` cell for the kernel clock on TIM8 in DTSI for
high-/XL-density STM32F1 devices, which prevented use of the peripheral
as the driver expects this cell to be present.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
As per our documentation, we have to
reuse bindings from Linux, there they use
"snps,dwmac-mdio", so let's use the same one
here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
Allign the devicetree structure of the wch ethernet
nodes wich the other existing nodes, that also use the
Synopsys Designware IP.
With that also move the "mdi-port-ctrl" from the
mdio node to the ethernet node, wich is now the
parent of the mdio node.
Signed-off-by: Fin Maaß <info@finmaass.de>
Allign the devicetree structure of the wch ethernet
nodes wich the other existing nodes, that also use the
Synopsys Designware IP.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to
reuse bindings from Linux, there they use
"snps,dwmac-mdio", so let's use the same one
here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to
reuse bindings from Linux, there they use
"snps,dwmac-mdio", so let's use the same one
here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to
reuse bindings from Linux, there they use
"snps,dwmac-mdio", so let's use the same one
here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to reuse bindings from Linux, there
they use "snps,dwmac-mdio", so let's use the same one here in zephyr.
The esp32 itself is not in Linux, but the ethernet IP from Synopsys is.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to reuse bindings from Linux, there
they use "snps,dwmac-mdio", so let's use the same one here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
The audio PLL should be set to 786.432MHz to be able to derive
standard audio samples rates 16kHz, 32kHz, 48kHz, etc.
This requires a multiplier of 32.768. It used to be rounded to 32.77.
Signed-off-by: Koen Van Herck <koen.v.herck@gmail.com>
Corrects register address for the HPPASS_SAR adc block. The previous
0x7000 address offset is the offset for the calibration data block.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
Define labeled Cortex-A55 and Cortex-A76 CPU nodes for RK3588 and select
the combined Cortex-A76/A55 CPU configuration. Keep the existing
ROC-RK3588-PC SMP variant on its supported Cortex-A55 CPUs.
Signed-off-by: Chao Liu <chao.liu@processmission.com>
CONFIG_SMP_BOOT_DELAY was a global, application-level switch that made
the kernel skip starting every secondary CPU at boot, used in-tree only
by two tests and in practice by one platform class (intel_adsp, where
the host or PM policy brings DSP cores up on demand). Boot topology is
a hardware/platform property, and all-or-nothing is needlessly coarse.
Replace it with a per-CPU devicetree flag, zephyr,deferred-start, on
the /cpus children (mirroring zephyr,deferred-init for devices):
z_smp_init() now always runs and simply skips flagged CPUs, which are
brought up at run time with the existing k_smp_cpu_start() (or
k_smp_cpu_resume()). Deferral is per CPU, so asymmetric bring-up
(start some cores at boot, defer others) is now expressible, and the
special-case branch disappears from the boot path.
The flag is declared in the common cpu.yaml binding. The lookup uses
DT_PROP_OR() so cpu nodes whose binding does not cover the property
simply cannot be deferred rather than breaking the build; a binding
for the intel,x86_64 compatible used by qemu_x86_64's cpu nodes was
missing entirely and is added.
The two users are converted: tests/kernel/multiprocessing/
smp_boot_delay marks the secondary CPUs in per-board overlays (both
tests pass on qemu_x86_64) and tests/boards/intel_adsp/smoke gains
overlays for its four platforms (all build). Normal SMP boot is
unaffected (verified on qemu_x86_64, all CPUs online).
Out-of-tree users migrate by dropping CONFIG_SMP_BOOT_DELAY=y and
adding zephyr,deferred-start to the deferred cpu nodes in their board
overlay.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit migrates the existing pinmux driver for the musca-b1
board to the newer pinctrl API. The new implementation also fixes
a bug in the original pinmux driver which would have selected
alternative function 2 instead of ALTF1 as desired.
The musca-s1 pinmux driver has been left as this board is
deprecated.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
The TMP112 can stay in shutdown (SD) mode and perform a single
conversion on demand via the one-shot (OS) bit. This is the lowest
idle-current mode and suits battery-powered designs that sample
infrequently.
Expose this mode through the conversion-rate property: setting it to 0
keeps the sensor shut down and triggers a one-shot conversion on every
sample_fetch call, blocking until the OS bit reads back as 1 (typ.
10 ms per datasheet 7.4.3) or a timeout elapses. The same mode can be
selected at runtime by setting a 0 Hz sampling frequency through
sensor_attr_set().
Because a new value (0) is prepended to the conversion-rate enum, the
device-tree enum index no longer maps directly onto the CR register
field, so the init path subtracts one for the periodic rates.
Tested on an nRF54L15-DK with a TMP112 over I2C: the periodic rates are
unchanged and conversion-rate = 0 returns correct readings on demand
while the sensor is held in shutdown between fetches.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Martin Hubáček <martin.hubacek@hardwario.com>
