RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Which does not have HW support for it, as stated by ST here:
https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html
"
The STM32U575 portfolio offers from 1 to 2 Mbytes of flash memory
and from 48- to 169-pin packages.
The STM32U585 is available with 2 Mbytes of flash memory and provides
an additional encryption accelerator engine (AES, PKA, and OTFDEC).
"
All the U5 SoC have a hash HW accelerator (even the ones which don't
have crypto support: U535XX, U575XX, U59XXX and U5FXXX).
The hash node is therefore moved directly inside the stm32u5.dtsi.
Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
1. Upgrade the ATCDMAC driver to make it compatible with multiple
ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
The STM32 QUADSPI peripheral allows to configure, in clock cycles, the
duration the chip select signal must stay high between each command sent
to the flash memory controller (QUADSPI_DCR_CSHT).
Currently, this value is set by the flash driver to 1 clock cycle in
single flash mode and 3 clock cycles in dual flash mode. However, the
minimal duration depends on the flash memory (typically 30-50 ns) and
the number of clock cycles on the QSPI's clock frequency. So, adding
this new property allows to select the value of CSHT to match the
requirement of the flash memory used. Also note that in single flash
mode, the current configuration is out-of-spec for most flash memories.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Add support for timer kernel clock for STM32U0.
Contrary to other series, on U0, TIMPCLK is always equal to PCLK, so no
need to define it, we can use PCLK directly.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7RS.
Define a new property for the timer prescaler in the RCC binding of H7RS.
Also fix the clock bus of TIM16 and TIM17 (they are on APB2 instead of 1)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7.
Define a new property for the timer prescaler in the RCC binding of H7.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H5.
Define a new RCC binding for H5 with the timer prescaler property (timpre).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F7.
The STM32F7 RCC clock driver complies with st,stm32f4-rcc
driver variant.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F4.
Define a new RCC binding to add the timer prescaler property (timpre).
This new binding is used for all STM32F4 except F405/F407/F415/F417 who do
not support it.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32F3.
Also reorganizes the timer instances:
- TIM3 is not available on F301, F318, F302x6 or x8, but is available for
all others
- TIM4 is available on F302xB and higher, F303xB and higher, F358, F398,
F373 and F378
- TIM7 is not available on F301, F318, F302, but is available for all
others
- TIM8 is only available on F303xB and higher, F358 and F398
- TIM20 is only available on F303xD and xE,and on F398
Depending of the SoC version, some timers have access to one or two
distinct clock sources. Timers with NO_SEL selection only have access
to the base TIMPLCKx clock, those defined with TIMx_SEL(0) can use another
source clock: STM32_SRC_TIMPLLCLK. That's why some clocks are redefined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit sets the interrupt mode to high-level
triggered, as fifo mode is enabled by default
(CONFIG_SPI_ITE_IT51XXX_FIFO_MODE=y) and the fifo
mode only supports high-level triggered.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add initial device tree support for the Rockchip RK3588 SoC.
The DTS describes:
- Four Cortex-A55 cores with PSCI enable-method
- GICv3 interrupt controller
- ARMv8 timer
- UART2 and UART3 (disabled by default)
Signed-off-by: Guowei Li <15035660024@163.com>
The OTG_HS PHY from stm32u5a5xx device require the correct reference
clock frequency selction in SYSCFG_OTGHSPHYCR. The current default is
hard coded to 16Mhz (which matches the development board crystal).
However, a custom board my require a different crystal and then the
USB will not work. This add a required field in the
st,stm32u5-otghs-phy binding to force user to select the correct
clock reference. The current nucleo_u5a5zj_q baord was updated to
reflect the mandatory field.
Signed-off-by: BUDKE Gerson Fernando <gerson.budke@leica-geosystems.com>
Add include of the stm32l4+ specific clock bindings in
stm32l4p5.dtsi in order to let all stm32l4+ benefit from it.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
