Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The BDF values can differ on the same platform, based on e.g. BIOS
configuration, and in the case of qemu the command line parameters. It's
therefore more reliable to always look up the BDF value based on the
known Vendor and Device IDs.
This patch introduces such a framework, and allows the incremental
update of PCIe drivers to start taking advantage of it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.
- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
Updating mps3_an547 board files with DTB entries for Ethos-U.
Adding DTS bindings for the Ethos-U DTB entry.
Signed-off-by: Kristofer Jonsson <kristofer.jonsson@arm.com>
Signed-off-by: Fredrik Knutsson <fredrik.knutsson@arm.com>
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
The sensor uses the ALERT terminology (pin can be configured to trigger
on certain events such as conversion ready or overvoltage alerts). The
"IRQ" name is not clear.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the units of the current LSB in microamperes, so that we can
measure low maximum currents. Right now it was specified in
milliamperes, but ignored and always hardcoded to 1mA in the driver.
This makes the driver pretty much useless when the maximum current to be
measured is in a range of e.g. 20-50mA.
This patch also removes some unnecessary ifdeffery: since we write the
calibration register, we can always provice measurements with the right
units. It is also wrong to provide sensor readings that do not match
with the units specified by the channel. After this change voltage is
always reported in V, current in A and power in W.
Note that power measurement had the current LSB hardcoded in the
calculation (assuming 1mA/LSB), this has been fixed as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following dtschema practices, add phyisical units to the shunt resistor
value: milliohms.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The "pmic" driver was in reality a driver for NXP PCA9420 PMIC. There's
no "universal PMIC". While the driver may work for other NXP PMICs, it
is clearly not generic for other vendors PMIC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Force cache-size to 0 and treat flashdisk as read-only when backing
partition has read-only flag set. This allows users to save RAM when the
application does not write to the flashdisk, e.g. when a predefined FAT
filesystem is used.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Sort SoC nodes by address to make it easier to find them. As part
of this also move the intel-sha node under SoC where it belongs.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Following the modification of the STM32 OSPI driver, the clock-names
binding is now required
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
"alh0: alh1:" will create only one instance and this needs to be
reverted to original form with two instances
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
For larger transfers DMA can be used enabling other tasks
to continue running. A threshold of 32 byte transfers
is about right and is defined threshold value for using DMA.
This does not currently support multiple SPI transactions changing
chip select with DMA (though the hardware supports this) currently.
Instead opting for the simpler first change of enabling one shot
DMA SPI transfers for those where the size warrants it.
Adds the loopback binding option to enable the spi_loopback test.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
New ADC driver for the TI CC13xx/CC26xx family.
ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).
Async mode was also implemented & tested.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This commit adds an optional property to the nRF21540 Front-End Module
devicetree description that specifies supply voltage in mV. This
property can be used by the nRF21540 driver to compensate the value of
achieved gain for different supply voltage.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SparkFun Pro Micro header connector that is implemented by many
other controllers. This allows hardware with compatible headers to
define the related GPIOs and peripherals.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Cavs25 alh definition is currently the same as in ace platform, which is
wrong, thus fix it.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The ESP32 series MCUs allow to set a timeout which triggers an error
if the SCL line is unchanged for the specified amount of time.
By default, the ESP-IDF HAL sets the timeout to an arbitrary value of
10 times the bus cycle.
This is not sufficient for chips like the TI bq76952, which pulls the
SCL line low (clock stretching) for several 100 µs.
The timeout should also not be dependent on the chosen bitrate, as it
is defined by the time a chip needs for internal calculation before it
can provide requested data or continue communication.
This commit adds a property to devicetree to allow configuration of
the scl timeout. This value is set via direct register access, as the
ESP-IDF HAL does not provide access to the enable bit and does not
give any information about the maximum size of the timeout (defined
in I2C clock cycles in the register).
Fixes#51351
Signed-off-by: Martin Jäger <martin@libre.solar>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add bindings to describe a block storage device based on flash map
partition.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add devicetree binding for the PSA Crypto Random source.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
This commit adds missing binding file for the ite,it8xxx2-usbpd.
Without this file, the DT_HAS_*_ENABLED macro wasn't defined and
couldn't be used in the Kconfigs.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
A USB TypeC connector has many peripherals associated with
it and the DTS binding in this commit provides a way to group
peripherals and properties in a device tree.
This binding is used with the USB-C Subsytem.
This is based on Linux, documentation:
https://www.kernel.org/doc/Documentation/devicetree/bindings/connector/usb-connector.yaml
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Add pin control properties to the STM32 UCPD bindings file so that
the pins can be configured in the device tree.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
USB interface that may be used to send messages from a USB host to
the M4 processor in the S3B, and vice-versa.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Add support for regulator-boot-on to PMIC driver. Many PMIC devices will
be enabled at boot, so this property allows the regulator framework
to correctly track their state.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
As part of a previous refactor, this property was removed from the STM32
USART binding. The driver code to support this feature was not changed.
This commit simply adds the property back to the new base .yaml for
device trees which used it.
Tested on a proprietary board using the STM32U5 on USART1.
Signed-off-by: Peter Maxwell Warasila <madmaxwell@soundcomesout.com>
Migrates all Winsen sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all WE sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Vishay sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all TI sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ST sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Silabs sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Sensirion sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Semtech sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Seeed sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all SBS sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Plantower sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Panasonic sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all NXP sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Nuvoton sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Nordic sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Microchip sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Measurement Specialties sensors to inherit base sensor
device properties. This will allow us to define properties shared by
multiple sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Maxim sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all LM sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ITE sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Intersil sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Invensense sensors to inherit base sensor device
properties. This will allow us to define properties shared by multiple
sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Infineon sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all HOPERF sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Honeywell sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Espressif sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Bosch sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Avago sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Atmel sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Asahi-Kasei sensors to inherit base sensor device
properties. This will allow us to define properties shared by multiple
sensors in one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all Aosong sensors to inherit base sensor device properties.
This will allow us to define properties shared by multiple sensors in
one place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all AMS sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Migrates all ADI sensors to inherit base sensor device properties. This
will allow us to define properties shared by multiple sensors in one
place.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Introduces an initial set of devicetree properties to be inherited by
all sensor devices, similar to how we define a base set of devicetree
properties for I2C and SPI devices. These properties will be used by the
future sensor subsystem to manage and expose sensors to a host operating
system, through HID or another protocol. Additional properties may be
added in the future.
An earlier version of this patch attempted to use the label property
instead of friendly-name, as it was noted during code review as a
possibly legitimate usage of the mostly-deprecated label property.
However, in practice it was difficult to implement because most sensor
bindings also inherit from i2c-device.yaml or spi-device.yaml, and
therefore inherit the deprecated label property from base.yaml. To work
around the deprecation, every sensor binding would have needed to
explicitly block the label property with a property-blocklist, which
would somewhat defeat the purpose of having a shared sensor-device.yaml.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Newer ESP32 series MCUs like the ESP32-C3 contain some register changes
incompatible to the original ESP32 and the SJA1000.
The additions in this commit consider these changes and fix the
incompatibilities in the TWAI front-end for the SJA1000 driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Enable GPIO driver on s32z270dc2_r52 boards. S32Z27 pads are grouped
into GPIO ports A to N.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Implement GPIO driver minimal API's for NXP S32 devices, based on SIUL2
peripheral. SIUL2 allows to control the pins electrical characteristics
such as internal pull resistors, pin direction and more.
GPIO driver API's for interrupts will be implemented in a future patch.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 LINFlexD peripheral operating
in UART mode. Polling and interrupt-based serial API's are supported.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce Pinctrl driver for SIUL2 module present on NXP S32 devices,
which provides control over all pins, such as function selection and
electrical characteristics that appear on external chip pins.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Ethernet MAC dts definition for STM32F107, similar to STM32F207 but with
different clocks, especially no PTP clock.
Signed-off-by: Pierre-Emmanuel Novac <piernov@piernov.org>
Add mode selection properties for regulator-pmic compatible. These
mode selection properties will be used with regulators that support
multiple modes, with each mode enabling specific voltage and current
limits.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Refactor binding to use root PMIC IC, so that properties can be shared
between regulator devices. Each individual regulator output is still
created as an individual device, since the regulator API aligns with
these devices better than the PMIC IC itself.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If the flash is used in 4-byte addressing, reading SFDP will fail after
a system reset if the flash isn't power cycled or hardware reset, since
Zephyr will try to use 3-byte addressing while the flash (still) expects
4-byte addressing.
This commit adds the ability to send a reset command to the flash as part
of initialization, which complements the existing reset-gpio
functionality, and is useful on low-pincount flashes which do not have a
hardware reset.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
Added support for the AMS AS621x series of temperature sensors as a
variant of the TI TMP108 temperature sensor.
Signed-off-by: Jared Baumann <jared.baumann8@t-mobile.com>
Signed-off-by: James Johnson <james.johnson672@t-mobile.com>
Adding ethernet in the DTS file and corresponding binding
for Cyclone V SoC FPGA board..
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
rt1170 has two group fast gpio and shared the same
interrupt source. Now add the dts definition for the
fast gpio
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Add Intel dmic dai dts definitions for ace15, cavs15 and cavs25
platforms.
Add also pre dts cmake files as the dmic nodes use same address and emit
warnings otherwise.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add a fifo address as int value into dmic yaml to separate different
outputs (corresponds to different dais) from the same hw block. Also
change shim address from array to int value.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add successive inclusion for STM32F072 dts by including
STM32F070 dts instead of STM32F0 dts.
This allows to reuse the definition of
- Flash
- SPI
- USB
from the new parent.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace the hardcoded kPWM_Prescale_Divide_128
driver prescaler with the ones defined in the dtsi file
that allow overriding them by the user.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
This commit adds a driver to simulate GPIO state and interrupts
using the keyboard when using SDL.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Add 2 properties to configure the "any movement" event.
* Ability to disable the interrupt latch
* Select movement mode
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Update RT11xx SOC DTSI files to use DT nodelabels on RT11xx SOCs,
instead of reencoding the base address of each peripheral in the M7
and M4 DTSI files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Include files should not have compatible properties set. These do not
represent real hardware and should therefore not appear to do so, e.g.
by appearing in the bindings index as if they were a real hardware
peripheral.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Fix ordering of IOMUXC pinctrl selections for gpio pinmux setting.
This will allow the gpio_configure call to correctly set
mux settings for this SOC.
Fixes#50502
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The vref has to be set to 3000mV.
It is the voltage to find on the stm32F3.
is fixed by the platform to be lower or equal to VDDA.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add gpio-reserved-ranges property to gpio controllers on RT10xx devices
that have gaps in their GPIO numbering.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 qmspi. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 adc. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 pwm. Update board dts, pinmux and driver files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove pinmux calls and add pinctrl support for mec15xx
and mec1501 espi. Update board dts, pinmux and espi driver
files.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Apparently, downstream drivers are allocating devices using
DT_NODELABEL(alh0) and DT_NODELABEL(alh1) on a node with compatible
intel,alh-dai. These represent something like "channels" within the
device.
This is a strange choice. It would be better to do something like have
a property with the count of "channels", or one child node per
channel.
It is also a dtc error to have duplicate node names like this, and
will be an error in Zephyr's dtlib soon.
For now, work around this representation issue by replacing it with
something equivalent that doesn't have duplicate nodes. The
representation should be addressed at some point, but not by me.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Two issues:
- The nsmi_gpio107 node is being defined twice with the same pinmux
property value. This is an error when compiling the file with dtc.
Zephyr's dtlib doesn't currently error out on this, but it will soon.
Fix this by removing one of the redundant definitions.
- The eeprom_clk_gpio117 node label is referring to a node named
gpspi_clk_gpio117, which is already defined in the same file, but
with a different pinmux property value. This looks like a clear
copy/paste error causing invalid pinmux settings for the
gpspi_clk_gpio117 node.
Fix it by aligning the node name with the node label to create
a separate node with its own pinmux value.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Fix the incorrect temperature sensor (Die temp), the default value of
the vref-mv is 3.3V.
Actually, the vref is a board value rather than a soc one
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The FULLDRIVE description on the rt-iocon yaml file was
describing the slew rate and not the FULLDRIVE property.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
The LPC55s3x SOC comes with 2 FlexPWM peripherals each with 4 Sub-Modules.
Each Sub-Modules has 2 channels A && B.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When the EXTI Line nb is not set as interrupt by default
(at reset value), the uart instance cannot waekup the
system from its low power stop mode.
The EXTI line must be specified, like with stm32WL55
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds a base binding for I3C controllers.
Note that this follows the Linux kernel 5.17 bindings under
Documentation/devicetree/bindings/i3c/i3c.yaml.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a few bits to the devicetree API tests for multi-bus
nodes where a bus can support multiple protocols. This uses
I3C as basis as I3C controller can support both I2C and I3C on
the same bus, while I2C controller cannot support both. So
this needs to make sure the correct bus macros are generated
if appropriate (and not generated if not needed).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add support to at86rf212[b] sub-giga devices. This work enables use of
pages 0, 2 and 5 in accordance with IEEE-802.15.4/2003/2006/2011. The
proprietary speeds can be object of future work.
Note: It is recommended that user define a power table for better
performance, low emissions and to save power. A reference power table
can be found in the datasheet and should be used for tests only and
not on a final product.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of power table is hardcoded in the driver which is a
problem when use devices in production. This change remove all hardcode
from driver and reimplement the feature to allow people create a table
which is defined in devicetree. The big advantage is that each board can
define their own table based on lab tests and allows use of FEM devices
inclusive.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.
- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
The property is similar to the usb_controller_index_t
enum that is available in the NXP SDK.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit introduces the 1-wire master driver for maxim ds2485.
The ds2485 master has nearly the same (1-wire) feature set and
i2c-interface as the ds2477.
Therefore the common parts are extracted, but to avoid
any nda troubles only the ds2485 specific part is included.
Compared to older 1-wire masters, the ds2485 supports higher level
commands, supporting multi byte operations, search next, automatic crc
calculation.
In this driver only basic read and write operations are supported,
further hardware features are not yet utilized by the driver.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
According to errata sheet, LSE driving-capability should not be set
to 0 or 1.
Set it to 2 as default value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This driver provides an interface to SocketCAN interfaces of the Linux
system running a Zephyr application with the native_posix board. These
interfaces may be virtual or actual CAN buses.
Signed-off-by: Martin Jäger <martin@libre.solar>
Migrate information to DTS and get it from there on the code. Note that
for CAVS 15, the information is not migrated as there's no DTS entry for
it. It can be brought back (in the DTS) if TLB support is enabled for
it.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Reduce the default RAM usage for the NXP LPC MCAN CAN controller driver by
reducing the number of RX buffers, TX buffers, and filter elements.
The LPC MCAN uses regular SRAM as backend and the default configuration
causes SRAM overflows for many CAN tests.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add emulator functionality to the serial_test driver, so that it can be
used to simulate a device on the other end of the uart.
If you don't set the buffer-size property in the dts node, there should
be effectively no change from the previous behavior.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Add the DMA in the DTS binding for OCTOSPI interface
for the stm32 devices from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
There are three types GD32 FMC.
GD32 FMC v1: its flash memory has 1 bank, page size is equal in the
bank, flash size is smaller than 512KB.
GD32 FMC v2: its flash memory has 2 banks. Page size equal within the
same bank but different between banks. Flash size can be up to 3072KB.
FMC v2 has two registers to control bank0 and bank1 separately.
GD32 FMC v3: its flash memory has 2 banks, use sector size as the
minimum operating unit, the sector size is not equal.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
R-Car Gen3 platforms have up to 7 channels. Add the node to
the rcar_gen3_cr7 SoC series. In contrary to Linux, declare
only one PWM controller with 7 channels. So only one node is
written into dtsi file.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Define RaspberryPi Pico ADC.
The ADC has internally connected temperature sensor,
Add property to enable this.
The ADC has a single VREF. VCC usually connects to it,
but it may not be in a case.
Add property to make configurable it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Use the clock control API to enable peripheral clocks. Note that both
GPIO and pinctrl drivers are updated at once since they share some IP
blocks.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use the clock control API to turn on ADC clocks. Note that clock
selection is not yet implemented, so we still rely on custom rcu
properties for that.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove the CAN_STM32FD_CLOCK_DIVISOR configuration option,
and add configuration via dts property clk-divider instead.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
There is only a single DMA in GD32F3X0. It is referenced as DMA in
datasheet, not DMA0 as in series that have > 1.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Enable all cpu cores in soc dts and disable unused core in board dts.
2. Use default irq priority for uart interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Use node label to overwrite the flash and ram properties.
This removes some boilerplate as it is less verbose.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Convert the device to be Devicetree based. Adjusted tests and other
areas that were using old Kconfig properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This patch adds D0i3 definition to available core power states in device
tree.
Additionally, changing the name of the OFF state to better reflect what
is in the documentation.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
The clock bus of the specific SPI module (FIU) is under FIUCLK. The
previous commit misconfigured it to APB3_CLK. Although it won't
cause any issue as the driver doesn't use it. It should be fixed to
prevent confusion when reading the datasheet.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Some custom refresh profiles need to set the PLL and VDCS
registers. Add them as optional DT properties.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for overriding display LUTs in the UC81xx driver. This
makes it possible to use different LUTs for the full and partial
refresh profiles.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add a separate profile for partial refreshes. This makes it possible
to specify a separate refresh configuration for partial and full
refreshes.
The driver now transitions to full refresh mode when blanking is
turned on. It transitions back to partial refresh mode when there is a
write while blanking is off.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Introduce the concept of refresh profiles which are specified as a
child node in the device tree. This makes it possible to use different
overrides for different types of refreshes (full/partial).
The only profile that is currently supported is the "full" profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
This reverts commit fdd47f39be.
After v4.4.1, write-block-size is no longer needed to be 32-bytes
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
zephyr.dts:482.21-491.5: Warning (simple_bus_reg): /soc/dietemp: missing
or empty reg/ranges property.
To fix this bug, just move dietemp node outside of soc{}.
Signed-off-by: TLIG Dhaou <dhaou.tlig-ext@st.com>
This adds flash driver for Renesas SmartBond(tm) family.
This technically uses QSPI controller but since default and most
commonly used configuration is to boot from external QSPI flash (DA1469x
do not have built-in flash) and that flash is mapped into memory space,
it can be represented as internal flash.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds serial driver for Renesas SmartBond(tm) family. Both polling
and interrupt APIs are supported.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
