- Add SOC interrupt properties and interrupt-names ("reset_prep", "pcidev",
"pmu2ioapic") to intel_ish5 DTS files so PM IRQs are discoverable via DT.
- Move SEDI PM initialization and IRQ setup into ISH SOC PM init:
- Remove the direct call to sedi_pm_init() from soc_early_init_hook in
soc.c.
Previously SEDI code has those IRQ numbers hard coded and calls Zephyr APIs
to connect IRQs, which should be avoided.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
1. Added siwx91x power domain node in siwg917.dtsi
2. Updated UART device nodes to reference the newly added power domain.
3. Implemented power domain driver to manage power domain transitions
for the SoC.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
PM and PM_DEVICE should be enabled, by default. The latter, require that
timer2 node be employed and reserved for the OS tick generation.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add bindings for the SF32LB52X SoCs PINMUX peripheral. Note that
SF32LB56X SoCs contain a compatible IP (not others, where HPSYS_CFG is
not required), so if SF32LB56X support is added, binding could be
adjusted to reflect 52x/56x support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This is defined as a subnode because RCC is a MFD device (clock and
reset controller), however, Zephyr does not allow >1 device per DT node!
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add bindings for the SiFli SF32LB PMUC. PMUC is a sort of "syscon" type
register block used to control multiple power-management related stuff.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Refer to Ch 2 "Clock and Reset" from reference manual. Some may require
specific bindings in the future if they can be configured (e.g. RC48).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SF32LB AON module controls certain low-power or clocks, e.g.
enablement of HXT48 on different LP modes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SoCs have a multi-purpose register set named HPSYS_CFG, which we
can treat as a "syscon".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SRAM is segmented as:
- RAM0: 128K (DTCM)
- RAM1: 128K
- RAM2: 256K
where:
- RAM0 can be accessed by all peripherals except PTC1/2.
- RAM1/RAM2 have its own port, so e.g. master 1 can access RAM1 while
master 2 can access RAM2.
Depending on the application, one may decide to just use the whole RAM
as a single block, split RAM0 (DTCM) and RAM1/2, etc. For now, provide 2
schemes:
- Use all SRAM as a single block
- Use RAM0 (DTCM) + RAM1/2
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Just define basic ARM hardware: CPU, MPU and NVIC settings. SF32LB SoCs
are technically Arm-Star MC1 based, an Arm Cortex-M33 compatible CPU
developed by Arm China.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Explicitly set the default alt clock for canfd. Without
explicitly setting it the clock subsystem will return
the frequency of the gating clock(APB1).
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix peripheral availability per h5 line.
Some peripherals are not available on the entry level
lines of the stm32h5 series:
- fdcan2 only on SoCs >= H523, but not on h562
- sai only on >= H562
- ethernet only on >= H563
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add the compatible zephyr,memory-region for all mmio-sram region
which do not have yet that compatible as well as add the label to
those regions. This allow to have a linker memory report which list
all areas and also have all regions accessible via the linker script.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
- Replace the UARTs with the ones defined in k3-am62-main.dtsi.
- Also ends up adding main prefix to the uarts.
- Adjust the board dts to use the new names.
- Since the same file is also used by m4 cores, do not add interrupt
properties, since they are different between m4 and a53
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add support for BGM220P modules. Enable oscillators in SoC DTS
since the necessary crystals are present in the modules.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add missing EUART0 peripheral to devicetree for xg22.
Fix NUM_IRQS, there are 64 external interrupts on xg22.
Remove `select` of UART_INTERRUPT_DRIVEN at SoC level, this doesn't
belong here, since it prevents disabling the UART. This should be a
board or application level decision.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Describe the DSI block available from STM32F767 and onward
and allow to output data generated by the LTDC to a DSI
panel.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
