dts: stm32u5: Removes trailing 'U's in dt props
Integers in devicetree are always signed. See https://github.com/zephyrproject-rtos/zephyr/pull/89978#discussion_r2124113613 signed-off-by: Harris Tomy <harristomy@gmail.com>
This commit is contained in:
parent
d280d89214
commit
ab6c6b44f3
2 changed files with 69 additions and 69 deletions
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@ -218,7 +218,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
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};
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gpiob: gpio@42020400 {
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@ -226,7 +226,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
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};
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gpioc: gpio@42020800 {
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@ -234,7 +234,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
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};
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gpiod: gpio@42020c00 {
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@ -242,7 +242,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
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};
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gpioe: gpio@42021000 {
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@ -250,7 +250,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
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};
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gpiog: gpio@42021800 {
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@ -258,7 +258,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
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};
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gpioh: gpio@42021c00 {
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@ -266,7 +266,7 @@
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
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};
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};
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@ -279,7 +279,7 @@
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wwdg: wwdg1: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002c00 0x1000>;
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clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 11)>;
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interrupts = <0 7>;
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status = "disabled";
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};
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@ -296,8 +296,8 @@
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 14)>;
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resets = <&rctl STM32_RESET(APB2, 14)>;
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interrupts = <61 0>;
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status = "disabled";
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};
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@ -305,8 +305,8 @@
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
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resets = <&rctl STM32_RESET(APB1L, 18U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 18)>;
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resets = <&rctl STM32_RESET(APB1L, 18)>;
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interrupts = <63 0>;
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status = "disabled";
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};
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@ -314,8 +314,8 @@
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
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resets = <&rctl STM32_RESET(APB1L, 19U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 19)>;
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resets = <&rctl STM32_RESET(APB1L, 19)>;
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interrupts = <64 0>;
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status = "disabled";
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};
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@ -323,8 +323,8 @@
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
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resets = <&rctl STM32_RESET(APB1L, 20U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 20)>;
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resets = <&rctl STM32_RESET(APB1L, 20)>;
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interrupts = <65 0>;
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status = "disabled";
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};
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@ -332,8 +332,8 @@
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lpuart1: serial@46002400 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x46002400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
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resets = <&rctl STM32_RESET(APB3, 6U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 6)>;
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resets = <&rctl STM32_RESET(APB3, 6)>;
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interrupts = <66 0>;
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status = "disabled";
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};
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@ -344,7 +344,7 @@
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <59 5>;
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clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 12)>;
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status = "disabled";
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};
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@ -354,7 +354,7 @@
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <60 5>;
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clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 14)>;
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status = "disabled";
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};
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@ -364,7 +364,7 @@
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#size-cells = <0>;
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reg = <0x46002000 0x400>;
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interrupts = <99 5>;
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clocks = <&rcc STM32_CLOCK(APB3, 5U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 5)>;
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status = "disabled";
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};
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@ -374,7 +374,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 21)>;
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interrupts = <55 0>, <56 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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@ -386,7 +386,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 22)>;
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interrupts = <57 0>, <58 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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@ -398,7 +398,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46002800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 7U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 7)>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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@ -410,7 +410,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 1)>;
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interrupts = <101 0>, <100 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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@ -421,7 +421,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 11)>;
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interrupts = <67 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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@ -432,7 +432,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
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clocks = <&rcc STM32_CLOCK(APB1_2, 5)>;
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interrupts = <68 0>;
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interrupt-names = "global";
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status = "disabled";
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@ -443,7 +443,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 12)>;
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interrupts = <98 0>;
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interrupt-names = "global";
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status = "disabled";
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@ -454,7 +454,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 13)>;
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interrupts = <110 0>;
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interrupt-names = "global";
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status = "disabled";
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@ -464,7 +464,7 @@
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compatible = "st,stm32-rtc";
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reg = <0x46007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK(APB3, 21U)>;
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clocks = <&rcc STM32_CLOCK(APB3, 21)>;
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prescaler = <32768>;
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alarms-count = <2>;
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status = "disabled";
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@ -495,8 +495,8 @@
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
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resets = <&rctl STM32_RESET(APB2, 11U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 11)>;
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resets = <&rctl STM32_RESET(APB2, 11)>;
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interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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@ -511,8 +511,8 @@
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
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resets = <&rctl STM32_RESET(APB1L, 0U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 0)>;
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resets = <&rctl STM32_RESET(APB1L, 0)>;
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interrupts = <45 0>;
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interrupt-names = "global";
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status = "disabled";
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@ -527,8 +527,8 @@
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
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resets = <&rctl STM32_RESET(APB1L, 1U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 1)>;
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resets = <&rctl STM32_RESET(APB1L, 1)>;
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interrupts = <46 0>;
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interrupt-names = "global";
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status = "disabled";
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
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resets = <&rctl STM32_RESET(APB1L, 2U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 2)>;
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resets = <&rctl STM32_RESET(APB1L, 2)>;
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interrupts = <47 0>;
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interrupt-names = "global";
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status = "disabled";
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
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resets = <&rctl STM32_RESET(APB1L, 3U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 3)>;
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resets = <&rctl STM32_RESET(APB1L, 3)>;
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interrupts = <48 0>;
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interrupt-names = "global";
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status = "disabled";
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
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resets = <&rctl STM32_RESET(APB1L, 4U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 4)>;
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resets = <&rctl STM32_RESET(APB1L, 4)>;
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interrupts = <49 0>;
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interrupt-names = "global";
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status = "disabled";
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
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resets = <&rctl STM32_RESET(APB1L, 5U)>;
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clocks = <&rcc STM32_CLOCK(APB1, 5)>;
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resets = <&rctl STM32_RESET(APB1L, 5)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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status = "disabled";
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
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resets = <&rctl STM32_RESET(APB2, 13U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 13)>;
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resets = <&rctl STM32_RESET(APB2, 13)>;
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interrupts = <51 0>, <52 0>, <53 0>, <54 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
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resets = <&rctl STM32_RESET(APB2, 16U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 16)>;
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resets = <&rctl STM32_RESET(APB2, 16)>;
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interrupts = <69 0>;
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interrupt-names = "global";
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status = "disabled";
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
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resets = <&rctl STM32_RESET(APB2, 17U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 17)>;
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resets = <&rctl STM32_RESET(APB2, 17)>;
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interrupts = <70 0>;
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interrupt-names = "global";
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status = "disabled";
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
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resets = <&rctl STM32_RESET(APB2, 18U)>;
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clocks = <&rcc STM32_CLOCK(APB2, 18)>;
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resets = <&rctl STM32_RESET(APB2, 18)>;
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interrupts = <71 0>;
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interrupt-names = "global";
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status = "disabled";
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reg = <0x420d1400 0x400>;
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interrupts = <76 0>;
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clock-names = "ospix", "ospi-ker", "ospi-mgr";
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clocks = <&rcc STM32_CLOCK(AHB2_2, 4U)>,
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clocks = <&rcc STM32_CLOCK(AHB2_2, 4)>,
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<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
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<&rcc STM32_CLOCK(AHB2, 21U)>;
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<&rcc STM32_CLOCK(AHB2, 21)>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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rng: rng@420c0800 {
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compatible = "st,stm32-rng";
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reg = <0x420c0800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
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clocks = <&rcc STM32_CLOCK(AHB2, 18)>;
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interrupts = <94 0>;
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nist-config = <0xf60d00>;
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health-test-config = <0x9aae>;
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sdmmc1: sdmmc@420c8000 {
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compatible = "st,stm32-sdmmc";
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reg = <0x420c8000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 27U)>,
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 27)>,
|
||||
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
|
||||
resets = <&rctl STM32_RESET(AHB2L, 27U)>;
|
||||
resets = <&rctl STM32_RESET(AHB2L, 27)>;
|
||||
interrupts = <78 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -738,7 +738,7 @@
|
|||
dac1: dac@46021800 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x46021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB3, 6U)>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB3, 6)>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
@ -746,7 +746,7 @@
|
|||
adc1: adc@42028000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x42028000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10U)>,
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10)>,
|
||||
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
|
@ -764,7 +764,7 @@
|
|||
adc4: adc@46021000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x46021000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB3, 5U)>,
|
||||
clocks = <&rcc STM32_CLOCK(AHB3, 5)>,
|
||||
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
|
||||
interrupts = <113 0>;
|
||||
status = "disabled";
|
||||
|
@ -786,7 +786,7 @@
|
|||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <39 0>, <40 0>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 9)>;
|
||||
bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -797,7 +797,7 @@
|
|||
reg = <0x40020000 0x400>;
|
||||
interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0
|
||||
80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB1, 0)>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <114>;
|
||||
dma-offset = <0>;
|
||||
|
|
|
@ -33,15 +33,15 @@
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x42022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 9U)>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 9)>;
|
||||
};
|
||||
};
|
||||
|
||||
usart6: serial@40006400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40006400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 25U)>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1, 25)>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 25)>;
|
||||
interrupts = <126 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -52,7 +52,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40009800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 6U)>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 6)>;
|
||||
interrupts = <128 0>, <127 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
|
@ -64,7 +64,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40009c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 7U)>;
|
||||
clocks = <&rcc STM32_CLOCK(APB1_2, 7)>;
|
||||
interrupts = <130 0>, <129 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
|
@ -74,7 +74,7 @@
|
|||
adc2: adc@42028100 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x42028100 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10U)>,
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10)>,
|
||||
<&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
|
@ -96,7 +96,7 @@
|
|||
adc1_2: adc@42028300 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x42028300 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
|
||||
clocks = <&rcc STM32_CLOCK(AHB2, 10)>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue