Describe Alif Balletto and Ensemble I2C controllers as disabled
snps,designware-i2c nodes so boards can enable them through the
existing upstream I2C_DW driver without adding a new driver.
Each node includes register base, interrupt routing (NVIC/GIC as
appropriate), clock phandle, and standard DesignWare properties such
as clock-frequency and timing offsets.
Controllers remain disabled by default until board devicetree
enables the instances required by each devkit.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
This driver integrates with the Zephyr regulator API to control the
MAX20362 PMIC. Additional MAX20362-specific helper functions are
exposed to support device features that are not covered by the
generic regulator API.
Signed-off-by: Anthony Raterta <Anthony.Raterta@analog.com>
Add a driver for the VIRTIO I2C adapter device (virtio spec 1.3, section
5.16), letting a Zephyr guest drive an I2C bus exposed by a hypervisor or
a vhost-user backend.
One i2c_msg is one descriptor chain, and the whole batch is queued before
the device is notified, so a multi-message transfer costs one round trip
instead of one per message. FAIL_NEXT groups the messages the device runs
back to back; a message that ends in a stop closes its group, so a failure
takes the rest of that group with it.
Every operation is a round trip to the device, so the I2C API can only be
used from a thread. VIRTIO_I2C_F_ZERO_LENGTH_REQUEST is mandatory, so a
device that does not offer it is refused. 10-bit addressing is not
supported, and the bus speed is accepted and ignored.
Assisted-by: Claude Code:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add min/max constraints for row-size and col-size in the input-keymap
devicetree binding to reject out-of-range values at build time.
This aligns schema validation with MATRIX_KEY 8-bit row/column
encoding and uint8_t runtime storage in input_keymap.
Signed-off-by: Mingzong Zhao <mingzong.zhao@outlook.com>
Add DMA support for STM32MP13 by defining DMA1, DMA2, and DMAMUX1
controller nodes in the SoC devicetree.
Signed-off-by: Christophe Guibout <christophe.guibout@st.com>
Add the display driver for the DSI bridge, which streams a
framebuffer to the host DPI port. It owns the framebuffers,
presents a completed frame at the next frame boundary so an
update is tear-free, and reports frame events.
Reading back returns the buffer on screen, and blanking is
forwarded to the panel, which owns the backlight. The MIPI DSI
host starts and stops it, since the framebuffer size depends on
the pixel format the panel reports when it attaches.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add bindings for the ESP32-P4 MIPI DSI host and for the DPI
scanout controller behind it, and the nodes describing them.
The bridge streams a framebuffer to the host DPI port rather
than being a peripheral of its own, so it is a child of the
host and carries no registers.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes the help text of the lvgl pointer input device binding to mention the
correct property names for touch devices.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The E4, E6 and E8 devices carry more GPIO than the minimum common subset:
GPIO9 to GPIO14 in the peripheral domain. They also carry the full eight
pin wide LPGPIO rather than the two pins available on the E1C.
Note that GPIO16 and GPIO17 are left out as they are not bonded out on
every package this layer covers.
As with the ports in the common layer, the interrupt lines are described
for completeness, but the hardware requires the GPIO debounce logic to be
enabled for interrupt detection to work correctly, which in turn needs
the debounce clock running. Enabling it is left to a follow-up change.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Ensemble SoCs use the Synopsys DesignWare GPIO controller, with one
eight pin controller instance per port and one interrupt line per pin.
Add the controllers common to every Ensemble SoC: GPIO0 to GPIO8 and
LPGPIO. LPGPIO sits in the Always-On domain and is only two pins wide on
the E1C, so it is described here at that width and widened by the layer
that describes the larger devices.
As with the other peripherals in this layer, the interrupt routing is
kept out of the resource description and lives in the NVIC and GIC
specific files, since the same controller is reached through the NVIC
from an RTSS cluster and through the GIC from the APSS cluster.
The interrupt lines are described here for completeness, but the hardware
requires the GPIO debounce logic to be enabled for interrupt detection to
work correctly, which in turn needs the debounce clock running. That
clock is off after reset and nothing turns it on, so enabling it is left
to a follow-up change.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add the ESP32-C61 devicetree, dt-bindings headers and the
wroom-1 module dtsi files. The devkitc module is a wroom-1
n8r2, so its dtsi carries 8 MB flash and 2 MB psram. UART0
uses GPIO11/GPIO10, the ROM console pins. GPIO15-21 are the
MSPI flash pads and are marked reserved.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The pgain, again, ppulse-length and pled-boost enums spelled the 2-bit
register fields they select in hex, i.e. 0x00/0x01/0x10/0x11, so the
last two selections were really 16 and 17 and reached the registers as
such. The pgain entries were also mislabelled, listing 4x twice instead
of the 1x/2x/4x/8x the part supports.
Express each enum as the physical value it selects - gain multipliers,
microseconds and percent - and let DT_INST_ENUM_IDX() turn the selection
back into the register field value, which the enums are already ordered
to match. Devicetree now describes the sensor instead of its register
encoding, and the defaults keep selecting the same settings as before.
While here, give every default the justification the binding guidelines
require, and bound ppulse-count to the 1 to 64 pulses the PPULSE field
can encode.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add flash ranges, package GPIO counts, and BLE radio feature flags
for IM40 (QFN40) and IM32 (QFN32), matching the MG22C counterparts.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Assisted-by: Cursor:composer-2.5
Describe the SPC buffered bandgap output as a regulator on MCXA SoCs so
ADC channel configurations can reference the shared hardware resource.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Allow an LPADC channel node to reference an optional bandgap supply.
Enable the supply when channel setup selects the physical input
described by that node so continuous monitoring needs no additional
application control.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Expose the buffered SPC bandgap output through the regulator API so
consumers can acquire it only while needed. Use the common regulator
reference counting and always-on policy instead of defining a separate
resource lifecycle.
The output has a fixed voltage and supports enable and disable operations.
Device PM restores the hardware state when an active regulator resumes.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Several binding type folders had no entry in the registry, so the
documentation fell back to a capitalized folder name ("Cpu_freq",
"Pulse-io", ...). Add entries for buzzer, clock-monitor, cpu_freq, dali,
dsp, mcumgr, mux and pulse-io.
Also fix the "ppmcie" key, which never matched the "pmci" folder it was
meant to describe, and use the DMTF expansion of the PMCI acronym.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:claude-opus-5
- Add the watchdog node for pic32cz_ca device
- Update the binding for pic32cz_ca device
Signed-off-by: Farsin Nasar V A <farsin.nasarva@microchip.com>
During build, we are presented with a warning from the devicetree compiler
<Warning (interrupt_provider): /soc/gpio@20120000: Missing #address-cells
in interrupt provider>. This patch strips the interrupt-controller
property from GPIO banks.
Signed-off-by: Alexandra Covaci <Alexandra.Covaci@microchip.com>
Use the CM0+ IRQ numbers for the AON GPIO, LPUART and RTC
nodes in the shared MCXL AON devicetree file.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
The lp core is an rv32imac processor with the zicsr and
zifencei extensions, but the devicetree only declared i, m, c
and zicsr. Add the missing a and zifencei extensions so the lp
core image builds with native atomic instructions and fence.i
support, matching the esp32c5 and esp32c6 definitions.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The xmc7200 flash-controller node declares two soc-nv-flash children
(flash0 and flash1). The Infineon CAT1 flash driver only supports a
single soc-nv-flash child, so when the driver is built without fixed
partitions it selects the first okay child and the presence of a second
okay soc-nv-flash node breaks the build.
Disable the unused second (work) flash node so the controller exposes a
single active soc-nv-flash child, matching the arrangement already used
for the psoc6 SoC devicetree.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Add the power node and the wake-up pins for all STM32C5 SoCs.
Wake-up pins 1, 2, 4 and 5 are common on all SoCs, pins 3, 6 and 7 are only
available on STM32C551 and higher.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Implements power management interface for MAX32 I3C driver.
To restore the peripheral after resuming from a suspend-to-ram state,
use the controller-mode enable bit to detect whether the I3C controller
has lost its state.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
According to the reference manual the s32 also
has the ptp clock, so add the node for it.
As the devicetree just describes the hardware,
independant of software and driver support,
we can add it without having a working driver for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
For the NXP MCXE31B mcu there is currently no
driver support for the ethernet controller, add it via
the generic dwc_mac driver.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the AON-domain MUB mailbox node for MCXL devices.
MUB is disabled by default and can be enabled by board devicetree files.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
The RTC timer present in mspm0l111x is RTC_b. This does not have power
enable register, and thus will crash on init without setting `ti,rtc-x`.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Remove the "bus-speed" and "bus-speed-data" CAN controller devicetree
properties, deprecated in Zephyr 3.7 when they were renamed to "bitrate"
and "bitrate-data".
The nested DT_PROP_OR() fallbacks in CAN_DT_DRIVER_CONFIG_GET() collapse
to a single DT_PROP_OR() on the new property names. Both bindings and the
header must change together, as can-fd-controller.yaml includes
can-controller.yaml.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
For the rpi5, you will need to use both the BCM2712 the RP1 pinctrl driver.
The process for selecting which to use is done in
`soc/brcm/bcm2712/pinctrl_soc.c`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Enabling the rp1 pinctrl also requires the bcm2712 pinctrl,
so add a minimal stub.
This does not perform any processing, but preserves the register
settings at reset.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add RCC driver for the STM32WL3x series with CLK_SYS
sources (HSI, RC64MPLL PLL and HSE), peripheral clock gates
and the reset controller, together with the st,stm32wl3-rcc binding.
Signed-off-by: Anders Frandsen <anfran@anfran.dk>
Add an EEPROM child driver for the Micro Crystal RV-3028 RTC.
The driver provides EEPROM read and write access through the
RV3028 MFD parent driver.
Signed-off-by: Janez Ugovsek <janez@ugovsek.info>
Add support for configuring ERFO in/out capacitance
through device tree on MAX32657.
Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Anu Biradar <anu.biradar@analog.com>
