Commit graph

8801 commits

Author SHA1 Message Date
Tamas Jozsi
2c43a00f65 boards: fix Bluetooth LE support on the SparkFun ThingPlus Matter MGM240
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Tamas Jozsi
e4dc7c9fb1 soc: silabs: Add support for the MGM240SD22VNA
Also introduce the framework to support other
Silicon Labs modules.

Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
2025-06-21 15:31:36 +02:00
Camille BAUD
8c385be293 soc: bflb: enable clock_control for bl60x
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-21 10:40:20 +02:00
Camille BAUD
46b5d05ae1 drivers: clock_control: Introduce bl60x clock driver
This introduces a clock_control driver for bl60x

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-21 10:40:20 +02:00
Francois Ramu
d63b6e774f dts: arm: stm32 reg definition for the st,stm32-ospi compatible
The st,stm32-ospi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32H7, stm32L4plus, stm32L5, stm32U5 series.
ospi1 is addressing max 256 MBytes from 0x90000000
ospi2 is addressing max 256 MBytes from 0x70000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Francois Ramu
c550baecb6 dts: bindings: flash controller size of the stm32 ospi nor
This change adds the size in Bits of the flash nor memory
for the st,stm32-ospi-nor compatible.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Francois Ramu
66b85e5a81 dts: bindings: flash controller stm32-xspi-nor compatible
Update the description of the bindings to match the
xspi-nor-flash node properties: size in expressed in Bits

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-20 14:41:41 -05:00
Camille BAUD
3787be931e drivers: display: Introduce SSD1363
This introduces a driver for the SSD1363 PMOLED controller

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-20 14:41:31 -05:00
Mario Paja
0637ec4821 drivers: i2s: stm32 sai add mclk-divider property
This property enables the user to configure the Master Clock Divider.

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2025-06-20 13:26:14 -04:00
Mathieu Choplain
f8db99339e dts: arm: st: stm32n6: change pinctrl binding
Use the new and appropriate "st,stm32n6-pinctrl" compatible for the pinctrl
in DTSI for STM32N6 series.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-20 13:21:55 -04:00
Mathieu Choplain
58baaa395f bindings: pinctrl: stm32: add binding for STM32N6 series pinctrl
Add a new binding for the pinctrl controller of STM32N6 series.

The specificity of this series is the "I/O retime" feature not present on
other series. This new binding exposes pinctrl properties to configure this
feature.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
2025-06-20 13:21:55 -04:00
Khaoula Bidani
1cfcdcb804 dts: arm: stm32u3: add entropy node as Random Number Generator
Add the true Random Number Generator (RNG) node for stm32u3 socs.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-20 08:52:15 +02:00
Khaoula Bidani
edac88658e dts: arm: st: u3: add adc node in dtsi file
all stm32u3 boards have only one and same
adc peripheral.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 22:27:35 -07:00
Fabrice DJIATSA
4866cfcc9d dts: arm: st: l5: update dtsi file with fdcan node
add FDCAN1 node in l5 dtsi file.

stm32l5 have same ip with stm32u5.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2025-06-19 14:02:07 +02:00
Fabrice DJIATSA
67c628d025 dts: arm: st: l5: add stm32l552xc dtsi file
This dts include file is for certain stm32 boards
such as the stm32l552zc,which have a memory size
of 256KB for both flash and RAM peripherals.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2025-06-19 14:02:07 +02:00
Khaoula Bidani
20d4ab149e dts: arm: st: u3: add dac node in dtsi file
all stm32u3 boards have only one and same
dac peripheral.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-19 13:57:36 +02:00
Pieter De Gendt
a540ee6143 drivers: hdlc_rcp_if: Add HDLC SPI adapter driver
Implement the HDLC over SPI adapter driver to support the Openthread RCP
with SPI communication.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-18 17:50:31 -04:00
cyliang tw
bf86f1f1c0 drivers: watchdog: support numaker m55m1x
Modify driver code to support m55m1x series.
Update m55m1x.dtsi, to add wdt node for wdt driver support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-06-18 09:29:20 -04:00
Hou Zhiqiang
2efe6ab3bf dts: arm64: nxp: add LPI2C DT nodes for imx91
Add device-tree nodes for LPI2C instance 1 ~ 8.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2025-06-18 09:12:38 -04:00
Camille BAUD
eb06f11a8f soc: bflb: fix bl60x using wrong mtime freq
use new timebase-frequency to fix the timebase of this SoC

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-06-18 09:12:26 -04:00
Robert Hancock
ba2f6f8945 edac: shell: Make more generic
The EDAC shell code previously contained a number of references to the
Intel IBECC driver. Make the shell code more generic to the defined EDAC
API, and make IBECC-specific code dependent on its config option.

Also make NMI control dependent on X86 as it is specific to that
platform.

Rather than looking for a node labeled "ibecc", the EDAC shell code
now simply requires that a chosen entry for "zephyr,edac" be present to
point to the desired device. The Intel Elkhart Lake DTS has been updated
to add this alias.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2025-06-18 09:09:40 -04:00
Robert Hancock
5ec82573ca drivers: edac: Add Synopsys EDAC driver
Add an EDAC driver for the Synopsys DDR memory controller, used in the
Xilinx MPSoC (ZynqMP) devices, to allow monitoring for ECC errors.

Note that currently only the compatible string used for the ZynqMP
(shared with Linux) is currently supported. Support for other Synopsys
core implementations can be added in the future.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2025-06-18 09:09:40 -04:00
Fin Maaß
4a468e93cd dts: treewide: fix missing use of underscores
in  #83352 a few bindings were not migrated,
fix that, as it will lead to ci fails.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-06-18 09:08:05 -04:00
Yangbo Lu
af181c5620 dts: arm: nxp_imx943_m33: add NETC ENETC support
Added NETC ENETC nodes, MDIO node, and scmi power node which will
be used to power up NETC MIX in dtsi file.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2025-06-18 07:37:24 +02:00
Swift Tian
69c14e37ac drivers: mspi: add ambiq mspi timing scan utility
The utility may be used during development stage to get
ambiq platform specific timing parameters for mspi devices.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-06-18 07:36:26 +02:00
Swift Tian
cc5c142535 drivers: mspi: add mspi is25xx0xx device driver
This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-06-18 07:36:26 +02:00
Swift Tian
8ef0792eec drivers: mspi: add APMemory APS Z8 pSRAM driver
The APS Z8 driver would just support APS51216BA for now.

Signed-off-by: Swift Tian <swift.tian@ambiq.com>
2025-06-18 07:36:26 +02:00
Jamie McCrae
5bc71e6e9b boards: nordic: nrf54l05: Change to use common dts partitioning file
Adds a common vendor dts file specifying the default partition
layout for nRF54L05-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Jamie McCrae
e542188ce9 boards: nordic: nrf54l15_ns: Change to use common dts partitioning file
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp_ns board targets and updates boards
to use this common file.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Jamie McCrae
124a803fc4 boards: nordic: nrf54l15: Change to use common dts partitioning file
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Jamie McCrae
9dc6040fcd boards: nordic: nrf54l10: Change to use common dts partitioning file
Adds a common vendor dts file specifying the default partition
layout for nRF54L10-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Jamie McCrae
0f0c80e931 dts: vendor: nordic: nrf54l10: Fix wrong size of NVM
Fixes the NVM size going beyond what the chip supports

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Jamie McCrae
a56cb0ad4d dts: vendor: nordic: nrf91xx_partition: Adapt to sub-partitions
Updates to use sub-partitions for TF-M slots

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-06-17 16:11:45 +02:00
Venkatesh Odela
b052a086a4 ethernet: phy: dp83867: Add support for configurable internal RGMII delays
Add support for setting RGMII RX and TX internal delays via DT properties:
`ti,rx-internal-delay` and `ti,tx-internal-delay`.

Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
2025-06-17 16:07:42 +02:00
Youssef Zini
1a7bac5b19 dts: arm: st: stm32mp2_m33.dtsi: add GPIO nodes
Add GPIO A-K nodes to the device tree for STM32MP2 SoC.
Note that GPIOs are disabled by default in the STM32MP2 SoC.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Youssef Zini
0972b23171 drivers: gpio: add mp2 gpio clock handling
Remove gpio clock management from the GPIO driver when running on the
cortex-m33 on the mp2 and gpio clocks are managed by the cortex-A, being
the resource manager, allowed by the Resource Isolation Framework (RIF).
Also add a specific binding for the mp2 gpio to make clock property
optional.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Youssef Zini
7f23ce2967 dts: clock_control: add mp2 rcc binding
Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Youssef Zini
38428c6f52 drivers: interrupt_controller: add stm32mp2 exti
Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Youssef Zini
898eaa9a3f dts: arm: st: stm32mp25*_m33.dtsi: add init dtsi
Add the initial device tree source include (dtsi) files for the
stm32mp25 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, RCC clock controller and NVIC interrupt
controller.

Key features:
- Set flash and RAM addresses to DDR memory.
- Adjust RCC peripheral address for non-secure context.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
2025-06-17 08:20:33 +02:00
Armando Visconti
a2d230bd88 drivers/sensor/: lis2dux12: support FIFO modes
Support three different FIFO contents which are selectable through
a new DT property, fifo-mode-sel, which may be set to one of the
following values:

    - 0x0 # 1x Accelerometer @12bit and 1x temperature @12bit samples
    - 0x1 # 1x Accelerometer @16bit sample
    - 0x2 # 2x Accelerometer @8bit samples (previous and current)

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2025-06-17 07:23:23 +02:00
Jiafei Pan
132d79615c dts: nxp: imx95_a55: add GPIO device nodes
Added all GPIO device nodes in i.MX 95 Cortex-A Core SoC dts.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-06-17 07:21:32 +02:00
Ioan Dragomir
92a11405f7 drivers: can: Add CAN support for max32662
Adapt MAX32690 driver to use Wrap_MXC_CAN_Init to handle differences
in the MSDK API (see analogdevicesinc/msdk#1306) between the
MAX32690 and MAX32662.

can_driver_api.timing_min required phase_seg1 >= 3 and phase_seg2 >= 2
when configuring CAN bit timing. Both microcontrollers covered by this
driver (MAX32662, MAX32690) support values down to 1 for both of these
timing parameters.

Refer to the docs for registers CAN_BUSTIM1, CANn_BUSTIM1.

Add a can0 node to the MAX32662 dtsi.

Signed-off-by: Ioan Dragomir <ioan.dragomir@analog.com>
2025-06-16 14:13:59 -04:00
Anıl Kara
b38a1f4a89 dts: arm: adi: Add CAN peripheral to max32690
This commit defines CAN peripheral as a devicetree node.

Signed-off-by: Anıl Kara <anil.kara@analog.com>
2025-06-16 14:13:59 -04:00
Anıl Kara
7f3b002210 drivers: can: Add max32xxx CAN driver
This commit adds CAN driver for max32xxx.

Signed-off-by: Anıl Kara <anil.kara@analog.com>
2025-06-16 14:13:59 -04:00
Mathias Markussen
00733cebc3 dts: Add hspi to STM32U5 chips including this
The SOCs including this dts all have hspi (xspi comatible)
peripheral included.

Signed-off-by: Mathias Markussen <mathias.markussen@st.com>
2025-06-16 14:03:42 -04:00
Tien Nguyen
5599bc2ecb drivers: gpio: Add support for RZ/V2N
Add support for RZ/V2N

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
2025-06-16 14:00:22 -04:00
Tien Nguyen
05289f40a7 drivers: pinctrl: Add support for RZ/V2N
Add support for RZ/V2N

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
2025-06-16 14:00:22 -04:00
Hieu Nguyen
b431204a6d dts: arm: renesas: Add support for Renesas RZ/V2N
Add devicetree to support for Renesas RZ/V2N

Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-06-16 14:00:22 -04:00
Khaoula Bidani
8144a6638a dts: bindings: flash: add STM32U3 flash controller
Add the Device Tree binding for the STM32U3 flash controller.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-16 13:59:38 -04:00
Khaoula Bidani
9b23a73184 dts: bindings: clock: add STM32U3 MSI
Add the Device Tree bindings for the
MSI clock of STM32U3 series.

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
2025-06-16 13:59:38 -04:00