Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The st,stm32-ospi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32H7, stm32L4plus, stm32L5, stm32U5 series.
ospi1 is addressing max 256 MBytes from 0x90000000
ospi2 is addressing max 256 MBytes from 0x70000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Update the description of the bindings to match the
xspi-nor-flash node properties: size in expressed in Bits
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use the new and appropriate "st,stm32n6-pinctrl" compatible for the pinctrl
in DTSI for STM32N6 series.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Add a new binding for the pinctrl controller of STM32N6 series.
The specificity of this series is the "I/O retime" feature not present on
other series. This new binding exposes pinctrl properties to configure this
feature.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
This dts include file is for certain stm32 boards
such as the stm32l552zc,which have a memory size
of 256KB for both flash and RAM peripherals.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Implement the HDLC over SPI adapter driver to support the Openthread RCP
with SPI communication.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The EDAC shell code previously contained a number of references to the
Intel IBECC driver. Make the shell code more generic to the defined EDAC
API, and make IBECC-specific code dependent on its config option.
Also make NMI control dependent on X86 as it is specific to that
platform.
Rather than looking for a node labeled "ibecc", the EDAC shell code
now simply requires that a chosen entry for "zephyr,edac" be present to
point to the desired device. The Intel Elkhart Lake DTS has been updated
to add this alias.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an EDAC driver for the Synopsys DDR memory controller, used in the
Xilinx MPSoC (ZynqMP) devices, to allow monitoring for ECC errors.
Note that currently only the compatible string used for the ZynqMP
(shared with Linux) is currently supported. Support for other Synopsys
core implementations can be added in the future.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Added NETC ENETC nodes, MDIO node, and scmi power node which will
be used to power up NETC MIX in dtsi file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
The utility may be used during development stage to get
ambiq platform specific timing parameters for mspi devices.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
This device driver supports ISSI is25w/lx032/64 series flash.
Only extended SPI mode(1s-1s-1s, 1s-8s-8s, 1s-1s-8s) is implemented.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Adds a common vendor dts file specifying the default partition
layout for nRF54L05-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp_ns board targets and updates boards
to use this common file.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L15-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds a common vendor dts file specifying the default partition
layout for nRF54L10-based cpuapp board targets and updates boards
to use this common file. This also drops the secure/non-secure split
in the partitioning as this was reducing NVM storage that is not
used by this board target and fixes the wrong flash field in
twister yaml files
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support for setting RGMII RX and TX internal delays via DT properties:
`ti,rx-internal-delay` and `ti,tx-internal-delay`.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Add GPIO A-K nodes to the device tree for STM32MP2 SoC.
Note that GPIOs are disabled by default in the STM32MP2 SoC.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Remove gpio clock management from the GPIO driver when running on the
cortex-m33 on the mp2 and gpio clocks are managed by the cortex-A, being
the resource manager, allowed by the Resource Isolation Framework (RIF).
Also add a specific binding for the mp2 gpio to make clock property
optional.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Add the initial device tree source include (dtsi) files for the
stm32mp25 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, RCC clock controller and NVIC interrupt
controller.
Key features:
- Set flash and RAM addresses to DDR memory.
- Adjust RCC peripheral address for non-secure context.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
Support three different FIFO contents which are selectable through
a new DT property, fifo-mode-sel, which may be set to one of the
following values:
- 0x0 # 1x Accelerometer @12bit and 1x temperature @12bit samples
- 0x1 # 1x Accelerometer @16bit sample
- 0x2 # 2x Accelerometer @8bit samples (previous and current)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Adapt MAX32690 driver to use Wrap_MXC_CAN_Init to handle differences
in the MSDK API (see analogdevicesinc/msdk#1306) between the
MAX32690 and MAX32662.
can_driver_api.timing_min required phase_seg1 >= 3 and phase_seg2 >= 2
when configuring CAN bit timing. Both microcontrollers covered by this
driver (MAX32662, MAX32690) support values down to 1 for both of these
timing parameters.
Refer to the docs for registers CAN_BUSTIM1, CANn_BUSTIM1.
Add a can0 node to the MAX32662 dtsi.
Signed-off-by: Ioan Dragomir <ioan.dragomir@analog.com>
Add devicetree to support for Renesas RZ/V2N
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
