Add the possibility to configure the interrupt gpio in one of the
two possiblities:
- GPIO_INT_EDGE_TO_ACTIVE
- GPIO_INT_LEVEL_ACTIVE
Default is GPIO_INT_EDGE_TO_ACTIVE, which matches with old fixed
configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add support for using RTI hardware as system timer:
- Add headers, driver code, Kconfig, and bindings for TI RTI Timer
- Make changes in CMakeLists.txt and Kconfig to support ti_rti_timer
- Add documentation and usage instructions in bindings file.
NOTE: Each RTI has 2 Counter blocks, 4 Counter Compare blocks.
This driver assumes that Counter block 0, Compare block 0 of
chosen RTI instance are used as RTI Timer.
Signed-off-by: Shreyas Shankar <s-shankar@ti.com>
Fix devicetree coding style regarding whitespaces through the tree.
This affects code snippets inside documentation, comments, error messages
as to encourage a style that passes CI. Follow-up of #101619
Signed-off-by: Josuah Demangeon <me@josuah.net>
Keep the RNG node disabled at the SoC level so board-specific
DTS files remain responsible for enabling the hardware when
appropriate.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Introduce new properties for ST HCI SPI to handle the new changes
required by x-nucleo-wba25a1 efficiently.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Added support for autanalog PRB for PSE84.
This implementation uses the shared autonomous controller (AC) MFD
with the other autanalog drivers.
The PRB is a programmable reference block inside the autonomous
(aut) analog subsystem. It is controlled using the autonomous
controller (AC), which is a programmable state machine. The AC is
shared across all autonomous analog peripherals including the
SAR, PRB, PTComp, CTB, and CTDAC.
The PRB contains two variable voltage references derived from
either VDDA(1.8V) or VGBR(0.9V). These need to be configured
together and accessed using the AC. A PRB MFD is used to bring
together the two voltage reference configurations. AC MFD then
references the combined PRB MFD configuration, and brings together
all other autanalog peripherals into a single AC setup for the
application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Updated pse84 autanalog sar to support muxed inputs.
This implementation uses the autonomous controller (MFD).
The autonomous controller (AC) a programmable state machine. The AC
is shared across all autonomous analog peripherals including the
SAR, PRB, PTComp, CTB, and CTDAC.
The device supports 8 direct GPIO inputs and 16 muxed inputs.
The muxed inputs can be sourced from pins or from interal signals
from other autanalog blocks. Muxed inputs can be chosen by assigning
channels 8 and above. Only 2 muxed channels are allowed per sequencer
when operating in high-speed mode. 1 muxed channel is permitted per
sequencer when operating in low power mode.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add I2C bus support to the BMI323 sensor driver. The BMI323
supports I2C communication with a dummy byte offset protocol
where 2 dummy bytes precede actual data in read operations.
Changes:
- Add bmi323_i2c.c/.h with I2C read/write and chip ID validation
- Add BMI323_BUS_I2C Kconfig option
- Update BMI323_DEVICE_BUS macro to handle I2C bus type
- Add bosch,bmi323-i2c.yaml device tree binding
The I2C implementation handles the dummy byte offset required
by the BMI323 when reading registers over I2C.
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Enable FlexCAN FD on the FRDM-MCXA577 board using PORT1_18 (CAN0_TXD)
and PORT1_19 (CAN0_RXD). Update the nxp_mcxa5x_common SoC DTS to
advertise FlexCAN FD capability present on MCXA5x devices.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Add a clarification about pll-charge-pump possible values since
value 0 is listed twice in the description, to state it is not a typo.
While at it, rephrase description of the other frequency range
related properties for consistency.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Set the status for usbhs_wrapper to disabled to avoid having to
explicitly disable it for boards that do not use it. The node
is enabled in nrf54lm20dk to keep it as before.
Signed-off-by: Andreas Vibeto <andvibeto@gmail.com>
For now, these registers are not yet used. They allows to clarify the
resources used by the NWP device.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
These pin are currently managed by the HAL. However, for the consistency,
this patch enforces their declaration in the Device Tree.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add the WICR node. The node is disabled by default; boards that boot
the Wi-Fi core should enable it and populate the WICR properties.
Add Wi-Fi LMAC and UMAC ROM regions. These provide the boot addresses
used by the WICR.
Add temporary Wi-Fi LMAC and UMAC patch partitions at the current
FPGA/bring-up addresses used by the patch binaries. These partitions
provide the ROM patch addresses used when generating WICR. The
placement is expected to be revisited when the Wi-Fi patch partition
and DFU architecture is finalized.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Add driver for Nordic USB PD Charging-Type detector.
This driver depends on the USBHS wrapper driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Commit 454fabb155 added nxp,crc devicetree nodes to shared dtsi
files, but the NXP HAL does not expose CRC_Type for every variant
that includes those files, breaking the build on MCXC444 and on
MIMXRT798S cm33_core1.
Move the crc node from nxp_rt7xx_common.dtsi into
nxp_rt7xx_cm33_cpu0.dtsi so it only reaches the core that has the
peripheral, and /delete-node/ &crc; in nxp_mcxc444.dtsi. Drop the
stale zephyr,crc chosen and &crc overrides from those board DTS
files.
Verified with twister tests/drivers/build_all -M all: the two failing
targets build clean, and frdm_mcxc242 and cm33_cpu0 still keep
CONFIG_CRC_DRIVER_NXP=y.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
eDMA2 on i.MX95 has 32 shared IRQs, each covering a pair of channels:
ch0/1 -> IRQ 128, ch2/3 -> IRQ 129, ch4/5 -> IRQ 130, ...
ch62/63 -> IRQ 159
The previous DTS only declared 3 IRQs (128, 129, 143) with an incorrect
channels-shared-irq-mask that mapped ch4/5 to IRQ 143 (ch30/31).
This caused an "Unhandled IRQn: 130" crash when SAI3 DMA transfers
(using edma2 ch4/5) were started.
Expand interrupts to cover all 32 channel-pair IRQs (128-159) and
update channels-shared-irq-mask accordingly.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
Add watchdog5 device node into mimx9596 m7, watchdog3/4 is assigned into
A55, only watchdog5 can be use by M7 cpu
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
3GPP TS 27.010 section 5.4.6.3.2 specifies a PSC frame exchange when
entering power save and section 5.4.7 specifies a flag-byte exchange
when exiting. modem_cmux blocks at T3 timeout on either half if the
peer does not implement the exchange, which is the case for modems
that manage sleep and wake out-of-band (hardware lines or
modem-control AT commands).
Add an opt-in DT property cmux-no-powersave-handshake (default off)
on the cellular-modem common binding. When set,
modem_cmux_runtime_pm_handler skips modem_cmux_send_psc and the T3
reschedule on entry and transitions directly to STATE_POWERSAVE;
powersave_wait_wakeup skips the wake-pattern transmission and the
STATE_RESYNC wait on exit and transitions directly to STATE_CONNECTED.
Signed-off-by: Paulo Santos <paulo.santos-ext@hexagon.com>
The Digital Filter for Sigma Delta Modulators (DFSDM) is dedicated to
interface external Σ∆ modulators.
It features:
* Up to 8 multiplexed input digital serial channels:
– SPI or Manchester-coded 1 wire interface
– clock output for Σ∆ modulators
* Up to 8 internal digital parallel channels:
– up to 16 bit resolution
– internal sources: memory (CPU/DMA write) data streams
* Adjustable digital signal processing
* Up to 24-bit output data resolution
* Signed output data format
* Continuous or one-shot conversion
* “regular” or “injected” conversions
* Analog watchdog
* Short-circuit detector
* Min/Max extremes detector
* DMA read access
* Interrupts for end of conversion, overrun, analog watchdog,
short-circuit, channel clock absence
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Add optional device tree option `recover-bus-on-init`,
it recovers the I2C bus during driver initialization.
Requires scl-gpios and sda-gpios to be defined on the same node.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Add optional device tree option `recover-bus-on-init`,
it recovers the I2C bus during driver initialization.
Requires scl-gpios and sda-gpios to be defined on the same node.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
This PR introduces the `sda-hold-time-ns` DeviceTree property for
DesignWare I2C controllers. The driver logic is updated to prioritize
this nanosecond configuration, calculating the necessary hardware clock
ticks at build time using the new `HOLD_TIME_TO_TICKS` macro. If the
property is not defined, it safely falls back to the legacy
`sda-hold-tx` tick configuration.
Fixes#83437
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
Set 'zephyr,min-timeout-cycles' to 32 cycles for the SysTick timer on
Realtek RTL8752H and RTL87x2G (Bee Famliy) SoCs.
Since these SoCs typically use a 32 kHz clock source for the SysTick
timer, the default driver limit (1024 cycles) imposes a ~31.25 ms
minimum wait time. By reducing this to 32 cycles, the minimum hardware
timeout is aligned with a 1ms kernel tick (at 1000 Hz).
This improvement enables functional tickless idle mode and ensures that
kernel timing-dependent tests can achieve the required 1ms resolution.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add support for configuring the minimum timer delay via the Devicetree
property 'zephyr,min-timeout-cycles'. This is particularly useful for
platforms using low-frequency clock sources (e.g., 32.768 kHz).
The driver's default MIN_DELAY is MAX(1024, CYC_PER_TICK / 16). On a
system with a 32.768 kHz clock and CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000,
CYC_PER_TICK is 32. This results in a MIN_DELAY of 1024 cycles, which
translates to a ~31 ms minimum timeout. This granularity is too
coarse for tickless operation and causes failures in tests that expect
sub-10ms precision.
This change allows boards to override this limit, enabling finer timing
resolution while maintaining the existing default for backward
compatibility.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Allow configuring the clock source for TI's dmtimer using syscon driver for
MMR writes. The new property "clksel" takes offset and value to select
the mux configuration.
This is required since there are no clock parent APIs in the clock
controller subsystem as of now.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Switch binding to zephyr,cellular-modem-device.yaml
- Use MODEM_DT_INST_PPP_DEFINE to properly associate PPP with the modem
device and preserve runtime PM integration
Signed-off-by: Luca Impagliazzo <Luca.Impagliazzo@telit.com>
Convert FlexSPI-backed flash partition tables on NXP boards from
"fixed-partitions" to "zephyr,mapped-partition" so that
FIXED_PARTITION_NODE() resolves to a CPU-mapped (AHB/XIP) address
instead of a flash-local offset. This lets MCUboot, settings/NVS, and
other partition consumers reach the partition through the FlexSPI AHB
window without the driver having to translate offsets at runtime.
Related-to: #107737
Signed-off-by: Albort Xue <yao.xue@nxp.com>
