dts: arm: st: add stm32u385 dtsi files
Provide support for the ST32U385 series Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit is contained in:
Khaoula Bidani
Daniel DeGrasse
parent
85e6cc421e
commit
496517c032
3 changed files with 278 additions and 0 deletions
239
dts/arm/st/u3/stm32u3.dtsi
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239
dts/arm/st/u3/stm32u3.dtsi
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/reset/stm32u3_reset.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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clk_msis: clk-msis {
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#clock-cells = <0>;
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compatible = "st,stm32u3-msi-clock";
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msi-range = <0>; /* 96MHz (reset value) */
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status = "disabled";
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};
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clk_msik: clk-msik {
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#clock-cells = <0>;
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compatible = "st,stm32u3-msi-clock";
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msi-range = <0>; /* 96MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <2>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32u3-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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/* maximum erase time(ms) for a 8K sector */
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max-erase-time = <5>;
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};
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};
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rcc: rcc@40030c00 {
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compatible = "st,stm32u5-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x40030c00 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@40032000 {
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compatible = "st,stm32g0-exti","st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x40032000 0x400>;
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num-lines = <16>;
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interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
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<15 0>, <16 0>, <17 0>, <18 0>,
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<19 0>, <20 0>, <21 0>, <22 0>,
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<23 0>, <24 0>, <25 0>, <26 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2000>;
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gpioa: gpio@42020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
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};
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gpiob: gpio@42020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
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};
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gpioc: gpio@42020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
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};
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gpiod: gpio@42020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
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};
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gpioe: gpio@42021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
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};
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gpiog: gpio@42021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021800 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
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};
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gpioh: gpio@42021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
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};
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB2, 14)>;
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resets = <&rctl STM32_RESET(APB2, 14)>;
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interrupts = <61 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 18)>;
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resets = <&rctl STM32_RESET(APB1L, 18)>;
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interrupts = <63 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 19)>;
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resets = <&rctl STM32_RESET(APB1L, 19)>;
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interrupts = <64 0>;
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status = "disabled";
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};
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lpuart1: serial@40042400 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x40042400 0x400>;
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clocks = <&rcc STM32_CLOCK(APB3, 6)>;
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resets = <&rctl STM32_RESET(APB3, 6)>;
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interrupts = <66 0>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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13
dts/arm/st/u3/stm32u385.dtsi
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13
dts/arm/st/u3/stm32u385.dtsi
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@ -0,0 +1,13 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/u3/stm32u3.dtsi>
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/ {
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soc {
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compatible = "st,stm32u385", "st,stm32u3", "simple-bus";
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};
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};
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26
dts/arm/st/u3/stm32u385Xg.dtsi
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26
dts/arm/st/u3/stm32u385Xg.dtsi
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/u3/stm32u385.dtsi>
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/ {
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sram0: memory@20000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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/* SRAM1 + SRAM2 */
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/* 192K + 64K */
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reg = <0x20000000 DT_SIZE_K(256)>;
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zephyr,memory-region = "SRAM0";
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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};
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};
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};
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