dts: arm: st: add stm32u385 dtsi files

Provide support for the ST32U385 series

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit is contained in:
Khaoula Bidani 2025-04-20 23:38:22 +02:00 committed by Daniel DeGrasse
commit 496517c032
3 changed files with 278 additions and 0 deletions

239
dts/arm/st/u3/stm32u3.dtsi Normal file
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/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/reset/stm32u3_reset.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(16)>;
status = "disabled";
};
clk_hsi48: clk-hsi48 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(48)>;
status = "disabled";
};
clk_msis: clk-msis {
#clock-cells = <0>;
compatible = "st,stm32u3-msi-clock";
msi-range = <0>; /* 96MHz (reset value) */
status = "disabled";
};
clk_msik: clk-msik {
#clock-cells = <0>;
compatible = "st,stm32u3-msi-clock";
msi-range = <0>; /* 96MHz (reset value) */
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <2>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
};
soc {
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller", "st,stm32u3-flash-controller";
reg = <0x40022000 0x400>;
interrupts = <6 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
write-block-size = <16>;
erase-block-size = <8192>;
/* maximum erase time(ms) for a 8K sector */
max-erase-time = <5>;
};
};
rcc: rcc@40030c00 {
compatible = "st,stm32u5-rcc";
clocks-controller;
#clock-cells = <2>;
reg = <0x40030c00 0x400>;
rctl: reset-controller {
compatible = "st,stm32-rcc-rctl";
#reset-cells = <1>;
};
};
exti: interrupt-controller@40032000 {
compatible = "st,stm32g0-exti","st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
reg = <0x40032000 0x400>;
num-lines = <16>;
interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
<15 0>, <16 0>, <17 0>, <18 0>,
<19 0>, <20 0>, <21 0>, <22 0>,
<23 0>, <24 0>, <25 0>, <26 0>;
interrupt-names = "line0", "line1", "line2", "line3",
"line4", "line5", "line6", "line7",
"line8", "line9", "line10", "line11",
"line12", "line13", "line14", "line15";
line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
<4 1>, <5 1>, <6 1>, <7 1>,
<8 1>, <9 1>, <10 1>, <11 1>,
<12 1>, <13 1>, <14 1>, <15 1>;
};
pinctrl: pin-controller@42020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x42020000 0x2000>;
gpioa: gpio@42020000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42020000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 0)>;
};
gpiob: gpio@42020400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42020400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 1)>;
};
gpioc: gpio@42020800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42020800 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 2)>;
};
gpiod: gpio@42020c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42020c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
};
gpioe: gpio@42021000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42021000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
};
gpiog: gpio@42021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42021800 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
};
gpioh: gpio@42021c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x42021c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 7)>;
};
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <61 0>;
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <63 0>;
status = "disabled";
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <64 0>;
status = "disabled";
};
lpuart1: serial@40042400 {
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40042400 0x400>;
clocks = <&rcc STM32_CLOCK(APB3, 6)>;
resets = <&rctl STM32_RESET(APB3, 6)>;
interrupts = <66 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

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/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/u3/stm32u3.dtsi>
/ {
soc {
compatible = "st,stm32u385", "st,stm32u3", "simple-bus";
};
};

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/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/u3/stm32u385.dtsi>
/ {
sram0: memory@20000000 {
compatible = "zephyr,memory-region", "mmio-sram";
/* SRAM1 + SRAM2 */
/* 192K + 64K */
reg = <0x20000000 DT_SIZE_K(256)>;
zephyr,memory-region = "SRAM0";
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};