Commit graph

502 commits

Author SHA1 Message Date
TOKITA Hiroshi
5c7a0ef888 drivers: interrupt-controller: add Nuclei ECLIC driver
Add support for the ECLIC interrupt controller
which is used with the Nuclei processor core.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
949d4b91d9 drivers: pinctrl: Support pinctrl with GD32VF103
Change the settings to support pinctrl on the GD32VF103.

- Split soc/arm/gigadevice/common/pinctrl_soc.h
  and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
  in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
  if GD32_HAS_AF(IO)_PINMAX was selected.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
TOKITA Hiroshi
c9c04e491e soc: riscv: Add initial support for GigaDevice GD32V SoC
Add GigaDevice GD32V SoC.
GD32V has non-standard CSR. It doesn't use common startup code.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-12-20 17:51:30 +01:00
Glauber Maroto Ferreira
dd04a328cf soc: riscv: esp32c3: dts: uart node refactoring
Not all boards use the same UART's defaults properties.

This commit updates device tree declarations by deferring
specific definitions to the board's DTS.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-12-09 19:57:10 -05:00
Ruibin Chang
fad78a2c07 ITE drivers/sensor: add tachometer driver for it8xxx2_evb
Add tachometer driver for it8xxx2_evb.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-29 08:25:19 -05:00
Tim Lin
e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Dino Li
6d8f1bf6d9 soc: it8xxx2: add support for eSPI driver
This supports eSPI slave, virtual wire, and peripheral functions.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-11-12 14:51:10 +01:00
Felipe Neves
b50cb2a537 drivers: counter: esp32: add support for esp32c3
to the unified esp32 counter driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-11 19:14:15 -05:00
Felipe Neves
857a188c76 drivers: watchdog: esp32: enabled esp32c3
support for the unified esp32 wdt driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-08 10:56:28 -05:00
Sylvio Alves
ab91612a6d driver: esp32: I2C code refactoring
Use i2c_hal functions to enable support for
multiple SoCs.

Use DT compat to enable I2C from device
tree configuration

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-05 14:07:09 -04:00
Sylvio Alves
27e44acda1 clock: esp32: unify clock control for all espressif socs
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-04 15:21:26 -04:00
Felipe Neves
0a0fed7879 drivers: spi: esp32: add esp32c3 support
to the esp32 spi unified driver

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-01 21:47:26 -04:00
Tim Lin
70fda06c73 ITE: soc/power: add power management
Add the power state of deep doze. When system enters deep doze, the
clock of CPU and EC can be stopped to reduce power consumption. And
enable the UART Rx WUI before entering deep doze to wake up EC and
CPU.

Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters
deep doze mode.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-29 22:55:28 -04:00
Felipe Neves
4c069b9894 drivers: serial: add support for esp32c3
into esp32_serial unified driver

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-29 16:09:09 -04:00
Glauber Maroto Ferreira
1af506dd32 soc: riscv: esp32c3: drivers: flash: add support
to host SPI Flash driver.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-10-28 06:47:21 -04:00
Felipe Neves
1e328fe109 clock_control: esp32c3: added clock control
gating driver support for esp32c3 SoC family

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-27 15:09:08 -04:00
Henrik Brix Andersen
95226c056f dts: riscv: neorv32: add trng devicetree node
Add devicetree node for the NEORV32 True Random Number Generator (TRNG).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-26 17:53:15 -04:00
Henrik Brix Andersen
b5d6f7f185 dts: riscv: neorv32: add gpio nodes
Add devicetree nodes for the NEORV32 GPIO device.

The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit
wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO
devices with a nexus devicetree node mapping pins 0 to 31 to the device
handling the lower half, and pins 32 to 63 to the device handling the
upper half.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Henrik Brix Andersen
85963cbc02 dts: riscv: neorv32: add uart devicetree nodes
Add devicetree nodes for the NEORV32 UART devices.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Henrik Brix Andersen
a281dbfb6d soc: riscv: privilege: add neorv32 processor suppport
Add support for the open-source NEORV32 RISC-V compatible processor
system (SoC).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Felipe Neves
ed55ee95e9 boards: riscv: esp32c3: added button support
in samples for esp32c3 devkitm_board using GPIO9

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-05 19:24:38 -04:00
Felipe Neves
9768e98001 drivers: gpio_esp32: added support for esp32c3
in the gpio drivers and pinmux for esp32 chip series

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-05 19:24:38 -04:00
Felipe Neves
16be75b68f dts: added dts binding for esp32c3
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Felipe Neves
d4ed7f69d4 drivers: entropy: esp32: enable rng driver
for esp32c3 allowing wifi subsystem to use inside
its driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-09-30 06:39:55 -04:00
Ruibin Chang
d16ae76d30 ITE drivers/kscan: add keyboard scan driver for it8xxx2_evb
Add keyboard scan driver for board it8xxx2_evb.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-09-28 19:53:15 -04:00
Katsuhiro Suzuki
981d10f232 dts: riscv: fix irq number of UART and SPI for SiFive FU740
This patch fixes wrong PLIC irq number of UART and SPI for SiFive
FU740 on HiFive Unmatched. Use samples/subsys/console/echo for
testing.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-18 09:15:15 -04:00
Katsuhiro Suzuki
ca853af0b9 soc: riscv: add initial support for SiFive Freedom U740
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Katsuhiro Suzuki
82f75ed337 soc: riscv: add initial support for SiFive Freedom U540
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Yuriy Vynnychek
587304836d dts: riscv: add Telink B91 I2C driver support
Added I2C driver DTSI support for Telink B91 platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-09-01 06:36:56 -04:00
Jim Shu
e4cb3469d6 dts: riscv: add DTS and related bindings of andes_ae350 soc
Add DTSI file of andes_ae350 SoC and bindings of GPIO driver.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-30 13:40:14 -04:00
Yuval Peress
74b9a607b4 drivers: bbram: Add it8xxx2 BBRAM driver implementation
Note that the it8xxx2 does not support a status register so that
functionality is omitted.

This change also adds driver tests that build both the npcx and it8xxx2
drivers.

Signed-off-by: Yuval Peress <peress@chromium.org>
2021-08-30 11:35:23 -04:00
Tim Lin
033eb55aca ITE: riscv: it8xxx2: declare gctrl dts node and registers
Add general control(gctrl) node in dts, and declare gctrl registers

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-25 18:04:37 -04:00
Yuriy Vynnychek
95b6a2fa54 dts: riscv: telink_b91: transform labels to uppercase
Transformed all dts labels to uppercase.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-20 06:23:24 -04:00
Yuriy Vynnychek
77df331cc2 dts: riscv: add Telink B91 SPI driver support
Added SPI driver DTSI support for Telink B91 platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-19 17:18:23 -04:00
Martí Bolívar
bc27139a4b dts: riscv32-litex-vexriscv.dtsi: drop 'spinalhdl' compatible
This has an unrecognized vendor prefix which does not seem to serve
any purpose. Removing it is a way forward to turning warnings into
errors on unrecognized vendor prefixes.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-17 17:51:57 -04:00
Martí Bolívar
30de558824 dts: rename 'vexriscv,intc0' compatible to 'vexriscv-intc0'
As far as I can tell, 'vexriscv' does not name a vendor:

https://github.com/SpinalHDL/VexRiscv

It also doesn't seem entrenched enough to merit a special case
exception to the de factor rule 'the "vnd,foo" namespace is for
vendors'. This is open to debate and we can revise as needed in the
future, but for now let's just rename the compatible to avoid
triggering warnings/errors about unknown vendors.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-17 17:51:57 -04:00
Martí Bolívar
3422b2d161 dts: fix 'sifive' compatibles
It's supposed to be lowercase.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-17 17:51:57 -04:00
Tim Lin
6a1262198a ITE: drivers/i2c: it8xxx2: move pinctrls macro to soc_dt.h
This PR will change accessing the related pinctrl macro from soc_dt.h
And the pinctrl of SCL and SDA were got from pinctrl-0 and pinctrl-1,
respectively. Change it to get from pinctrl-0 only.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-17 17:51:17 -04:00
Sylvio Alves
651b448131 dtsi: esp32c3: added missing cell defs
missing address and cell size definition causes
testing failures.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Yuriy Vynnychek
0830738975 dts: riscv: add Telink B91 PWM driver support
Added PWM driver DTSI support for Telink B91 platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-05 16:11:41 +02:00
Yuriy Vynnychek
2b1548d05d dts: riscv: add Telink B91 Entropy driver support
Added Entropy driver DTSI support for Telink B91 platform

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-04 15:45:32 +02:00
Yuriy Vynnychek
d011e782c7 dts: riscv: add Telink B91 IEEE802154 driver support
Added IEEE802154 driver DTSI support for Telink B91 platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-08-04 11:58:02 +02:00
Felipe Neves
d368087fc0 drivers: serial: added minimal uart driver for esp32c3
based on uart rom functions, also enable console driver
on top if this driver enabling logging

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-03 11:20:06 -05:00
Tim Lin
e300c8ecbb ITE: dts/riscv it8xxx2: add pinmux control of SHI
Add pinmux control for SHI alternate function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-07-27 17:42:47 -04:00
Ruibin Chang
21f0f958fe ITE drivers/ite_it8xxx2_timer: re-write ite timer driver
Re-write ite timer driver.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Yuriy Vynnychek
77bd56f9b1 dts: riscv: add basic dts support for new Telink B91 platform
CPU, Power, GPIO, Serial and Pinctrl dtsi support for new
Telink B91 RISC-V platform.

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-07-21 05:37:12 -04:00
Tim Lin
abe27c5bca ITE: driver/i2c: add I2C recovery function
Use GPIO output high and low to simulate I2C start and stop
conditions to restore i2c to normal.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-07-14 07:32:16 -04:00
Tim Lin
8fdcc11d6b ITE: drivers/i2c: create pinmux phandle to the I2C driver node
Create the pinmux phandle to the I2C driver node in the
devicetree. When the pinmux_pin_set function in
i2c_it8xxx2_init can refer to the setting of this phandle.
It is more flexible to use.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-07-14 07:32:16 -04:00
Felipe Neves
132ab922a8 drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
c23b46a78a dts: riscv: espressif: correct sram0 compatible label to mmio-sram
And removes the odd esp32c3 competible from it

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00