Adds the pwrmgr devicetree node. This is a simple binding that holds
only the address of the registers for now.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
Adds the AON Timer device in the OpenTitan Earlgrey device tree.
Adds overlay files to enable the watchdog and set the alias to
`watchdog0`.
Adds the AON timer (watchdog part) to the supported features section
of the OpenTitan documentation.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
This commit moves the `mpfs-icicle.dtsi` file to a common `microchip`
directory and updates include paths in the `mpfs_icicle` board
devicetree.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The current configuration is too long and will block soc from
entering sleep mode. This change was made to get better power
number on EVB.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The alternate pins of UART2 have been remapped, and the remapped
alternate pins must be added to the pinctrl map.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Microchips PolarFire-SoC Icicle Kit has 4x UART interfaces available
via single micro USB and 1x UART for programming and debugging via micro
USB. Add the remaining UARTs to the Devicetree
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Some lines of the mpfs_icicle Devicetree contained a jumble of white
space and tabs. Just use tabs
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Change the preprocessor identifier from CONFIG_SOC_ESP32C3 to
SOC_GDMA_SUPPORTED so it can include ESP32S3 in GDMA routines.
Remove hardcoded values from hal calls to use dma_host instead.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add overlay for the esp32c3 board to die_temp_polling sample.
- Add aliases for the die_temp_polling sample to esp32c3 dtsi.
Testing Environment:
esp32c3-devkitC-02
Signed-off-by: Hiroki Tada <tada.hiroki@fujitsu.com>
Microchip's PolarFire SoC has a core complex consisting of one e51
monitor core and four u54 application cores. Add the remaining cpu nodes
to mpfs-icicle device tree. Add the software and timer interrupt irq's
to the clint for the additional cpu nodes.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This board is confirmed to build and run simple applications in
RTL simulation as described in the included board documentation.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Add kscan pins gpio driver for KSI[7:0], KSO[15:0] pins that
they can be configured to gpio mode. These pins registers address,
bit fields and function are different from GPIO group, so I create
a new compatible driver for these pins.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The interrupt and watchdog registers of the it82xx2 will be
remapped, so these device nodes should be separated to
it81xx2 from it8xxx2. it8xxx2 dtsi are common settings
for it81xx2 and it82xx2.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit adds the support for host commands being transported
by the Serial Host Interface on the IT8xxx2 SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
The GCR, PINCTRL, I2C and WUC registers of the it82xx2 will be remapped,
so these device nodes will not be in the it8xxx2.dtsi, these should be
separated to create a it81xx2.dtsi.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Support for the measuring the CPU die temperature
for the ESP32 targets S2,C3. The ESP32 support
was ommited due to lack of offset calibration.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
