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576 commits

Author SHA1 Message Date
Jimmy Zheng
7edb310d02 arch: riscv: custom: add T-Head Xuantie CSR support 
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:

1. Rename Kconfig name
   CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
   a. arch/riscv/custom/thead/Kconfig: for T-Head extension
   b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
      (e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
 2025-10-13 11:26:28 -04:00
Jimmy Zheng
7ee9fd978c soc: telink: tlsr951x: use RISC-V custom CSR common code 
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:

1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
 2025-10-13 11:26:28 -04:00
Camille BAUD
63a52052df dts: bflb: Add bflb,l1c to bl60x and bl70x 
Adds BL60x and BL70x cache nodes

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-10-09 09:38:21 +02:00
Jacky Lee
9cde077512 soc: Add Egis et171 
This is a SOC based on AE350. In addition to the core, some
modifications have been made to the peripheral functions,
including the integration of built-in USB.

Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
 2025-10-08 12:15:44 +02:00
Raffael Rostagno
a71f2bae30 dts: bindings: counter: esp32: Fix compatible name 
Fix compatible name on device tree, to allow RTC timer based
counter driver to be enabled. Disable rtc_timer node for all
devices to keep standard.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-10-07 12:47:45 +02:00
Daniel Schultz
15aa152669 dts: riscv: aesc: elemrv-n: Add GPIO Controller 
ElemRV-N has a GPIO controller with a total of 12 pins.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
 2025-10-06 20:03:28 +03:00
Raffael Rostagno
1f91cfea21 dts: pm: esp32h2: Add power states 
Add power states for PM.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-10-06 20:00:52 +03:00
Raffael Rostagno
18dbda57d8 soc: esp32h2: Add BT support 
Add bluetooth support to ESP32-H2.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-09-30 19:37:19 +02:00
Andrew Featherstone
b7217a061f dts: bindings: timer: rp2350: Add machine timer for RP2350 
The RP2350's Hazard3 (RISC-V) cores use the mtime-based RISC-V timer.

Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
 2025-09-29 12:30:28 -04:00
Andrew Featherstone
5df091b7b1 dts: rp2350: Add DTSI for using two Hazard3 cores 
Add a DTS fragment to support defining a RP2350 series SoC with two
Hazard3 cores in use.

Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
 2025-09-29 12:30:28 -04:00
Sylvio Alves
df0a88994d dtsi: espressif: add RNG peripheral clock reference 
Adds default clock module reference for Espressif SoCs.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
 2025-09-29 05:50:56 +02:00
Ren Chen
1b7170b81b dts: ite: it82000: add pinctrl_q and power_ctrl_elpm nodes 
as title.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
 2025-09-26 11:07:54 +02:00
Raffael Rostagno
bbea66edae dts: esp32h2: Add ieee802154 support 
Add ieee802154 support for ESP32-H2.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-09-22 17:52:46 -04:00
Ren Chen
de93d4f41c soc: ite: it82xx2: add it82000.bw variant support 
as title.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
 2025-09-19 08:35:10 -04:00
Camille BAUD
e5384cf791 dts: bflb: Update GPIO nodes for bl70x and bl60x 
Rename node to reflect specificity, remove unused

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-09-14 17:02:11 +02:00
Kyle Micallef Bonnici
9f19763bfd devicetree: format SoC-level files in dts/riscv 
Applying dts-linter results for SoC-level files in

dts/riscv

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
b419c514b6 devicetree: format files in dts/riscv/wch 
Applying dts-linter results for files in

dts/riscv/wch

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
81679451ec devicetree: format files in dts/riscv/telink 
Applying dts-linter results for files in

dts/riscv/telink

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
c52ced12b6 devicetree: format files in dts/riscv/starfive 
Applying dts-linter results for files in

dts/riscv/starfive

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
8019bce857 devicetree: format files in dts/riscv/sifive 
Applying dts-linter results for files in

dts/riscv/sifive

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
2a120b5588 devicetree: format files in dts/riscv/sensry 
Applying dts-linter results for files in

dts/riscv/sensry

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
64207962fc devicetree: format files in dts/riscv/qemu 
Applying dts-linter results for files in

dts/riscv/qemu

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
b0840d2e63 devicetree: format files in dts/riscv/openisa 
Applying dts-linter results for files in

dts/riscv/openisa

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
495baba6fd devicetree: format files in dts/riscv/openhwgroup 
Applying dts-linter results for files in

dts/riscv/openhwgroup

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
224c97bb0f devicetree: format files in dts/riscv/nordic 
Applying dts-linter results for files in

dts/riscv/nordic

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
08a07b841b devicetree: format files in dts/riscv/niosv 
Applying dts-linter results for files in

dts/riscv/niosv

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
13e0fa4653 devicetree: format files in dts/riscv/microchip 
Applying dts-linter results for files in

dts/riscv/microchip

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
c6bda076b3 devicetree: format files in dts/riscv/lowrisc 
Applying dts-linter results for files in

dts/riscv/lowrisc

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
e7cb1f291b devicetree: format files in dts/riscv/ite 
Applying dts-linter results for files in

dts/riscv/ite

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
b8e1165d45 devicetree: format files in dts/riscv/gd 
Applying dts-linter results for files in

dts/riscv/gd

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
700bc8a7fa devicetree: format files in dts/riscv/espressif 
Applying dts-linter results for files in

dts/riscv/espressif

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
184f5ec1ec devicetree: format files in dts/riscv/efinix 
Applying dts-linter results for files in

dts/riscv/efinix

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
db10f20e5d devicetree: format files in dts/riscv/bflb 
Applying dts-linter results for files in

dts/riscv/bflb

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Kyle Micallef Bonnici
6627ef9546 devicetree: format files in dts/arm64/ti 
Applying dts-linter results for files in

dts/arm64/ti

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
 2025-09-12 19:23:13 -04:00
Camille BAUD
e0ca880329 dts: bflb: Fix GPIO node for bl61x 
makes gpio driver work for bl61x

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-09-06 10:35:17 +02:00
Raffael Rostagno
1c0e877351 dts: esp32h2: Add peripherals 
Add device tree entries for the following peripherals:

- ADC
- I2C
- I2S
- LEDC PWM
- MCPWM
- PCNT
- SPI
- DMA
- TWAI
- USB serial

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-09-02 21:41:09 +02:00
Tim Lin
d3d334c584 drivers/bbram: Enable bbram driver for it51xxx series 
The BBRAM driver of it51xxx is compatible with it8xxx2.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
 2025-09-02 12:33:48 +02:00
Raffael Rostagno
5bd4741c83 soc: esp32h2: Add initial support 
Add initial support files for ESP32-H2 SoC.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
 2025-08-26 22:07:36 +02:00
Camille BAUD
71be3c2823 dts: bflb: fix bad uart device address 
4 didnt become a 2 like it should have

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-23 05:10:56 +02:00
Kevin Wang
06bec271d9 drivers: dma: atcdmac300: Upgrade atcdmac driver to support series device 
1. Upgrade the ATCDMAC driver to make it compatible with multiple
   ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.

Signed-off-by: Kevin Wang <kevinwang821020@google.com>
 2025-08-21 15:58:35 +02:00
Ren Chen
d860b6f598 dts: ite: it51xxx: set high-level triggered mode for spi0 node 
This commit sets the interrupt mode to high-level
triggered, as fifo mode is enabled by default
(CONFIG_SPI_ITE_IT51XXX_FIFO_MODE=y) and the fifo
mode only supports high-level triggered.

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
 2025-08-21 06:51:59 +02:00
Camille BAUD
1e511e4bfe dts: uart: Add uart node to BL70x 
Adds the uart node for BL70x

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 16:30:48 +02:00
Camille BAUD
78e68d6c21 dts: clock_control: Add bl70x clock nodes and bindings 
This adds the clock_control nodes and bindings

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 16:30:48 +02:00
Camille BAUD
f139e5a868 dts: pinctrl: Add bl70x pinctrl node 
This adds the pinctrl node

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 16:30:48 +02:00
Camille BAUD
c36bd29a19 dts: syscon: Add BL70x efuse node 
Adds the syscon node

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 16:30:48 +02:00
Camille BAUD
c1d20a52a0 dts: bflb: Add bl70x dts 
Introduce most basic DTS for BL70x

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 16:30:48 +02:00
Camille BAUD
f3f434b4d5 dts: uart: Add uart nodes to BL61x 
Adds the uart nodes for BL61x

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 13:45:26 +02:00
Camille BAUD
559ad926c1 dts: clock_control: Add BL61x clock nodes and bindings 
This adds the clock_control nodes and bindings

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 13:45:26 +02:00
Camille BAUD
f0df862788 dts: pinctrl: Add bl61x pinctrl node 
This adds the pinctrl node

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 13:45:26 +02:00
Camille BAUD
d57bf82360 dts: syscon: Add BL61x efuse node 
Adds the syscon node

Signed-off-by: Camille BAUD <mail@massdriver.space>
 2025-08-20 13:45:26 +02:00