Unlike the esp32c6, the esp32h2 did not select RISCV_PMP. Its
linker script also lacked the PMP alignment, userspace, kobject
and rom-section includes, and no PMP region covered the ROM, IRAM
text or flash rodata, so user mode could not be used.
Select RISCV_PMP with 16 slots and unlocked global entries, as on
the esp32c6. Describe the 128 KB ROM as a soc_rom memory region,
map it, the IRAM text and the flash rodata as regions shared by
both modes, and add the missing linker script includes.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move the fixed SYS_CLOCK_HW_CYCLES_PER_SEC values of the SoC and board
Kconfig files into the timebase-frequency property of the cpus node,
which the kernel uses as default for SYS_CLOCK_HW_CYCLES_PER_SEC.
The value of CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is unchanged for every
board target, checked by comparing the generated .config of all board
targets before and after the change.
Assisted-by: Claude:claude-opus-5.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Enable the IEEE 802.15.4 radio on the BL70x (BL702) series: add the
ieee802154 devicetree node, compile the RF/platform shim, link the
lmac154/RF blobs, and place the timing-critical lmac154 .tcm_code in ITCM
(otherwise those input sections become orphans at an unloaded address).
Provide CONFIG_BT_HCI_DRIVER_LOG_LEVEL for 802.15.4-only builds so the
shared BLE/802.15.4 platform shim compiles without Bluetooth enabled.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Enable the IEEE 802.15.4 radio on the BL70xL (BL702L) series: add the
ieee802154 devicetree node, compile the RF/platform shim, place the
timing-critical lmac154 code in ITCM, and link the lmac154/RF blobs.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Enable the IEEE 802.15.4 radio on the BL61x (BL616) series: add the
ieee802154 devicetree node, RF/PHY init via the shared wl_api blobs, the
TCM code section, and link the lmac154 blob. The GLB reset / memcpy shims
required by the BL616 blobs live with the other HAL shims.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the SoC-side glue for the BL602 wifi4 firmware blob: AON RF
power-on, PHY power tables fed from devicetree, the firmware scheduler
task with the wifi_main bring-up wrap, MAC HW DMA-dead recovery, the
WIFI_RAM linker sections, and the IPC glue the wifi4 driver core hooks
into (shared-environment seeding, the E2A mailbox ISR, firmware quirk
workarounds and the TX path with the txl_cntrl_push redirect the blob
needs to put frames on air).
The bl60x_em_8kb_wifi.dtsi snippet enables the WiFi MAC alongside the
8 KB BLE exchange memory: EM keeps the top 8 KB of RAM and WIFI_RAM
covers the 32 KB below it at the vendor ram_wifi origin (0x42042000),
with all_ram/sram0 scaled down so the linker enforces the boundary.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The SiFive E24 implements the A extension but only supports atomic
operations in its tightly-integrated memories; an AMO issued to OCRAM
bus-faults. Drop "a" from riscv,isa-extensions so RISCV_ISA_EXT_A is
not enabled from devicetree and the toolchain links the AMO-free
multilib (the kernel already uses ATOMIC_OPERATIONS_C on this SoC).
This replaces the RISCV_ISA_EXT_A override previously carried in
soc/bflb/bl60x/Kconfig.defconfig.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the bflb,bt-hci controller node (disabled by default) and a
bl808_em_32kb.dtsi include that trims 32 KB of WRAM off system RAM for
the BLE Exchange Memory, mirroring the bl60x and bl61x EM includes.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add g-rx-fifo-size, g-np-tx-fifo-size and g-tx-fifo-size required
properties to snps,dwc2 compatible. Property names are the same as used
in Linux because Zephyr aims for devicetree source compatibility with
other operating systems.
Specifying fifo sizes in devicetree greatly reduces necessary driver
complexity and allows application developer to adjust the sizes if
necessary to best utilize underlying hardware.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add zkr to the ISA extensions of the 32-bit, 32-bit E and 64-bit QEMU
virt machines, including the AIA variant which overrides the list. The
-cpu argument of QEMU is derived from this property, so QEMU implements
the seed CSR and the qemu_riscv32, qemu_riscv32e and qemu_riscv64
boards get an entropy driver.
Tested with tests/drivers/entropy/api on qemu_riscv32, qemu_riscv32e,
qemu_riscv64 and their smp, aia-imsic, aia-direct, smode and opensbi
variants.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit introduces SHA completion interrupt handling
instead of disabling global interrupts and polling the status
register. It also stores the register base and synchronization
state (semaphore) in the device configuration and device
data structures, respectively.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The hp cores only implement the Zb extensions and Zcb from silicon
revision v3.0 on, so declaring them in esp32p4_common.dtsi would emit
instructions the v1.3 boards cannot execute. Add an esp32p4_rev3.dtsi
next to esp32p4.dtsi for v3.x boards to include instead; the Kconfig
symbols that build -march default from these properties.
Move the base and extension lists up to the cpus node, where the
devicetree spec puts properties identical on every hart, so the v3.x
dtsi overrides one node instead of two.
Zcmp and Zcmt stay out. The cores reverse cm.push and mis-execute
cm.popret, and the workaround is -mno-cm-push-reverse/-mno-cm-popret,
which only the Espressif toolchain has; Zcmt is unknown to the SDK
binutils.
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The pixel processing accelerator scales, rotates, mirrors and
blends blocks of pixels, and moves them with its own 2D DMA.
It is driven from graphics code rather than through a device, so
the node describes the registers and the transfer done interrupt
it needs and nothing more. Boards that use it enable it.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the clock controller and syscon to the Hydrogen platform.
Enable both by default and reduce the syscon priority to load
this driver before the clock controller.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add support for the C-DAC THEJAS32 SoC, based on the VEGA ET1031 32-bit
(RV32IM) single-core, in-order RISC-V processor developed under India's
Digital India RISC-V (DIR-V) programme.
The image is loaded into and executed from the 256 KB internal SRAM,
which is mapped at 0x00200000, so execute-in-place is not used. The
kernel system clock is driven by the CLINT machine timer.
THEJAS32 follows the RISC-V privileged specification for trap handling
but uses a custom (non-PLIC) interrupt controller, so the SoC does not
select RISCV_PRIVILEGED. Instead it provides its own reset entry, machine
trap acknowledge and interrupt-management code that routes second-level
interrupts to the THEJAS32 interrupt controller driver and first-level
interrupts to the mie CSR.
The memory map and register definitions were cross-checked against the
C-DAC VEGA board support package.
Signed-off-by: Anuj Deshpande <anuj@makerville.io>
Derive SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree.
This allows to override the system clock frequency.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
If flpr is used on nRF54L series, it will most likely use
IPC service to communicate with the cpuapp. Having the default
configuration simplifies the setup in tests and applications.
ICBMSG backend is used which has the smallest code and the most
features.
Add setting of IPC node to nordic-flpr snippet. After this change
when nordic-flpr is used then only CONFIG_IPC_SERVICE=y is needed
to have IPC communication up and ready.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
If flpr is used on nRF54L series, it will most likely use
IPC service to communicate with the cpuapp. Having the default
configuration simplifies the setup in tests and applications.
ICBMSG backend is used which has the smallest code and the most
features.
Remove ipc node from bsim targets as they do not support VPR.
Add setting of IPC node to nordic-flpr snippet. After this change
when nordic-flpr is used then only CONFIG_IPC_SERVICE=y is needed
to have IPC communication up and ready.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
All five harts on each SoC implement the cycle, time and instret
counters, but the SoC manuals predate the Zicntr name and so never use
it. The devicetree inherited that gap and left the extension
undeclared.
Declaring it enables CONFIG_RISCV_ISA_EXT_ZICNTR, which the arch code
uses to decide whether the counters can be exposed to user mode.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Drop the espressif/<soc>/<soc>_<module>.dtsi files in favor of one
<soc>.dtsi per SoC, and matching SOC_ESP32*_<MODULE> symbols in
favor of the plain SoC symbol. SOC_PART_NUMBER now reports the SoC.
Each board instead states its own flash, giving both reg and ranges
because the SoC dtsi no longer sets either, and its own psram size where
it has one.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Enable the esp32 HCI driver on the ESP32-C61: extend the
controller Kconfig gates, report the C61 vendor hardware
variant id, add the hci devicetree node and enable it on the
esp32c61_devkitc board. The C61 BLE controller reuses the C6
controller sources and blobs through the hal.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Enable the esp32 Wi-Fi driver on the ESP32-C61: extend the FTM
and mesh Kconfig gates, add the wifi devicetree node and enable
it on the esp32c61_devkitc board.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Rework the sleep path timing calculation to improve precision by
calculating sleep time and wakeup margins with the right time
references.
When CONFIG_ESP32_PM_SLP_IRAM_OPT is enabled, the early wake path
(RTC timer re-enable, GPIO restore, and post-exit ops) is also
placed in IRAM so resume does not refill from flash after CPU
power down.
Light sleep DT exit-latency-us is 0 so PM does not shorten the
budget; the RTC lead is applied in power.c. C5 keeps flash powered
in light sleep via SOC_ESP32_PM_FLASH_KEEP_POWER_IN_LSLP.
Assisted-by: Grok:4.6
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
RV_TIMER_BASE is derived from the mtimer devicetree node but the
register offsets used with it are relative to the rv_timer base at
0x40100000. Since commit f11f68eade that node describes only the
mtime and mtimecmp registers, so DT_REG_ADDR() returns 0x40100110
rather than the timer's base. The function soc_early_init_hook()
therefore writes CTRL to 0x40100114 and INTR_ENABLE0 to 0x40100210,
instead of 0x40100004 and 0x40100100.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Add support for the comparator peripheral found in WCH CH5xx SoCs.
This commit also extends the comparator API with a child API to allow
dynamic configuration of the negative reference voltage. This feature
is intended to enable software-based ADC implementations using the
comparator peripheral.
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
The WCH ESIG unit holds a 96 bit unique ID. Expose via the hwinfo
driver.
The WCH RCC unit accumulates the recent reset causes. Expose via the
hwinfo APIs.
Tested on the `bluepillplus_ch32v203` by running
`tests/drivers/hwinfo/api` and verifying the ID matches minichlink, and
that pressing the reset button makes the cause change.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V series has between 16 KiB and 480 KiB of in-place
programmable program flash. Add a driver that implements the Zephyr
flash API, the appropriate Devicetree nodes, and overlays for the
`flash_shell` sample.
For the sample, trim back the default settings to fit within the ~64
KiB of flash and 8 to 20 K of RAM and add test partitions.
Use Devicetree to define the erase value. For the 003 and 006, this is
the common 0xFF but for the 20x/30x this is 0xE339. The flash API
works correctly on the 20x/30x but systems that require the erase
value to be a single byte, or assume that it is 0xFF, will not. This
can be addressed in future PRs.
Tested on the ch32v00x_core and bluepillplus_ch32v203 board by loading
the sample and running `flash test ...`. The
tests/drivers/flash/common test passes on the bluepillplus except for
the erase test which fails due to the ch32v203's half word erase
pattern.
Signed-off-by: Michael Hope <michaelh@juju.nz>
GPIO controllers in the PIC64GX and SmartFusion2 DTS files still
declare interrupt-controller properties even though Zephyr does not
model GPIO controllers as interrupt controllers.
Drop interrupt-controller, #interrupt-cells, and the related
#address-cells property from those GPIO nodes while keeping their
interrupt lines intact for the driver.
Tested with:
- git diff --check
- west build -d /tmp/zephyr-dtapi -p always -b native_sim
zephyr/tests/lib/devicetree/api
- cmake --build /tmp/zephyr-dtapi -t run
Assisted-by: Codex:GPT-5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add bindings for the ESP32-P4 MIPI DSI host and for the DPI
scanout controller behind it, and the nodes describing them.
The bridge streams a framebuffer to the host DPI port rather
than being a peripheral of its own, so it is a child of the
host and carries no registers.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the ESP32-C61 devicetree, dt-bindings headers and the
wroom-1 module dtsi files. The devkitc module is a wroom-1
n8r2, so its dtsi carries 8 MB flash and 2 MB psram. UART0
uses GPIO11/GPIO10, the ROM console pins. GPIO15-21 are the
MSPI flash pads and are marked reserved.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
During build, we are presented with a warning from the devicetree compiler
<Warning (interrupt_provider): /soc/gpio@20120000: Missing #address-cells
in interrupt provider>. This patch strips the interrupt-controller
property from GPIO banks.
Signed-off-by: Alexandra Covaci <Alexandra.Covaci@microchip.com>
The lp core is an rv32imac processor with the zicsr and
zifencei extensions, but the devicetree only declared i, m, c
and zicsr. Add the missing a and zifencei extensions so the lp
core image builds with native atomic instructions and fence.i
support, matching the esp32c5 and esp32c6 definitions.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the snps,multicast-filter-bins and snps,perfect-filter-entries
properties to the ethernet nodes. The CH32V307 and CH32V317 have a
64 bin hash table and 4 MAC address entries.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
Add the snps,perfect-filter-entries property to the ethernet nodes.
The EMAC of the ESP32 and ESP32-P4 does not implement the multicast
hash table, but has 8 MAC address entries besides the station
address.
Assisted-by: Claude Code:claude-fable-5
Signed-off-by: Fin Maaß <info@finmaass.de>
The light sleep path in soc/espressif/common/power.c requires the
rtc_timer (LP timer) counter device as its wakeup timer. Without the
node, light sleep is silently skipped at runtime.
Add the node disabled, matching the layout used by esp32c5/c6/h2;
users enable it and set wakeup-source via overlay.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
The i2s binding marks unit as required, so any build enabling one
of the esp32p4 i2s nodes failed devicetree validation. Number the
three controllers and add the i2s_api loopback overlay for the
function ev board that surfaced it.
Declare i2s in the board yaml as well, otherwise twister filters
the suite out before the overlay is ever consulted.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the RMT peripheral node to ESP32, ESP32-S2, ESP32-S3,
ESP32-C3, ESP32-C5, ESP32-C6 and ESP32-H2 devicetrees, with a
pulse_io controller binding. Channels are selected through
pinctrl and consumers reference the controller with a single
channel cell. The ESP32-P4 node already exists and only gains
the pulse_io channel cells property.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Commit a36a77e9b8 ("drivers: reset: add ch32 reset controller")
added reset-controller nodes to the WCH dtsi files, but the include
added to ch32h417.dtsi names the binding header ch32_20x_30x-reset.h
while the header introduced by that commit is ch32v20x_30x-reset.h.
This breaks devicetree preprocessing for every ch32h417evt build.
Fix the include to use the correct header name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
