by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
LiteX GPIOIn module provides possibility to change IRQ mode
and edge via CSRs. This commit adds support for that feature.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
This adds missing option to disable IRQs.
Devicetree is modified to match previous commit with custom IRQ CSR
addresses.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
This commit adds support for GPIO interrupts in GPIO driver for Litex
SoC Builder.
Signed-off-by: Robert Szczepanski <rszczepanski@internships.antmicro.com>
The default status of UART should set disabled.
If UART needs to enable, it will be set in the
dts of board level.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.
This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rework the litex,clk to use the clock-controller.yaml and remove
address-cells/size-cells as they aren't needed for the binding.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This patch adds IRQ priority support for SiFive PLIC by device-tree.
Some IRQ sources of plic use Kconfig to set priority of their IRQ.
- AON: no driver
- I2C, SPI, PWM: not use IRQ
- GPIO, UART: default 1
So this patch specifies IRQ priority 1 for all sources.
Currently these drivers (gpio and uart) do not support that they get
and use IRQ priority from device-tree. We need more patches.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This commit is about it8xxx2 platform device tree.
Add driver's binding files, and one device tree as sample.
Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
RISC-V clint is an interrupt controller but it has no required
properties (#interrupt-cells and interrupt-controller).
This patch just adds missing properties.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
Removes peripheral aliases from the OpenISA RV32M1 SoC, which are no
longer being used after converting their associated drivers to use
DT_INST macros.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Replace DT_FLASH_DEV_NAME with DT_CHOSEN_ZEPHYR_FLASH_CONTROLLER_LABEL.
We now set zephyr,flash-controller in the chosen node of the device
tree to the flash controller device.
NOTE: For a SoCs with on die flash, this points to the controller and
not the 'soc-nv-flash' node. Typically the controller is the
parent of the 'soc-nv-flash' node).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now
set zephyr,entropy in the chosen node of the device tree to the entropy
device.
This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also
remove any other stale ENTROPY related defines in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a property to the openisa,rv32m1-gpio binding that relates the GPIO
node to the pinmux PORT node.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.
Updated the openisa,rv32m1_vega-pinmux binding to require the label
property and updated the rv32m1.dtsi to add label properties for the
pinmux nodes.
Also update gpio_basic_api test to use DT_NODELABEL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Also rename various node labels to match the SoC docs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a YAML, DTS node and driver support to utilize data from devicetree
for register address and driver name.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use zero-padded 32-bit hex constants for the start address and
length so the fields are easier to compare. Correct the span of
the priority/claim region.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This enables LiteX PRBS random number generator driver
for litex_vexriscv board.
Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This is just a cosmetic change to avoid a warning:
"unit-address and first reg (0xb0000000)
don't match for ethernet@e0009800"
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
The Generic FSK controller enables radio operation
using a custom GFSK/GMSK or MSK modulation format
achieved by programming a set of PHY variables such
as BT product, modulation index and modulation filter
co-efficients (such that max frequency deviation
<= 500kHz). Generic FSK mode also offers a highly
configurable packet structure, variable bit rate
transmission and reception, some limited packet
(header) processing, and interface to a RAM-based
Packet Buffer.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC.
Based heavily on the existing mcux LPSPI driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Enable LiteX DNA ID driver in litex_vexriscv board.
Signed-off-by: Jakub Wegnerowski <jwegnerowski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Each intmux block acts like 8 interrupt controllers in which we can
have multiple device interrupts on a single channel and that channel
than interrupt than chained to another interrupt controller (in the
case of the RISC-V cores, it is the event unit).
So to describe things better to properly be able to walk the interrupt
chain in the device tree we treat each channel in the interrupt mux as
an interrupt controller rather than the intmux as a single interrupt
controller.
In the future this will allow the device tree generation code to walk
the interrupt chain from the device and up through any interrupt
controllers to generate the IRQ value that Zephyr expects (rather than
us hard coding this into the DTS).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
