Use the new SPI FIFO related property to retrieve FIFO size (instead of
guessing it from the supported data width), and to check that the
TSIZE register is not written with a value that exceeds the maximal
supported transfer size.
Also reorder the spi_stm32_config structure to have better packing.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For an asynchronous transfer, the driver was waiting until transfer was
ended to leave the transceive function, which defeated the purpose of
async. Restore previous behavior. The transfer is still blocking for
half duplex though.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit adds the support of the FIFO threshold for H7-compatible SPI.
This makes full use of the two FIFOs (Tx and Rx) available for these
devices, by packing the frames together in a single read or write when
possible, reducing the number of operations.
The FIFO threshold is supported only when fifo-enabled property is enabled
in device tree.
This new implementation is useful in interrupt mode at fast speed:
on Nucleo H753ZI, test_spi_complete_multiple_timed at fast speed indicates
a theoretical minimum duration of 27 µs, with a latency measurement of
18 µs for the new code against 34 µs previously, and a huge 76 µs when
fifo-enable is not present.
There are no noticeable changes at slow speed, or in polling or DMA mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Until now, SPI DMA transfers were not possible for H7-compatible STM32
devices if the fifo-enable property was enabled.
This commit adds the support of this property with DMA usage.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move udc_stm32_clock_enable() and udc_stm32_clock_disable() above their
callers, grouped with other helper functions. This allows removing an ugly
forward declaration at the top of the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The (driver-internal!) function udc_stm32_ep_flush() was very short and
only called from one function. Inline its contents inside the caller.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move udc_stm32_lock(), udc_stm32_unlock() and udc_stm32_init() above all
other functions which implement callbacks of the UDC API (and are already
in the same order as the initializer for udc_stm32_api).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move HAL_PCDEx_SetConnectionState with the other HAL callbacks
(except SETUP/DATA IN/DATA OUT) to make driver easier to browse.
Also move a relevant comment to a more appropriate place and update it.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move HAL callbacks for SETUP/DATA IN/DATA OUT events next to (above) the
lower half/worker thread handler for these events. This makes it easier to
follow the event handling logic.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The macro `hpcd2data` is defined as a wrapper around CONTAINER_OF(), but
was also adding a `;` at the end which is not right.
Remove the trailing `;` in the macro's definition.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a comment documenting why ordinals are used to create the per-instance
symbol names, as this is a very uncommon practice among STM32 drivers.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Replace usage of atoi() with strtol() when parsing numeric values
from ES-WIFI AT command responses.
strtol() provides well-defined behavior and allows proper error
handling.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
In Slave Half-Duplex TX mode, the driver disables SPE immediately
after loading data into DR, before the Master provides clock.
Since the Slave depends on the Master for clock, data is never
actually shifted out.
Fix by treating Slave Half-Duplex TX like SPI_HOLD_ON_CS: keep SPE
enabled after spi_write() returns, and let the application call
spi_release() once the Master has clocked out the data.
Tested on NUCLEO-F439ZI with SPI1 (master) and SPI3 (slave) in
half-duplex configuration.
Signed-off-by: PyoJin Yoon <volphin310@gmail.com>
When calling `gpio_pin_configure` with GPIO_OUTPUT_INIT_LOW or
GPIO_OUTPUT_INIT_HIGH, it is expected from the driver to set initial
output state. The current driver implementation does not set this
user provided initial state.
This commit sets requested output state before changing channel mode
to output.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
MAX14906 implementation of GPIO function `port_toggle_bits` writes
back old register value instead of inverted new value.
This commit XOR's current output state with requested pins (as expected)
and writes new value to register.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
The MAX149x6 drivers do not implement the generic GPIO function
port_set_masked_raw. The current implementation therefore hard faults due
to dereferencing NULL ptr on calls to gpio_port_set_masked_raw.
This commit adds port_set_masked_raw for both MAX14906 and MAX14916.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
The MAX14906 SetOUT register packs direction bits in [7:4] and output
state in [3:0]. The existing implementation clears all output bits
regardless of pin mask, as the mask is ANDed with 0xf0 before inversion.
This commit fixes that by masking before inverting.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
The MAX14906 can be operated compliantly without directly controlling
EN/FAULT/SYNCH/READY ports. The MAX14906 DTS files already reflect this
optional nature.
This commit makes the driver treat these ports as optional without changing
the business logic of the driver. If these ports are not defined,
certain diagnostic logging calls are simply skipped over.
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
The MAX14906 (p36), MAX14915 (p26), and MAX14916 (p28) datasheets state
that the device includes A0,A1,ThrErr bits in CRC calculation. The existing
solution doesnt handle these bits.
This commit passes the 3 top bits of the SDO check byte to the CRC
function, making the CRC calculation datasheet compliant
Signed-off-by: Stan Verschuuren <stverschuuren@gmail.com>
Some implementations of the DesginWare I2C controller do not support the
system suspending to idle during an I2C transaction. Add a Kconfig
option to allow locking of the power management policy state during
I2C transactions.
Signed-off-by: Keith Short <keithshort@google.com>
Add pin control driver for Alif SoCs. The driver manages
pin muxing (alternate function selection) and pad configuration
for Alif SoCs.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add clock control driver for Alif Semiconductor SoCs. The driver
manages peripheral clocks in the device by operating on multiple
discontiguous register regions (called modules in this driver).
In this initial version, the driver supports on, off, get_rate and
get_status API.
Co-authored-by: Manoj A Murudi <manoj.murudi@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Change the initialization level of retained_mem RAM driver to
PRE_KERNEL_1.
It allows using the drivers in the pre-kernel stage, which can be a case
for some applications.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
SOC_COMPATIBLE_NRF7120_ENGA was erroneously being used in
KConfig filter and therefore not being applied, since soc configs are
generated at compile time. Created SOC_COMPATIBLE_NRF71 to be used at
KConfig build stage.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Add clock control driver
Implement bootup clock initialization, on, off, configure and get_rate API
Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
Added register bitmask description with low-level abstraction
Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The final call in the driver init should be pm_device_driver_init.
This ensures the device transitions to active when the driver starts.
Signed-off-by: Ryan Erickson <ryan.erickson@ezurio.com>
This offloaded wifi driver is deprecated and will be removed
in a future release. It is currently scheduled to be removed in
Zephyr 4.6. The reason for deprecation is that there is no
maintainer for this driver.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
This offloaded wifi driver is deprecated and will be removed
in a future release. It is currently scheduled to be removed in
Zephyr 4.6. The reason for deprecation is that there is no
maintainer for this driver.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Previously, the PHY driver always invoked the link state callback on
every check, even when the link state had not changed, and did not
properly synchronize access to the link state (issue #103826). This could
lead to spurious notifications and potential race conditions.
This patch:
- Calls the registered callback only when the link state actually changes.
- Logs link-up and link-down events correctly.
- Introduces a semaphore to protect the PHY link state.
- Updates link state in phy_mc_t1s_update_link_state() with proper
synchronization.
This ensures that both link state updates and callbacks reflect actual
changes, preventing unnecessary notifications and improving driver
correctness.
Fixes: #103826
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
In ataes132a_aes_ecb_block(), error paths could return after
k_sem_take() without releasing device_sem, leading to a potential
deadlock on subsequent calls.
Ensure k_sem_give() is called on all early-return paths after the
semaphore is taken.
This fixes a potential deadlock when invalid buffer sizes are
detected after acquiring the device semaphore.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Use int return type for command results to avoid truncating negative
errno values and ensure proper error propagation.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
The SPI_CTRLR0 register is intended for enhanced SPI modes, however some
implementations continue to process the INST_L and ADDR_L fields in
standard mode. On those platforms the controller to sends its own
instruction/address phase in addition to what the driver sends. This
results in a malformed SPI transaction with extra bytes on the wire.
Explicitly mask these fields in standard mode and only set them otherwise
in enhanced mode.
Signed-off-by: Lee Trager <lee@trager.us>
Add support for the Infineon PSoC 4 family to the SPI driver,
Kconfig options, and polling-based transfer completion for slave
mode as PSoC 4 slave hardware does not control transaction start.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Implement ifx_get_hw_block_num to retrieve the hardware block number
for a given SCB base address. This replaces the dependency on the
UART-specific lookup function ifx_cat1_uart_get_hw_block_num, making
the SPI driver more self-contained and ensuring correct resource
identification for SCB blocks.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Rename Kconfig options and internal macros to remove "CAT1" specificity,
making the driver more generic for the Infineon family. This is a
non-functional change to prepare for PSoC 4 support.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Adds the g1 driver for eic for microchip devices
- Uses the APIs of the eic driver from gpio driver
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Whenever the driver would fail initialization (return a non-zero value),
add an assertion to ease debugging/troubleshooting.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Fix "Violation to rule 21.2 (Should not use a reserved identifier) - clock"
in the aforementioned driver by renaming a local variable.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Clear the TX and RX FIFOs to ensure a clean state.
Without this reset, residual data or incomplete
characters from a previous session or the bootloader could remain
in the hardware buffers.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
