This bit would be used in order to generate several variants
of Bayer formats, however it shouldn't be enabled for YUV/RGB
formats by default.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Correct wrong macro GC2145_REG_OUTPUT_FMT / GC2145_REG_SYNC_MODE
being used while a different page is being accessed.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
SENSOR_XBR818_CLOCKRATE / val->val1 is getting assigned
to uint8_t variable which is causing the logically
dead issue, this commit is a fix for it.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Fix misleading comments and ensure "Bus Error" flag is properly cleared
(Bus-Off Entry flag was used twice previously).
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Selects TIMER_HAS_64BIT_CYCLE_COUNTER as an dependency for MCUX_OS_TIMER
This already is supported in the timer implementation in
drivers/timer/mcux_os_timer.c
Signed-off-by: Tomas Groth Christensen <tgc@foss.dk>
1. The edma version 5 share one driver with edma 4.
2. Edma5 tcd structure some difference, Use tcd type to distinguish,
and Edma5 uses 64 bytes for alignment instead of 32.
3. Some platforms have some address offsets for certain memory
when processing from a DMA perspective, such as imx95 cm7 TCM,
so add offset processing.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
cb_sqe could have been NULL before being passed into the callback function,
which expects cb_sqe to be non-NULL.
Add NULL check before the callback function with cb_sqe is called. The
reordering of the callback function after the sqe drop is okay as the
sqe drop is called when cb_sqe is NULL and the callback function isn't
expected to work when cb_sqe is NULL.
Signed-off-by: Alexander Apostolu <apostolu240@gmail.com>
Add clock bindings for UART/USART (1-9) peripherals in the
`stm32mp2_clock.h`.
Add UART/USART clocks rate reading to the STM32MP2 clock driver.
Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>
The STM32WBA Flash Manager driver is failing to erase a sector, instead of
erasing one sector, two sectors are erased.
Fix it by correctly calculating the number of sectors to erase
Signed-off-by: Eric Mechin <eric.mechin@st.com>
Previously if the MDIO access failed to complete, the driver could enter
an infinite busy loop. Add timeouts to fail the operation if the
hardware fails to respond within a reasonable time.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
There are multi sai instance shared on clock source on
cm33_cpu0, clock driver don't need index parameter, so
modify clock driver to adapt clock driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
XCACHE has been designed for RT700, tcd pool need to be put in
noncache region, update driver to support
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Automatically initialize NXP Wi-Fi driver and FW for Wi-Fi networking
operation. Disable this setting if Wi-Fi module will be used for
non-Wi-Fi use cases (manufacturing/calibration/test).
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Add PM hooks to release or reattach the serial ports from the bridge.
Does not save power per se but allows switch the lower level serial
ports for something else in runtime.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Enable NXP_WIFI_TX_RX_ZERO_COPY for IW610, which will reduce extra memcpy
between net stack and driver in TX data path and avoid the allocation of
RXPD and mlan_buffer in RX data path, to improve the throughput
performance.
Increase CONFIG_NET_BUF_DATA_SIZE to hold one packet in one buffer.
NXP_WIFI_TX_RX_ZERO_COPY can be enabled not only for NXP_RW610 case.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Flexio ISR handle all flags even they are not interrupt enabled.
This will cause invalid calling of ISR callback functions.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
This commit changes the implementation to distinguish between is25lpXXX
and is25lpXXXd. Using RDERP as in the original solution didn't work for
is25wpXXX chips and would cause a halt. This new implementation reads
the AutoBoot register instead, which is not present in is25lpXXX but
present in is25lpXXXd, is25wpXXX and is25wpXXXd.
Tested on:
- mimxrt1020-evk
- mimxrt1170-evk rev. A
- custom board with mimxrt1170 and is25lp128d
Signed-off-by: John Barbero Unenge <git@lsrkttn.com>
Set right frame size in spi_context_buffers_setup and fetch
the right rx size based on frame size. Also clear SPI control register
before set mode & data width in spi configure routine.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Replaced conditional compilation of `CONFIG_NXP_WIFI_SOFTAP_SUPPORT`
where applicable with IS_ENABLED() macro to improve code readability.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Add support for gating/ungating IMX8QM/IMX8QXP's ESAI clocks and the
AUD_PLL_DIV_CLK0 clock used as source for ESAI's EXTAL.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
New property of the st,stm32-qspi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-qspi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix ABUS allocation if both EVEN and ODD busses are used for the
same port. The initialisation loop would incorrectly overwrite
entire GPIO_nBUSALLOC when iterating the pinctrl array, must do
a read/mask/update/write sequence.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
Comments and documentation mention compatibility with several
Sharp LS0xxx references, such as LS012B7DD06, a 64-color 6-bit
parallel display, and LS013B7DH06 a 8-color serial display.
The ls0xx driver supports serial and monochrome only.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Allow setting fifo-highres from DT, also unify the
naming of all registers and expand to a more complete list.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Add initial support for i2c on Renesas RX MCU
This driver is controlling the RIIC HW of RX MCU for i2c bus
interface on Zephyr
Only master mode is supported
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Implement I2C target mode in STM32 I2C RTIO drivers. The implementation
in respectively i2c_ll_stm32_v1_rtio.c and i2c_ll_stm32_v2_rtio.c is
based on the implementation of the non-RTIO drivers, respectively
i2c_ll_stm32_v1.c and i2c_ll_stm32_v2_rtio.c.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct management of I2C write transfers that are driven from 2
I2C messages, one for the transfer of the address to write
to and a following message for the transfer of the data to be written.
In this case, no START and STOP bit should be triggered between the 2
I2C transfers.
In STM32 I2C v1 driver, this simply means not emitting a START
condition when the input sequence does not set the RESTART flag.
In STM32 I2C v2 driver, this can only be achieved using the SoC I2C
controller Reload Mode feature, hence update Reload Mode implementation
to use reload mode for both transfers over 255 bytes (splitted in
chunks) and for cases where no STOP and START bits are emitted between
2 transfer in the same transaction.
Regarding STM32 I2C v2 driver, the reload mode must be enable before the
first transaction, known that it's needed due to the following
transaction. Therefore we need to parse the messages grouped in the same
transaction to detect such sequences (a message without STOP flag
followed by a message without RESTART flag) and when so, pass the
information to the I2C driver through RTIO framework. To achieve that,
let's use a free bit from I2C message flags (bit 7) in the message
for which we need to enable SoC ReloadMode from the first transfer.
We check that this bit flag is not used by the I2C framework prior
using it.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
