Format existing drivers according to clang-format rules.
Not all drivers were formatted, according to the clang-format rules,
this commit resolves this.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Refactor drivers so all have the same clean public interface.
With this change, all drivers have the same coding style.
This change does not change how the driver works and was tested with
the "fuel-gauge-build all test"
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Add wsen_isds_2536030320001 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Add a num_of_allocated_channels field to struct dma_mcux_lpc_config. Add
a a capacity check for dma_X_channel_data_arr in dma_mcux_lpc_configure.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Enable Link-Up and Link-Down interrupts. On the interrupt handling
the monitor work is scheduled to update the link status and calling
corresponding callback routine.
Signed-off-by: Tony Han <tony.han@microchip.com>
Call ksz8081_init_int_gpios() after phy_mc_ksz8081_reset() due to
keep the configurations for interrupt.
Signed-off-by: Tony Han <tony.han@microchip.com>
Update the internal driver flags to avoid setting DO_AUTONEG_FLAG
unconsciously when setting LINK_STATE_VALID.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add a stupid binding for doc purposes. Terrible coupling when we have to
configure DT in order to generate documentation properly. At least we
get rid of one of the stupid HAS_MCUX_ kconfigs in the process.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
When USDHC_Reset fails, we should be more verbose about it failing. Add
the error prints here so that we can observe the failure in logs.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
1.Update dts bindings to move clock-source properties from
nxp,ftm-pwm.yaml to nxp,ftm.yaml.
2.Provide counter driver based on FTM driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The following error is issued by clang when building with
SPI_NOR_SFDP_RUNTIME enabled:
error: fields must have a constant size:
'variable length array in structure' extension will never be supported
1379 | uint32_t dw[MIN(php->len_dw, 20)];
Instead, hardcode the array length to 20 32-bit words (it's instantiated
in the stack anyway).
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Re-configure the registers if they re erased because of a STOP2 low power
mode.
Return the error code when re-initializing the UART after a STANDBY low
power mode.
Fix few typos and comments.
Run clang format on uart_stm32_pm_action()
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
In both lsm9ds1 and lsm9ds1_mag drivers, the device data structure is
generally referenced with the variable name data.
However, in the initialization functions, the variable was named
lsm9ds1 (or lsm9ds1_mag for the magnetometer), which breaks this
convention.
Rename these variables to data for consistency across the driver.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Adds support for device PM for the lsm9ds1 sensor, putting the sampling
frequency of both the accelerometer and the gyroscope at 0 when the device
is suspended.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Controllers that use buffers directly must always allocate the length of
the control OUT buffer as a multiple of the control endpoint MPS.
Kinetis UDC driver explicitly checks the remaining buffer size and
finishes the transfer earlier.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Fix typo und remove unused variable, add a check for buffer allocation.
Do not disable controller on udc_disable.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Some controllers, such as those used in Kinetis devices, do not provide
a way to reset the buffer descriptor flags for each endpoint. Do not
reset the odd flag on endpoint enable, as this will cause it to become
out of sync with the hardware.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Until recently this driver wasn't built in CI. Now that it is, clang
is complaining about `err` possibly being uninitialized in case
`bitmask` is 255. Fix it by actually removing code that was
unnecessarily trying to access the uninitialized variable.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
In HAL based stm32 drivers, dma handling is done internally to HAL.
Though, in order to avoid a dma_config() call is done to ensure stream
will be set as busy in zephyr dma driver to avoid potential resource
sharing conflict.
This dma_config() call was done while taking into account
STM32_DMA_STREAM_OFFSET, which is wrong as it will prevent zephyr dma
driver to set the right stream as busy.
Fix this in impacted drivers.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
To ease code understanding of offset handling within the driver,
harmonize its treatment within impacted functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32_DMA_STREAM_OFFSET is defined as 0 in case "dma u5" is in use.
Clean up code relating to this define.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
On STM32L4, similarly to other STM32 series, enable DMA directly based
on dt configuration and avoid need to configure it at application level.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This change fixes STM32H7xx dma configuration.
PeriphInc and MemInc should be the same for both directions.
MemDataAlignment should be set to DMA_MDATAALIGN_HALFWORD
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Fix Coverity issue CID 524766: A potential integer overflow could occur
in paj7620_set_sampling_rate() due to multiplication of
sensor_value->val1 instance(which is of type int32_t) with 1000000
without typecasting it to int64_t.
Fixes#90482
Signed-off-by: Aditya Chopra <adityachopra2912@gmail.com>
Set mem_block to NULL after the STOPPING command in order to exit
TX callback at the end of the buffer transmission.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Check `explorir_m_uart_transceive`'s return value in `explorir_m_init` and
return the value if not 0.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
rtc_ds3231.h only contains register definitions and bitmasks used
internally by the driver - make this header file private.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add compatibility macros to map SDMMC constants to SDIO equivalents
for STM32F4 series MCUs. STM32F4 uses SDIO peripheral with SDIO_*
constants while newer STM32F7/H7 series use SDMMC peripheral with
SDMMC_* constants.
This fixes compilation errors on STM32F4 platforms where SDMMC_*
constants are undefined:
- SDMMC_CLOCK_EDGE_RISING
- SDMMC_CLOCK_BYPASS_ENABLE/DISABLE
- SDMMC_CLOCK_POWER_SAVE_ENABLE/DISABLE
- SDMMC_HARDWARE_FLOW_CONTROL_DISABLE
Fixeszephyrproject-rtos/zephyr#94896
Signed-off-by: Shan Pen <bricle031@gmail.com>
The AT25XV021A variant is a flash variant of Atmel's AT25 family
that adds extra protections, requiring additional writes to the
device to program or erase data.
This commit adds a flash driver for AT25XV021A devices instead of
modifying (1) the existing AT45 SPI flash driver or (2) the
existing AT24/25 EEPROM driver because this variant poses
fundamental changes that affect all aspects of the driver.
Notably,
- AT25XV021A includes a second status register, and the format
and functions of the existing status register is
changed from the existing drivers.
- AT25XV021A requires executing page or chip erase commands
before writing, making it incompatible with the
existing AT24/25 EEPROM driver.
- AT25XV021A adds a software protection layer that requires
extra writes before executing program or erase commands.
Tested writing to and erasing from an AT25XV021A device. Tested
reading from an AT25XV021A device across page boundaries. Tested
chip erase function. Tested driver initialization from varying
initial hardware states.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
The `pio` value is stored in the internal `pio_rpi_pico_config` structure
that is not exposed. However, it is the first element of the structure.
Here, I convert the pointer to `pio_rpi_pico_config` into a pointer to PIO
to access this value.
Signed-off-by: Terry Geng <terry@terriex.com>
Connection manager doesn't depends on ESP32 Wi-FI AP+STA mode.
This modification fix integration of connection manager binding
in the Wi-Fi ESP32 driver.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Add a choice of which RSSI type should be reported to the application
layer, packet RSSI (which stops at the noise floor) or signal RSSI
(which estimates the LoRa signal strength into the noise floor).
Signed-off-by: Jordan Yates <jordan@embeint.com>
As a first integration of the LoRa Basics Modem backend, implement the
LoRa API for the standard SX126x/SX127x chips.
Much of the logic from `lbm_common.c` is taken from the loramac-node
`sx12xx_common` implementation, but it should now be agnostic for all
LoRa RF transceivers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Move the current implementation of the LoRa API using `loramac-node` to
a dedicated folder in preparation for the LoRa basics modem
implementation.
Signed-off-by: Jordan Yates <jordan@embeint.com>
This commit is fixing configuration of mx66uw1g45g NOR when working
at 200MHz.
According to its specification, when running at 200MHz, this memory should
use a Number Dummy Cycles configuration of 20 (DC bits in CFGR2), which is
the device's default configuration.
Applying the 66MHz configuration as done today was preventing flash to run
at frequency higher than 100Mhz.
This commit doesn't solve the more generic problem of this driver which
is applying this 66MHz configuration universally, irrespective of the
frequency and the memory device, but fixes the configuration which was
reported broken today.
Providing a global change would require starting a clear split between XSPI
controller configuration an bus device configuration, which is what new
MSPI API intend to solve, so this will be tackled once this driver will be
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
