drivers: flash: Optimize mspi_nor driver memory
Move MSPI NOR commands to rodata. Replace array with empty padding (~1kB) with macro-based assignments. Ref: NCSDK-32779 Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
This commit is contained in:
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eab720201f
commit
2f6ac20654
3 changed files with 199 additions and 167 deletions
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@ -520,7 +520,7 @@ static int quad_enable_set(const struct device *dev, bool enable)
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struct flash_mspi_nor_data *dev_data = dev->data;
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int rc;
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flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
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flash_mspi_command_set(dev, &commands_single.write_en);
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rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
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&dev_data->xfer);
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if (rc < 0) {
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@ -672,7 +672,7 @@ static int flash_chip_init(const struct device *dev)
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}
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#endif
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flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].id);
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flash_mspi_command_set(dev, &commands_single.id);
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dev_data->packet.data_buf = id;
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dev_data->packet.num_bytes = sizeof(id);
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@ -787,7 +787,39 @@ static DEVICE_API(flash, drv_api) = {
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}
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#define FLASH_SIZE_INST(inst) (DT_INST_PROP(inst, size) / 8)
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#define FLASH_CMDS(inst) &commands[DT_INST_ENUM_IDX(inst, mspi_io_mode)]
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/* Define copies of mspi_io_mode enum values, so they can be used inside
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* the COND_CODE_1 macros.
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*/
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#define _MSPI_IO_MODE_SINGLE 0
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#define _MSPI_IO_MODE_QUAD_1_4_4 6
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#define _MSPI_IO_MODE_OCTAL 7
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BUILD_ASSERT(_MSPI_IO_MODE_SINGLE == MSPI_IO_MODE_SINGLE,
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"Please align _MSPI_IO_MODE_SINGLE macro value");
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BUILD_ASSERT(_MSPI_IO_MODE_QUAD_1_4_4 == MSPI_IO_MODE_QUAD_1_4_4,
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"Please align _MSPI_IO_MODE_QUAD_1_4_4 macro value");
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BUILD_ASSERT(_MSPI_IO_MODE_OCTAL == MSPI_IO_MODE_OCTAL,
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"Please align _MSPI_IO_MODE_OCTAL macro value");
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/* Define a non-existing extern symbol to get an understandable compile-time error
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* if the IO mode is not supported by the driver.
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*/
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extern const struct flash_mspi_nor_cmds mspi_io_mode_not_supported;
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#define FLASH_CMDS(inst) COND_CODE_1( \
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IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_SINGLE), \
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(&commands_single), \
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(COND_CODE_1( \
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IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_QUAD_1_4_4), \
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(&commands_quad_1_4_4), \
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(COND_CODE_1( \
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IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_OCTAL), \
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(&commands_octal), \
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(&mspi_io_mode_not_supported) \
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)) \
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)) \
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)
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#define FLASH_QUIRKS(inst) FLASH_MSPI_QUIRKS_GET(DT_DRV_INST(inst))
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#define FLASH_DW15_QER_VAL(inst) _CONCAT(JESD216_DW15_QER_VAL_, \
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@ -39,7 +39,7 @@ struct flash_mspi_nor_config {
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struct flash_pages_layout layout;
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#endif
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uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
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struct flash_mspi_nor_cmds *jedec_cmds;
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const struct flash_mspi_nor_cmds *jedec_cmds;
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struct flash_mspi_nor_quirks *quirks;
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uint8_t dw15_qer;
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};
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@ -73,169 +73,169 @@ struct flash_mspi_nor_cmds {
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struct flash_mspi_nor_cmd sfdp;
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};
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struct flash_mspi_nor_cmds commands[] = {
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[MSPI_IO_MODE_SINGLE] = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_ID,
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.cmd_length = 1,
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_WREN,
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.cmd_length = 1,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_READ_FAST,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDSR,
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.cmd_length = 1,
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},
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.config = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDCR,
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.cmd_length = 1,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_PP,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_SE,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_CE,
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.cmd_length = 1,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_SFDP,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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},
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const struct flash_mspi_nor_cmds commands_single = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_ID,
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.cmd_length = 1,
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},
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[MSPI_IO_MODE_QUAD_1_4_4] = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_ID,
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.cmd_length = 1,
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.force_single = true,
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_WREN,
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.cmd_length = 1,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_4READ,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 6,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDSR,
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.cmd_length = 1,
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.force_single = true,
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},
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.config = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDCR,
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.cmd_length = 1,
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.force_single = true,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_PP_1_4_4,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_SE,
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.cmd_length = 1,
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.addr_length = 3,
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.force_single = true,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_CE,
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.cmd_length = 1,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_SFDP,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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.force_single = true,
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_WREN,
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.cmd_length = 1,
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},
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[MSPI_IO_MODE_OCTAL] = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_OCMD_READ_ID,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 4
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_WREN,
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.cmd_length = 2,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_OCMD_RD,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 20,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_OCMD_RDSR,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 4,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_PAGE_PRG,
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.cmd_length = 2,
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.addr_length = 4,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_SE,
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.cmd_length = 2,
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.addr_length = 4,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_CE,
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.cmd_length = 2,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_OCMD_READ_SFDP,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 20,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_READ_FAST,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDSR,
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.cmd_length = 1,
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},
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.config = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDCR,
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.cmd_length = 1,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_PP,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_SE,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_CE,
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.cmd_length = 1,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_SFDP,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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},
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};
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const struct flash_mspi_nor_cmds commands_quad_1_4_4 = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_ID,
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.cmd_length = 1,
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.force_single = true,
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_WREN,
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.cmd_length = 1,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_4READ,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 6,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDSR,
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.cmd_length = 1,
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.force_single = true,
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},
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.config = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_CMD_RDCR,
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.cmd_length = 1,
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.force_single = true,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_PP_1_4_4,
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.cmd_length = 1,
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.addr_length = 3,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_SE,
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.cmd_length = 1,
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.addr_length = 3,
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.force_single = true,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_CMD_CE,
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.cmd_length = 1,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_CMD_READ_SFDP,
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.cmd_length = 1,
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.addr_length = 3,
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.rx_dummy = 8,
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.force_single = true,
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},
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};
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const struct flash_mspi_nor_cmds commands_octal = {
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.id = {
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.dir = MSPI_RX,
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.cmd = JESD216_OCMD_READ_ID,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 4
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},
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.write_en = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_WREN,
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.cmd_length = 2,
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},
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.read = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_OCMD_RD,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 20,
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},
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.status = {
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.dir = MSPI_RX,
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.cmd = SPI_NOR_OCMD_RDSR,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 4,
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},
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.page_program = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_PAGE_PRG,
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.cmd_length = 2,
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.addr_length = 4,
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},
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.sector_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_SE,
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.cmd_length = 2,
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.addr_length = 4,
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},
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.chip_erase = {
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.dir = MSPI_TX,
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.cmd = SPI_NOR_OCMD_CE,
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.cmd_length = 2,
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},
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.sfdp = {
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.dir = MSPI_RX,
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.cmd = JESD216_OCMD_READ_SFDP,
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.cmd_length = 2,
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.addr_length = 4,
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.rx_dummy = 20,
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},
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};
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@ -75,7 +75,7 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev)
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} while (status & SPI_NOR_WIP_BIT);
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/* Write enable */
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flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
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flash_mspi_command_set(dev, &commands_single.write_en);
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rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
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&dev_data->xfer);
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if (rc < 0) {
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@ -154,7 +154,7 @@ static inline int mxicy_mx25u_post_switch_mode(const struct device *dev)
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}
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/* Write enable */
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flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
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flash_mspi_command_set(dev, &commands_single.write_en);
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rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
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&dev_data->xfer);
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if (rc < 0) {
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