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drivers: flash: Optimize mspi_nor driver memory

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Move MSPI NOR commands to rodata.
Replace array with empty padding (~1kB) with macro-based assignments.

Ref: NCSDK-32779

Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
This commit is contained in:
Tomasz Chyrowicz 2025-04-10 14:53:50 +02:00 • committed by Benjamin Cabé
commit 2f6ac20654
3 changed files with 199 additions and 167 deletions
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38
drivers/flash/flash_mspi_nor.c
View file

@ -520,7 +520,7 @@ static int quad_enable_set(const struct device *dev, bool enable)
struct flash_mspi_nor_data *dev_data = dev->data;
int rc;
flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
flash_mspi_command_set(dev, &commands_single.write_en);
rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
&dev_data->xfer);
if (rc < 0) {
@ -672,7 +672,7 @@ static int flash_chip_init(const struct device *dev)
}
#endif
flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].id);
flash_mspi_command_set(dev, &commands_single.id);
dev_data->packet.data_buf = id;
dev_data->packet.num_bytes = sizeof(id);
@ -787,7 +787,39 @@ static DEVICE_API(flash, drv_api) = {
}
#define FLASH_SIZE_INST(inst) (DT_INST_PROP(inst, size) / 8)
#define FLASH_CMDS(inst) &commands[DT_INST_ENUM_IDX(inst, mspi_io_mode)]
/* Define copies of mspi_io_mode enum values, so they can be used inside
* the COND_CODE_1 macros.
*/
#define _MSPI_IO_MODE_SINGLE 0
#define _MSPI_IO_MODE_QUAD_1_4_4 6
#define _MSPI_IO_MODE_OCTAL 7
BUILD_ASSERT(_MSPI_IO_MODE_SINGLE == MSPI_IO_MODE_SINGLE,
"Please align _MSPI_IO_MODE_SINGLE macro value");
BUILD_ASSERT(_MSPI_IO_MODE_QUAD_1_4_4 == MSPI_IO_MODE_QUAD_1_4_4,
"Please align _MSPI_IO_MODE_QUAD_1_4_4 macro value");
BUILD_ASSERT(_MSPI_IO_MODE_OCTAL == MSPI_IO_MODE_OCTAL,
"Please align _MSPI_IO_MODE_OCTAL macro value");
/* Define a non-existing extern symbol to get an understandable compile-time error
* if the IO mode is not supported by the driver.
*/
extern const struct flash_mspi_nor_cmds mspi_io_mode_not_supported;
#define FLASH_CMDS(inst) COND_CODE_1( \
IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_SINGLE), \
(&commands_single), \
(COND_CODE_1( \
IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_QUAD_1_4_4), \
(&commands_quad_1_4_4), \
(COND_CODE_1( \
IS_EQ(DT_INST_ENUM_IDX(inst, mspi_io_mode), _MSPI_IO_MODE_OCTAL), \
(&commands_octal), \
(&mspi_io_mode_not_supported) \
)) \
)) \
)
#define FLASH_QUIRKS(inst) FLASH_MSPI_QUIRKS_GET(DT_DRV_INST(inst))
#define FLASH_DW15_QER_VAL(inst) _CONCAT(JESD216_DW15_QER_VAL_, \

324
drivers/flash/flash_mspi_nor.h
View file

@ -39,7 +39,7 @@ struct flash_mspi_nor_config {
struct flash_pages_layout layout;
#endif
uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
struct flash_mspi_nor_cmds *jedec_cmds;
const struct flash_mspi_nor_cmds *jedec_cmds;
struct flash_mspi_nor_quirks *quirks;
uint8_t dw15_qer;
};
@ -73,169 +73,169 @@ struct flash_mspi_nor_cmds {
struct flash_mspi_nor_cmd sfdp;
};
struct flash_mspi_nor_cmds commands[] = {
[MSPI_IO_MODE_SINGLE] = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_ID,
.cmd_length = 1,
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_WREN,
.cmd_length = 1,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_READ_FAST,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDSR,
.cmd_length = 1,
},
.config = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDCR,
.cmd_length = 1,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_PP,
.cmd_length = 1,
.addr_length = 3,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_SE,
.cmd_length = 1,
.addr_length = 3,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_CE,
.cmd_length = 1,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_SFDP,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
},
const struct flash_mspi_nor_cmds commands_single = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_ID,
.cmd_length = 1,
},
[MSPI_IO_MODE_QUAD_1_4_4] = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_ID,
.cmd_length = 1,
.force_single = true,
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_WREN,
.cmd_length = 1,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_4READ,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 6,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDSR,
.cmd_length = 1,
.force_single = true,
},
.config = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDCR,
.cmd_length = 1,
.force_single = true,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_PP_1_4_4,
.cmd_length = 1,
.addr_length = 3,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_SE,
.cmd_length = 1,
.addr_length = 3,
.force_single = true,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_CE,
.cmd_length = 1,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_SFDP,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
.force_single = true,
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_WREN,
.cmd_length = 1,
},
[MSPI_IO_MODE_OCTAL] = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_OCMD_READ_ID,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 4
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_WREN,
.cmd_length = 2,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_OCMD_RD,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 20,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_OCMD_RDSR,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 4,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_PAGE_PRG,
.cmd_length = 2,
.addr_length = 4,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_SE,
.cmd_length = 2,
.addr_length = 4,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_CE,
.cmd_length = 2,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_OCMD_READ_SFDP,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 20,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_READ_FAST,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDSR,
.cmd_length = 1,
},
.config = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDCR,
.cmd_length = 1,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_PP,
.cmd_length = 1,
.addr_length = 3,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_SE,
.cmd_length = 1,
.addr_length = 3,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_CE,
.cmd_length = 1,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_SFDP,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
},
};
const struct flash_mspi_nor_cmds commands_quad_1_4_4 = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_ID,
.cmd_length = 1,
.force_single = true,
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_WREN,
.cmd_length = 1,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_4READ,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 6,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDSR,
.cmd_length = 1,
.force_single = true,
},
.config = {
.dir = MSPI_RX,
.cmd = SPI_NOR_CMD_RDCR,
.cmd_length = 1,
.force_single = true,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_PP_1_4_4,
.cmd_length = 1,
.addr_length = 3,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_SE,
.cmd_length = 1,
.addr_length = 3,
.force_single = true,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_CMD_CE,
.cmd_length = 1,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_CMD_READ_SFDP,
.cmd_length = 1,
.addr_length = 3,
.rx_dummy = 8,
.force_single = true,
},
};
const struct flash_mspi_nor_cmds commands_octal = {
.id = {
.dir = MSPI_RX,
.cmd = JESD216_OCMD_READ_ID,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 4
},
.write_en = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_WREN,
.cmd_length = 2,
},
.read = {
.dir = MSPI_RX,
.cmd = SPI_NOR_OCMD_RD,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 20,
},
.status = {
.dir = MSPI_RX,
.cmd = SPI_NOR_OCMD_RDSR,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 4,
},
.page_program = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_PAGE_PRG,
.cmd_length = 2,
.addr_length = 4,
},
.sector_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_SE,
.cmd_length = 2,
.addr_length = 4,
},
.chip_erase = {
.dir = MSPI_TX,
.cmd = SPI_NOR_OCMD_CE,
.cmd_length = 2,
},
.sfdp = {
.dir = MSPI_RX,
.cmd = JESD216_OCMD_READ_SFDP,
.cmd_length = 2,
.addr_length = 4,
.rx_dummy = 20,
},
};

4
drivers/flash/flash_mspi_nor_quirks.h
View file

@ -75,7 +75,7 @@ static inline int mxicy_mx25r_post_switch_mode(const struct device *dev)
} while (status & SPI_NOR_WIP_BIT);
/* Write enable */
flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
flash_mspi_command_set(dev, &commands_single.write_en);
rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
&dev_data->xfer);
if (rc < 0) {
@ -154,7 +154,7 @@ static inline int mxicy_mx25u_post_switch_mode(const struct device *dev)
}
/* Write enable */
flash_mspi_command_set(dev, &commands[MSPI_IO_MODE_SINGLE].write_en);
flash_mspi_command_set(dev, &commands_single.write_en);
rc = mspi_transceive(dev_config->bus, &dev_config->mspi_id,
&dev_data->xfer);
if (rc < 0) {