Implement z_sys_clock_hw_cycles_per_sec_update() for the Cortex-M
SysTick driver to support runtime system timer frequency changes
when CONFIG_SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE is enabled.
Also extend the conditional compilation guard for the external
z_clock_hw_cycles_per_sec declaration to include the runtime update
configuration option.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add infrastructure to support updating the system timer frequency at
runtime on platforms where the timer clock rate can change dynamically.
Introduce CONFIG_SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE Kconfig
option that enables runtime frequency updates. This option is mutually
exclusive with CPU_FREQ_PER_CPU_SCALING since the system timer frequency
is tracked as a single global value.
Add z_sys_clock_hw_cycles_per_sec_update() API that platforms must call
after applying a system timer clock change. The kernel provides a weak
default implementation that updates the stored frequency value used by
sys_clock_hw_cycles_per_sec().
System timer drivers that cache derived constants or need to reprogram
hardware on frequency changes can provide a strong override of this
function to maintain driver state consistency while ensuring the stored
frequency is also updated.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Now that everything uses the generic STM32L4 PLL binding, remove all
references from the the old PLLSAI binding:
- Remove the lines using div_divr (it is now post_div_r)
- Remove the clock source check since it is now done in the driver
- Remove the PLLSAI binding since it is no longer used
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For the STM32L4/L5/WB/WL, update the clock driver to support all PLL
channels.
Also add some BUILD_ASSERT to check that the clock are correctly defined
and configured in device tree.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The property names in error message were not the correct ones (missing
an "-"). This commit fixes them.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove adcxx_prescaler macros. They are unused since commit
914425fafc54bf359e1d7693846e387a1150988d.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use stm32_reg_modify_bits to configure the clock source, instead of calling
sys_clear_bits then sys_set_bits. Using modifiy makes only one write in
the RCC register instead of two previously.
Incidentally, for H5, clear was missing. It is now replaced by modify.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Define IFX_SCB_ARRAY_SIZE for PSoC Edge SoCs to properly
determine the SCB array size.
Without this change, the driver fails to compile on
PSoC Edge platforms
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Fix trailing commas in ADVANCED_SPI_FIELDS macro definition
and its usage to ensure clean macro expansion.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Extend the Infineon peripheral clock control driver to support
ADC peripherals. Adds IFX_RSC_ADC resource type handling and
PSOC4-specific clock destination initialization (set to 0 as
PSOC4 peripherals manage their own clock routing).
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Add driver for the Infineon SAR ADC peripheral with device tree
binding. The driver uses a generic compatible (infineon,sar-adc)
with an infineon,version property to differentiate IP block
revisions (v2, v3). Features include:
- Single-ended and differential channel configuration
- Configurable resolution (8-12 bits)
- Multiple voltage reference sources (internal, VDDA, VDDA/2, external)
- Channel reference validation against block-level vref-src
- Hardware compensation for SAR v2/v3 single-ended channel limitation
- Interrupt-driven conversion completion
- Integration with peripheral clock control
The driver includes a compile-time per-instance API structure to
correctly report reference voltage to the ADC framework for accurate
raw-to-millivolts conversion.
Tested on CY8CKIT-041S-MAX (SAR v2) and CY8CPROTO-041TP (SAR v3) boards.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Use DT_GPARENT() so that protection entries are generated for
partitions under the fixed-partitions node, even when an extra
intermediate node is present. This ensures the C40 protection table
is correctly derived from the flash<x> partitions.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
Handle the case where the chosen zephyr,flash-controller device has
no flash API (api == NULL). This prevents flash_shell from
dereferencing a NULL api pointer and hard-faulting when no usable
default flash device is available.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
Initial generic driver for SPI-NAND devices that expose the ONFI
parameter page. Does not support advanced features such as continuous
reads, software ECC, or optional power down modes.
Configuration comes from devicetree in order to support other modules,
but is validated against the loaded ONFI data at boot.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Due to checksum offloading, the checksum field of a packet must be
zero before sending it to packet to the ethernet controller,
otherwise the computed checksum will be incorrect.
If the packet is bridged, it already has the correct checksum in
place, which will cause the automatically computed checksum to
incorrectly become zero.
In this patch we give bridged packets the special attention they
need.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
The flash info blocks needed to provide the device ID are not accessible to
the RV32 core on MAX32 devices, so disable this hwinfo driver there.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
A special SYS_INIT() callback with hardcoded PRE_KERNEL_1 level 0 priority
inside the STM32 pinctrl driver was configuring the SWD-JTAG ports on
STM32F1 series.
Since this is the only series which requires such configuration, move this
code to the SoC-specific init hook instead (which has almost the same
priority as PRE_KERNEL_1 level 0 - it runs just slightly earlier).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION calibration feature uses
HFCLK (hfxo in devicetree) as reference to calibrate the internal RC.
If the hfxo is not present, calibration is not possible, and if the
driver attempts to do it anyway, HFCLK will be requested wasting
power, and the calibration will never complete.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
integrate the mdio driver area into the
ethernet driver area. mdio itself is defined as part
of the ethernet specification.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Use official TDK Invensense driver for icm45686 sensor in tdk_hal module.
Supports icm456xx variants.
Signed-off-by: Remi Buisson <remi.buisson@tdk.com>
The drive mode validation added in commit ede19a4337 was rejecting
valid configurations for input pins. The validation ensures that
GPIO_SINGLE_ENDED and GPIO_LINE_OPEN_DRAIN flags match the hardware
capabilities of each MCP23xxx variant (push-pull vs open-drain).
However, this validation was applied to all pin configurations,
including input pins. Input pins do not have a drive mode, so
applications typically configure them without setting drive mode flags.
This caused the validation to incorrectly reject input pin configurations
with -ENOTSUP.
Fix by only validating drive mode flags when GPIO_OUTPUT is set.
Input pins now configure successfully, while output pins still receive
proper validation to ensure the requested drive mode matches the
hardware capabilities.
Fixes: ede19a4337 ("drivers: mcp23xxx: add support for open-drain ...")
Signed-off-by: Cliff Brake <cbrake@bec-systems.com>
This adds a driver for the interprocessor mailbox in the Raspberry Pi
Pico SoCs (RP2040/RP2350).
The SIO subsystem contains a set of low-latency peripherals, including a
pair of mailboxes (FIFOs) for inter-processor communication. One of the
FIFOs can only be written by core 0 and read by core 1, the other can
only be written by core 1 and read by core 0.
According to the datasheets [1] [2], the register interface is the
same in both SoCs and the only functional differences are that the
mailbox in the RP2040 is 8 entries deep vs 4 in the RP2350, and that the
RP2350 defines the same core-specific interrupt number, while the RP2040
defines two different IRQ numbers.
Tested on a Raspberry Pi Pico 2W (RP2350).
[1]: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf
[2]: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf
Signed-off-by: Ricardo Cañuelo Navarro <rcn@igalia.com>
This commit fixes the inconsistent type usage. Functions which
initialised i2c registers as uint16_t, changed to uint32_t to
match with register definition struct.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
The driver used a decrement loop to check for time out during message
transfer, which was not sufficient. The newer implementation uses a
fixed time of 1000ms for timeout to be consistent with the Linux
kernel.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
The driver was not correctly extracting FIFO byte counts
from the BUFSTAT register, causing multi-byte I2C transfers
to fail.
The BUFSTAT register layout is:
- Bits [13:8]: RX FIFO byte count
- Bits [5:0]: TX FIFO byte count
Also, the driver didnot update the remaining bytes after
each transfer which is fixed by decrementing the remaining
message length after each transfer.
This fix aligns the driver implementation with Linux.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
Add support for secure TISCI communication paths to enable
message exchange with secure contexts on TI SoCs.
- Add secure header wrapping for outbound messages on secure path
- Add secure header parsing for inbound messages on secure path
Signed-off-by: Dave Joseph <d-joseph@ti.com>
- Add ti,is-secure device tree property to indicate secure host entities
- Add is_secure field in device config
Signed-off-by: Dave Joseph <d-joseph@ti.com>
- Add missing TISCI message type macros in tisci.h
- Clean macro organisation
- Add Secure indicator for message that require secure thread
Signed-off-by: Dave Joseph <d-joseph@ti.com>
HL7800 only supports restoring 1 socket on boot. This means,
only the first socket created can be restored.
This isn't very useful, so never restore sockets on boot.
The driver already handles recreating sockets when
low power modes are used.
Signed-off-by: Ryan Erickson <ryan.erickson@ezurio.com>
iface_status_work_cb() calls notify_all_tcp_sockets_closed() while
holding hl7800_lock(). The close-all path can re-enter hl7800 via
socket callbacks, causing a lock inversion deadlock.
Signed-off-by: Scott Coleman - wsl <scott@sjcdev.com>
TCP connect refused triggers +K**P_NOTIF ,5.
The current handler falls through to default, marks network_dropped,
and later closes all sockets, taking down unrelated
connections (e.g., MQTT).
Signed-off-by: Scott Coleman - wsl <scott@sjcdev.com>
The WWDG timeout check used a signed comparison between the requested
and computed timeout, causing valid configurations to be rejected when
the computed timeout was slightly lower than the requested one.
Replace the comparison by an absolute‑difference check so that the
configured timeout is accepted as long as it stays within the allowed
error margin.
This fixes spurious -EINVAL returned by install_timeout() on STM32.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add a hwinfo backend for GD32 providing:
- device unique ID readout from the 96-bit UID registers
- reset cause reporting via the RCU_RSTSCK reset status register
Reset cause mapping uses the hal_gigadevice RCU_RSTSCK flag definitions
and reports supported causes based on the macros available in the HAL.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Correct a bitmask issue on the temperature alert threshold
as per the datasheet (Section 7.5.7.4.2).
Signed-off-by: Jeremy Thompson <jthompson@blackberry.com>
Add initial NB-NTN RAT support to the HL78xx driver:
* Enable RAT selection for NB-NTN (SET_RAT_NBNTN_CMD_LEGACY).
* Configure NTN positioning via +KNTNCFG("POS", provider, dynamic).
* Query +KNTNCFG at init and cache into modem_status.ntn_rat.
* Handle +KNTNEV:"POSREQ" and raise MODEM_HL78XX_EVENT_NTN_POSREQ.
* If MANUAL position source is enabled, push +KNTNCMD("POS") with
Kconfig-provided latitude/longitude/altitude.
* Kconfig updates:
- Add MODEM_HL78XX_ADDRESS_FAMILY_IP and default it for NB-NTN.
- Add NTN_MANUAL_{LATITUDE,LONGITUDE,ALTITUDE} under MANUAL source.
* For NB-NTN, program PDP context without explicit AF in +KCNXCFG and
use address family "IP".
* Extend socket connect and TLS handshake timeout ranges to 120 s to
tolerate higher RTT on NTN links.
Non-NTN builds keep previous behavior.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
Adds device power manager support to TMAG5273 driver.
Suspending the device will put it into its SLEEP mode, resuming will
restore it to the mode configured in devicetree.
Before communicating with a device in sleep mode, an extra I2C transfer
is needed. Something like this is briefly mentioned in the datasheet,
but without any more specific details. The wake up has also been added
to the init function, even in case PM is disabled.
The device is marked as busy for the whole sample_fetch function.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
LTE modems typically support default PDP context (cid 0) which
is activated when network is attached.
Allow driver to choose whether this CID 0 is used by default, and
skip the whole APN state.
Some modems require PDP context to be defined by AT+CGDCONT=1 command
but do not necessary need the APN name.
Add both options as a Devicetree settings as an enum value so that
specific DTS bindings may change the default while allowing user
to override. Booleans with "default: true" would not work.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
- Implement flash read, write and erase APIs.
- flash rows are automatically erased during Cy_Flash_WriteRow()
operation.
- Implement erase by writing the erased value (0xFF) to maintain
compatibility with the Zephyr flash API.i
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Introduce FLASH_INFINEON_PSOC4 to enable the flash driver for the
Infineon PSoC4 family.
- This option selects required flash capabilities.
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
