Pins configured with SAM_PINMUX_FUNC_extra (e.g. ADC analog inputs)
fall through the pinctrl configuration with the function field
defaulting to 0, which maps to SOC_GPIO_FUNC_A (Peripheral A).
If Peripheral A for that pin is an active output (e.g. SSC_TD on
PA17/SAM4S), it drives the pin LOW and the ADC reads 0V despite a
valid analog signal on the input.
Configure extra-function pins as PIO input (high-impedance) so no
peripheral output driver interferes with the analog signal path.
The ADC reads via its own internal analog connection regardless of
PIO mode.
Tested on SAM4S where PA17 (ADC ch0) Peripheral A is SSC_TD — ADC
now reads correctly instead of returning 0.
Signed-off-by: Ričards Poriņš <ricards.porins@gmail.com>
Keep the RT1170 MICFIL Audio PLL initialization in the CCM clock
control path, but stop rewriting the MIC root clock while serving
PDM rate queries.
Reprogramming the MIC root caused RT1170 regressions during runtime.
It broke the i2s_codec sample and led to MICFIL capture starvation in
dmic_api. This keeps the safe Audio PLL bring-up while preserving the
working MIC root configuration used by the board.
The RT1170 dmic_api overlay and testcase enablement are included so the
test covers the board directly.
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
Correct FLASH_STM32_EX_OP_OPTB_WRITE private flash operation for
stm32 internal flash drivers when unlocking or locking option bytes
fails. flash_stm32_option_bytes_lock() returns non-zero negative error
when so, not a positive error, fix flash_stm32_ex_op() accordingly,
using a comparison against zero, for consistency with other
calls to flash_stm32_option_bytes_lock().
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Upper bound is defined as the last block within the erase region.
Subtract one block unit from the erase size when programming upper
bound to prevent the erase range from extending into the next block.
With the correct upper/lower bounds in place, erase requests can be
handled in a single operation. Remove the block-by-block erase
loop.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
- Fixes "warning: LPADC_DO_OFFSET_CALIBRATION
(defined at drivers/adc/Kconfig.mcux:109) was assigned the
value 'y' but got the value 'n'..." in any application that did not
independently enable ADC.
- CONFIG_LPADC_DO_OFFSET_CALIBRATION is only meaningful when
CONFIG_ADC_MCUX_LPADC is enabled. Setting `default y'.
- Remove the now-redundant CONFIG_LPADC_DO_OFFSET_CALIBRATION=y
from the defconfigs of all NXP FRDM MCXA boards.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Drop duplicated HAL_XSPIM_Config fallback code from STM32 XSPI
flash, MSPI, and MEMC drivers.
With manager setup centralized in the common XSPIM driver and
explicit xspim devicetree nodes, XSPI consumer drivers no longer
need to configure XSPIM directly.
Assisted-by: GitHub Copilot:GPT-5.3-Codex west
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The QingKe V2A, V2C, and V4C have a Debug Module with two data
registers `data0` and `data1`. These can be used with SDI compatible
debuggers such as `minichlink` to send console data to the host.
Add a console driver communicates with the host and fails gracefully
if the driver is enabled but the debugger is not connected.
Compared to the UART console, the debug console uses 916 bytes less
flash and frees up a UART.
Tested on the ch32v006evt and bluepillplus_ch32v203. To test, add
`&sdiconsole { status = "okay"; };` to the board Devicetree, set
`zephyr,console = &sdiconsole`, and enable the driver.
Signed-off-by: Michael Hope <michaelh@juju.nz>
use DT_INST_ENUM_HAS_VALUE for
phy_connection_type, that way we don't have to do
string operations.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
SCMI Platform-to-Agent (P2A) notifications are delivered via
the RX transport channel, Extend the SCMI transport callback
signature to pass the received message header to the core, allowing:
- validation of SCMI message type
- routing of NOTIFICATION messages to protocol handlers
- differentiation from synchronous response flow
Protocols may now optionally register supported notification
event IDs and a callback during static initialization.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
In SCMI Platform-to-Agent (P2A) notification flow, the agent
must explicitly mark the RX shared memory channel as FREE
after processing an incoming message.
Introduce scmi_shmem_clear_channel_status() to provide a
standardized mechanism for transport drivers to release RX
channel after handling notifications.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Mailbox-based SCMI transports may signal incoming Platform-to-Agent
(P2A) messages via a dedicated RX doorbell.
Introduce an optional RX callback registration path in the mailbox
transport driver to handle asynchronous notifications independently
from TX reply interrupts.
If no RX mailbox channel is defined, the RX path remains disabled.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
SCMI transports may optionally provide a dedicated RX channel to
deliver asynchronous Platform-to-Agent (P2A) messages such as
notifications or delayed replies.
The SCMI core previously assumed a TX-only transport model and
rejected RX channel setup.
Allow SCMI protocols to request and initialize an optional RX
transport channel when provided by the underlying transport
driver.
No functional change for platforms that only implement TX
shared memory.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The SiWx91x SoC features an external AHB instruction cache for the QSPI
flash. It has no data cache.
There is no dedicated hardware invalidate command. Invalidation is
performed by toggling the clock gate (disable then re-enable), which
implicitly clears all cached lines. An ISB barrier follows to flush the
Cortex-M4 instruction pipeline.
The driver selects EXTERNAL_CACHE (not ARCH_CACHE) because the siwx91x
Cortex-M4 core does not define __ICACHE_PRESENT in the CMSIS device
header, so the ARM architecture cache implementation (SCB_EnableICache)
cannot be used.
Note this commit has not functional impact. Instruction cache was already
automatically start by the hal.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
- add clocks and resets to MCXA CRC nodes.
- crc_nxp: deassert in init if a dt reset is given.
On MCXA SoCs the CRC peripheral boots held in reset, so enabling its
clock is not enough. Deassert the reset during driver init.
- nxp,crc.yaml: include reset-device.yaml for the resets property.
- mcxa Kconfig.defconfig: enable CONFIG_RESET
when MRCC reset is present.
- clock_control_mcux_syscon: enable the CRC clock gate.
- mcxa344: fix reset controller compatible to nxp,mrcc-reset.
Tested on frdm_mcxa344, frdm_mcxa156, frdm_mcxa266.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Stopping reception with lora_recv_async(dev, NULL, NULL) from inside the
async callback races with the DIO1 interrupt. modem_release() sets the
mode to MODE_SLEEP and puts the chip to sleep, but the DIO1 interrupt is
still enabled, so a packet arriving in that window schedules a work item
that then runs with MODE_SLEEP already set and logs "Unexpected modem
mode (0)".
On parts that re-assert DIO1 when woken from sleep with a pending IRQ
(observed on an LR11xx-based board) this becomes an infinite loop:
clearing the IRQ wakes the chip, DIO1 re-asserts, another work item is
scheduled, and so on.
Fix this in three parts:
- Disable DIO1 in modem_release() before the chip goes to sleep, and
re-enable it (with a stale-IRQ clear) when starting the next RX/TX.
The dio1 gpio_dt_spec is moved into lbm_lora_config_common so the
common layer owns the operational interrupt gating directly. Parts
that do not route their IRQ through a single DIO1 line (SX127x drives
several DIO lines and manages them itself) leave the pin unset, so the
common layer accesses it through a NULL-guarded helper.
- When the work handler sees MODE_SLEEP it returns instead of touching
the hardware, which is what previously drove the loop.
- When the async callback stops reception, the handler detects that the
modem was already released (mode is now MODE_SLEEP) and returns before
re-reading the IRQ status, leaving the chip asleep instead of waking
it again.
Fixes#111484
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@verkada.com>
Remove `$(ZEPHYR_BASE)` from `source "<file>"`.
Source is always relative to ZEPHYR_BASE, so no need to specify it.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
We changed the return type of
sy1xx_mac_set_mac_addr, but forgot to change
the prorotype, but instead of fixing that we can
remove the prototype, as the function is only used
after it is been implemented.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
CRC16_CCITT and CRC16_ITU_T share the same polynomial and
differ only in input/output reflection.
So collapse them into a single fall-through case to avoid duplication.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add missing k_spin_unlock() calls on error return paths in
gpio_altera_configure() and gpio_altera_pin_interrupt_configure().
Both functions returned -EINVAL in their default/else branches
while still holding the spinlock acquired earlier.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
remove setting tx stats, that are already handled
by ethernet_send. It will already call
eth_stats_update_errors_tx on failiure
and on success via ethernet_update_tx_stats
it calls eth_stats_update_bytes_tx,
eth_stats_update_pkts_tx,
eth_stats_update_broadcast_tx and
eth_stats_update_multicast_tx.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
These drivers were used by Series 2 SoCs before they were migrated from
gecko_sdk to simplicity_sdk. Currently, Series 2 SoCs don't use them
anymore. In fact, their Kconfig dependencies don't even allow using them
for simplicity_sdk based SoCs.
Removing the leftovers simplifies the code and is a preparation for larger
changes in soc.c.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
`DEVICE_MMIO_ROM/RAM` must be the first field in a struct, but the
GPIO API uniquely requires `gpio_driver_config/data` to be first.
This commit extends the changes made in PR #108244 to
the renesas_rza2m GPIO driver by switching to the named MMIO variants.
This allows the MMIO data to be safely placed in subsequent
fields for both ROM and RAM initializations.
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
Add a wait for the Transmission Complete (TC) flag at the start of
mcux_lpuart_configure(). This prevents reconfiguration while the
hardware is still shifting out the final byte on the TX line.
Without this wait, uart_configure() could interrupt an ongoing
transmission, causing the last byte to not be fully sent on the UART
bus. This behavior was observed on NXP LPUART and tracked in issue
#109807.
Fixes#109807
Signed-off-by: Michal Chromec <michal.chromec@nxp.com>
Resolve ITCM overflow (2928 bytes) on mimxrt1060_evk by applying
function-level FILTER to relocate only hot-path functions instead
of entire files. This reduces ITCM usage from 100% to 70.09%
with no throughput regression.
Use FILTER for net stack, socket, SDIO, and zperf files
Keep kernel primitives as whole-file (inline dependencies)
Add zvfs, poll, condvar, timeout to relocation list
Restrict to CONFIG_SPEED_OPTIMIZATIONS only
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Start the Wi-Fi driver during initialization so coexistence is
enabled early. Without it the Wi-Fi pp task blocks at boot when BLE
is also used, hanging the device.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When the A and B encoder pins connect to different GPIO ports, the
driver registered a single gpio_callback node on both ports' interrupt
lists. A sys_slist_t node can only belong to one list at a time;
inserting it into the second port silently unlinks it from the first,
so all interrupts from pin A are lost.
Fix this by replacing the single gpio_callback with two named fields,
gpio_cb_a and gpio_cb_b, each with its own independent slist node.
A dedicated ISR handler per field recovers the encoder device via
CONTAINER_OF with no extra RAM overhead per instance.
Signed-off-by: Eriks Zaharans <eriks.zaharans@marshall.com>
Assisted-by: Claude:claude-sonnet-4-6 Claude-Code
Related to commit 01b611100c. When not using
the fifo, the renesas_ra_sci peripheral will resend the last transmitted
character if you manually clear the TDRE bit in the SSR status register.
This makes 'SSR &=' dangerous to use in the case where the TDRE bit is set
in between reading the register and updating it. The hardware manual says
that writing a zero clears status bits and writing a one is ignored, so the
update isn't needed, only write 0 to the bits that need to be cleared. Only
the error status bits need to be manually cleared, the RDRF bit is cleared
automatically by hardware.
Signed-off-by: Aaron Brice <aaron@embeddedts.com>
The SPI SCK pin needs to be initialized to match the current SPI
transfer CPOL setting. The SPIM peripheral is enabled after CS is
toggled, thus all pins need to be configured to drive correct
initial state using gpio. Since the SCK pin is defined in pinctrl
rather than as a gpio pin, nrfy is used to get the pin number and
set the pin rather than gpio peripheral driver.
Without this addition, CPOL=1 may cause an incorrect clock to be
registered at the start of the transfer, shifting the data 1 bit.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
add a net_eth_carrier_set function, that
uses atomic_test_and_set_bit_to.
make net_eth_carrier_on and
net_eth_carrier_off inline and
based on net_eth_carrier_set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a system clock driver built on top of the NXP System Counter
(SYS_CTR) block, which provides a 56-bit free-running counter and two
compare frames capable of generating maskable interrupts.
The driver is a free-running counter paired with an absolute compare
register. Compare frame 0 is used for the system timer, leaving frame
1 available for other consumers. The instance is selected via the
zephyr,system-timer chosen property.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
dma_nxp_gdma_init() runs at PRE_KERNEL_1 and emitted an unconditional
LOG_INF on the init success path. Under the default deferred logging
mode that log captures a timestamp via the system clock, which on
RW612 is not initialized until PRE_KERNEL_2, hanging boot on frdm_rw612
(seen with the lvgl sample). ztest masks it by defaulting to minimal
logging, which takes no timestamp.
Other DMA drivers that log on init success run at POST_KERNEL, after
the clock is up; nxp_gdma is the only one doing so at PRE_KERNEL_1.
Remove the line to avoid the early-boot hang.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Add build-time validation of buffer constraints for the DWMAC driver.
This ensures that the configured buffer sizes and counts meet the
hardware requirements, preventing potential runtime issues due to
misconfiguration.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The Alif clock control driver needs to be usable by MMU-enabled
Cortex-A32 based board variants, which require the register regions to
be mapped into the virtual address space at runtime. Use the DEVICE_MMIO
named-region helpers to map and access the clock register regions.
The m55hp_cfg region is optional (absent on Balletto family and E1C
series SoCs), and the DEVICE_MMIO_NAMED_* helpers cannot express an
optional region. Store its physical address from the DT (0 if absent)
and map it manually with device_map() only when present.
No functional change for the existing non-MMU (Cortex-M55) targets.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Alif pinctrl driver needs to be usable by MMU-enabled Cortex-A32
based board variants (in addition to the Cortex-M55 based boards), which
require MMIO regions to be mapped into the virtual address space at
runtime. Map the pinctrl and lpgpio pinctrl regions using device_map()
during boot.
The driver does not use the device model, and the two regions are named
reg entries on a single pinctrl node. As the DEVICE_MMIO_TOPLEVEL_*
macros do not support named reg entries, device_map() is called directly
to map each region.
No behavioral change for the existing non-MMU (Cortex-M55) targets, as
device_map() collapses to a simple address assignment in them, now done
once at boot instead of compile time.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Factorize the macros and definitions of the I2C devices resources
between I2C STM32 non-RTIO and RTIO drivers that are the same
aside resource that can be conditioned to CONFIG_I2C_RTIO being enabled.
This change requires I2C API structure (renamed here i2c_stm32_driver_api)
and i2c_stm32_init() initialization function are no more locally defined.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add DMA support in the RTIO implementation of STM32 I2C v2 driver.
The implementation is based on the DMA support in the STM32 I2C v2 no-RTIO
driver (i2c_stm32_v2.c).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add a return status to i2c_stm32_msg_start() that will be needed to
manage DMA, in case the DMA configuration fails.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Depending on the series, the JPEG HAL requires either MDMA or
DMA HAL and for some series DMA_EX HAL is required as well.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Copy beacon/probe data under vif_lock, then post the net_mgmt
event without holding the lock. Avoids stalling firmware RX when
the event queue backs up during raw scan floods.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Cursor:Auto
