Add gnttab_query_size() to expose GNTTABOP_query_size through the
public Xen grant table helper API.
The helper accepts operation arguments directly, builds the Xen ABI
request internally, and returns the per-operation GNTST_* status through
an output parameter.
Signed-off-by: Vladyslav Goncharuk <vladyslav_goncharuk@epam.com>
Assisted-by: Codex:gpt-5
bt_nxp_close() was a no-op, violating the bt_hci_close() contract that
requires the transport to be fully closed before the function returns.
After bt_hci_close() cleared data->recv, the NXP HAL could still fire
the RX callback, and on a quick reopen stale packets could be delivered
into the new session.
Deregister the HCI RX callback via PLATFORM_SetHciRxCallback(NULL) and
propagate any error so bt_hci_close() only clears data->recv after the
transport is confirmed closed. With CONFIG_HCI_NXP_RX_THREAD, a plain
K_NO_WAIT drain loop is not sufficient: when bt_rx_thread is blocked in
k_msgq_get(K_FOREVER), k_msgq_put() hands the frame directly into the
thread's stack buffer without touching msgq->used_msgs, so the drain
misses any frame the thread already holds. Add bt_nxp_rx_drain(): flush
buffered frames, post a sentinel (data == NULL) with K_FOREVER, and
wait on rx_drain_sem until bt_rx_thread acknowledges it. Because the
queue is FIFO, the acknowledgement guarantees every pre-close frame has
been processed before close returns.
Signed-off-by: Guotao Zhang <guotao.zhang@nxp.com>
Enable Wireless Location Service (WLS) by default when NXP IW61X SoC
and WIFI_NM_WPA_SUPPLICANT are enabled. WLS supports 802.11mc (FTM)
and 802.11az (Next Generation Positioning) features.
Signed-off-by: Keval Thakker <keval.thakker@nxp.com>
An underrun maybe expected if, for instance, the controller is polling
to know if there's something to read. However, current logging was
logging URUNNACK (the underrun condition) with error level, which was
annoying (many messages per second depending on the controller's polling
rate).
This patch changes it so that underruns are only logged at debug level.
Assisted-by: Copilot-CLI:claude-opus-5
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
npcx_i3c_target_ibi_raise() is defined unconditionally, but the
.ibi_raise entry of the driver API that references it sits inside a
CONFIG_I3C_USE_IBI guard. Building with CONFIG_I3C_USE_IBI=n leaves
the function unreferenced and the compiler warns:
warning: 'npcx_i3c_target_ibi_raise' defined but not used
[-Wunused-function]
Wrap the function in the same guard as its only user.
Assisted-by: Copilot-CLI:claude-opus-5
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Convert the native_sim_timer system-timer driver to the generic tickless
timer core. The core takes over the tick accounting, and what is left here
is the cycle-domain primitives for this hardware, for a COMPARE_ORDERED
backend.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The IRQMP driver implements the interrupt source query used by the
SPARC interrupt trap path under an arch-namespace name,
z_sparc_int_get_source(), declared in the SPARC arch header. The
function is driver code, not arch code: rename it to
intc_irqmp_get_source(), declare it in the driver header next to
the rest of the API, and have the trap path call the driver API
directly, matching how the arch_irq_* control functions are already
mapped to this driver in the same file.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The IRQMP driver defines arch_irq_enable(), arch_irq_disable() and
arch_irq_is_enabled() directly. Interrupt controller drivers should
only expose their own namespaced API; providing the architecture
interrupt control functions is platform glue and does not belong in
a driver.
Rename the functions to intc_irqmp_irq_* and declare them in a
driver header. The arch_irq_* mapping goes into the SPARC arch
layer, not the SoCs: the port is already coupled to an IRQMP-style
controller -- the interrupt trap path queries it for the interrupt
source -- and every SPARC SoC uses it, so mapping it once in
arch/sparc/core/irq_manage.c under CONFIG_LEON_IRQMP serves all of
them. An SoC with a different controller can leave the option
disabled and provide its own implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Basic Timer PRE_SCALE field divides the input clock by
(prescaler + 1) per the datasheets, not by the raw prescaler value.
Update the frequency calculation to divide by (prescaler + 1) and
correct the binding description to match.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The driver calls IRQ_CONNECT() and irq_enable() but never includes
zephyr/irq.h, relying on it arriving indirectly. That does not always
hold: building samples/drivers/counter/alarm for an Arm Cortex-M
target fails with implicit declarations of both. Fix this.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
counter_dw_timer_init() reads the timer clock rate from the clock
controller but never requests the clock, so it relies on the clock
already being enabled by other means. clock_control_get_rate() is
documented to return -EAGAIN when a driver cannot report the rate of a
clock that is off.
Request the clock with clock_control_on() before reading its rate.
-ENOSYS is tolerated so that clock controllers implementing only
.get_rate keep working, and -EALREADY for controllers that report an
already-enabled clock that way.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add basic support for the AMD Versal Gen2 Clocking Wizard driver in the
Zephyr clock control subsystem. This hardware is used to generate
and control clocks on the Versal Gen2 platform.
Currently supported features:
- Configure the output clock frequency
- Read the current output clock frequency
- Enable/disable clock outputs
Signed-off-by: Beesam Sridhar Sagar <sagar.beesamsridhar@amd.com>
The eth_nxp_enet_qos_mac.c driver programs the MAC in a sequence that
violates the Synopsys DWC_ether_qos databook. This fixes that.
Signed-off-by: Martin Oliver Pitoňák <martin.pitonak@nxp.com>
The DCS display inversion state was never written, and the power-on
state of some panels is not deterministic, resulting in an image with
complemented colors on a random basis. Add an inversion-on devicetree
property and always program the state explicitly.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Vendor initialization sequences for ST7701S-based panels commonly
program additional registers: a Command2 BK3 setting (EFh), extra GIP
settings (E9h, BK1 EFh), and panel-specific values for the display line
setting (C0h), porch control (C1h) and CCh registers. Add optional
devicetree properties for these, keeping the existing computed or
hard-coded values when they are absent.
Add build assertions so a devicetree array that does not fit its
fixed-size configuration field fails the build instead of being
silently truncated.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The inversion selection (C2h) and the Command2 BK1 power and source
timing registers (Vop, VCOM, VGH, VGL, power control, source pre-drive,
MIPI setting) were hard-coded. These are panel-specific analog drive
parameters that panel vendors specify per module; expose them as
optional devicetree properties defaulting to the previously hard-coded
values.
The undocumented B9h register is now written only when the b9 property
is present. It was previously always written, but due to the short
write length bug its parameter never reached the panel, so no board
relied on a specific value.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The GIP and gamma configuration commands were always written with the
full size of their fixed-size config fields. A property shorter than
the field was padded with trailing zero parameters on the wire, and an
absent property was sent as an all-zeros packet instead of leaving the
controller's power-on default untouched.
Track the devicetree-provided length of each setting and write exactly
those bytes, skipping settings that are not set.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The LNESET (C0h) command was hard-coded to 0x63, which configures the
panel for (0x63 + 1) * 8 = 800 lines. Compute the value from the panel
height instead so panels other than 480x800 work. Existing 800-line
users are unaffected.
Heights that are not a multiple of 8 are encoded using the extra-line
delta field (LDE_EN + Line_delta), matching the reference formula
NL = (Line[6:0] + 1) * 8 + (LDE_EN ? Line_delta[1:0] * 2 : 0). A build
assertion rejects odd heights, which cannot be represented.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Not all MIPI-DSI host drivers implement DCS read transfers, e.g. the
NXP RT11xx DSI host returns -ENOTSUP. Failing the panel ID check in
that case aborts the panel initialization entirely on otherwise
functional hardware. Log a warning and continue instead.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The ST7701S datasheet requires 120 ms after the Sleep Out command
before the display is fully functional; the driver only waited 50 ms.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
st7701_short_write_1p() passed sizeof(val), which is 1, instead of
sizeof(buf) as the length, so every one-parameter write was transmitted
as a Generic Short Write with the command byte only. The controller
interprets such a packet as carrying parameter value 00h, so the entire
Command2 BK1 bank (Vop amplitude, VCOM, VGH and VGL voltages, power
control, source pre-drive timing and MIPI settings) was programmed to
zero on every panel initialized by this driver, resulting in unstable,
fading and heavily flickering output.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The driver never programs the per-address multicast hash table and does
not advertise ETHERNET_HW_FILTERING, so the stack never installs a group
filter. On a MAC that reports a hash table (HASHTBLSZ is nonzero) that
combination dropped every multicast frame, which breaks IPv6 neighbor
discovery and MLD group membership, so a joined group received nothing.
Set the pass-all-multicast bit unconditionally so joined groups are
delivered. The prior code set it only when the MAC reported no hash
table, but pass-all is needed in strictly more cases than that: the
driver never populates the hash table, so perfect multicast filtering
is unavailable regardless of the reported hash-table size.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This MAC gates inbound multicast through the group-address hash
(GAUR/GALR), which starts empty after ENET_Up. The driver advertises
ETHERNET_HW_FILTERING and installs a hash bit for every group the
stack joins, so IP multicast joined through the stack (including IPv6
neighbor discovery and MLD group membership) is delivered. Multicast
that the stack never joins, such as traffic received through a raw
packet socket, has no hash bit installed and is dropped by the MAC.
Add ETH_NXP_ENET_MULTICAST_FILTER (default y) to preserve the existing
hash-filtered behavior. When it is disabled, the driver stops
advertising ETHERNET_HW_FILTERING, skips the per-group hash
installation, and opens the group-address hash to every multicast
address so reception no longer depends on per-group installation. This
follows the ETH_NXP_S32_MULTICAST_FILTER and ETH_STM32_MULTICAST_FILTER
options already in tree.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ() calls with
k_irq_set_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it. These platforms are
plain-NVIC Cortex-M, so the pending-state capabilities are always
available where this code builds.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update comments, log messages, and driver-local identifiers to use
the controller/target terminology ratified by coding guideline A.2
and already used by the Zephyr I2C API.
Identifiers mirroring the Atmel/Microchip datasheets
(e.g. SERCOM_I2CM_CTRLA_MODE_I2C_MASTER, TWIM_CMDR_HSMCODE, and the
TWI/TWIHS register mnemonics) are kept unchanged. The hs_master_code
config member is also kept, as it holds the hs-master-code devicetree
property, whose name is unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Add support for both dedicated and shared IRQ lines based on
devicetree configuration using num-dedicated-irqs property.
- Dedicated IRQ: One IRQ per channel, uses CHINTFLAG register
- Shared IRQ: Multiple channels share one IRQ, uses INTPEND register
- Generate IRQ ISR functions using LISTIFY macro
- IRQ type (dedicated/shared) determined at compile time from DTS
Example: num-dedicated-irqs = <4> means ch0-ch3 have dedicated IRQs,
ch4+ share the remaining IRQ line.
Note: This dual-path design is required by hardware behavior, not just
an optimization. Channels with dedicated interrupt lines do not refresh
the INTPEND register (as per datasheet section 24.5.4), so the shared
handler using INTPEND is valid only for multiplexed channels, while
dedicated channels must use CHID and CHINTFLAG directly.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add a SmartDMA-accelerated transfer path as an alternative to the
generic-DMA (e.g. eDMA) back-end, selectable via
MIPI_DBI_NXP_FLEXIO_LCDIF_SMARTDMA.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Introduce an interactive multi-vector steering redirection table
probe subcommand to the common PCIe host shell driver layer.
The IRQ subsystem extracts MSI-X registers using pcie_get_cap()
offsets, decoding allocated vector pools and exposing steering
offsets via standard Base Address Register (BAR) bitmasks.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Introduce a dynamic hardware capability offload telemetry probe
command to the common PCIe host shell subsystem layer.
The capability subsystem automatically resolves and decodes the
Device Capabilities 2 (DEVCAP2) register map via the native
pcie_get_cap() engine. It evaluates bitmasks for Alternative
Routing-ID (ARI) and Single-Root I/O Virtualization (SR-IOV).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie link speed <bus:dev.func>' shell subcommand to allow
runtime discovery, interrogation, and bitfield decoding of the PCI Express
Link Capabilities and Link Status capability registers (Cap ID 0x10).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie device state <bus:dev.func> up|down' shell
subcommand to allow runtime interrogation, status tracking, and
bit-level state mutation of the standard PCI Power Management
Capability block (Cap ID 0x01).
The command scans the traditional capability linked list within
traditional configuration space to locate the power block base offset.
It utilizes a read-modify-write routine targeting the Power Management
Control/Status Register (PMCSR) to transition the underlying hardware
transceiver between the D0 Fully Operational state (00b) and the
D3hot Low Energy Suspend state (11b).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie link margin <bus:dev.func>' shell subcommand to
allow runtime discovery, interrogation, and bitfield decoding of the
PCI Express Lane Margining at Receiver extended capability structures
(Extended Cap ID 0x001A).
The command dynamically traverses the PCIe Extended Configuration Space
(offsets >= 0x100) to isolate the margining block base. It reads the
underlying hardware registers and unpacks the 16-bit Port Capabilities
and Control fields to report maximum voltage/timing steps, total link
widths, and independent per-lane software execution controls. It also
polls active receiver signal status flags and bounds tracking limit
thresholds.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie aer status <bus:dev.func>' shell subcommand to allow
runtime interrogation and decoding of the PCI Express Advanced Error
Reporting (AER) capability registers.
The command handles hardware traversal across the PCIe Extended Capability
Space (offsets >= 0x100) to dynamically isolate the AER capability block
and read configuration space registers. It decodes uncorrectable fatal
and non-fatal register flags—including Link Training errors, Data Link
Protocol errors, Poisoned TLPs, and Flow Control Protocol breakdown states—
as well as correctable signal layer degradation deviations.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a `pcie irq status` sub-command to the common
PCIe host shell subsystem layer.
The utility decodes legacy INTx pin and line metrics, structures real-time
traversals across standard device capabilities loops, and maps standard
MSI (Cap ID 0x05) and MSI-X (Cap ID 0x11) status parameters. The resulting
trace logs track active configuration states, vector capabilities, target
message address fields, and MSI-X table sizing dimensions to simplify
embedded hardware interrupt triage tasks.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a `pcie link set_speed` sub-command utility
to the PCIe host shell subsystem layer.
The tool locates the native PCI Express Capability structure (Cap ID
0x10), updates the Target Link Speed bitfield inside the Link Control
2 register, and issues a Retrain Link command override to the physical
layer. This enables developers to interactively scale bus power and
performance profiles directly from the command line window.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a standalone root-level shell command utility
named `pcie_resource` to decode and evaluate PCIe Base Address Register
(BAR) spaces dynamically from the serial console interface.
The command operates within its own dedicated top-level namespace to
prevent redefinition conflicts with existing shell subsystem tables. It
iterates through standard configuration offsets (BAR0 to BAR5), executes
the standard PCI write-all-1s probing algorithm to calculate resource
footprints, and decodes aperture characteristics natively. The output
provides human-readable size geometry metrics, 32-bit vs. 64-bit bounds,
prefetchable memory attributes, and I/O port address space layouts.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Introduce a dynamic software-based masking registry table to
the common PCIe host subsystem layer via the shell.
The masking subsystem features an explicit hook callback pointer that can
be runtime-registered via dynamic terminal command invocations. When
active, the core `scan_dev` device bus enumerator intercepts the BDF
coordinate before running the physical hardware registers discovery
sweeps. If a target slot matches a registered ignore block, it is
gracefully bypassed.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces an interactive `pcie write` sub-command to
the native PCIe kernel shell subsystem layer.
The utility accepts string arguments from the terminal prompt,
checks for link responsiveness via PCIE_CONF_ID to prevent
unmapped interconnect bus lockups, and invokes the low-level
`pcie_conf_write` function directly over the target configuration
space index parameters. An immediate read-back verification
check is executed to confirm latch status stability.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
When a power-domain-soc-state-change domain powers off, its visitor
suspends any ACTIVE child before turning it off. That suspend is issued
directly through pm_device_action_run() and is not recorded in the
system-managed PM device slots, so pm_resume_devices() never resumes the
device: on wake it is powered back only to SUSPENDED via TURN_ON and
never returns to ACTIVE.
Track devices the domain suspends and resume them symmetrically on
TURN_ON, so the actor that suspends a device is the one that restores it.
A failed TURN_ON still leaves the device in SUSPENDED and sets
PM_DEVICE_FLAG_TURN_ON_FAILED, so skip the resume in that case rather
than reporting a device as ACTIVE on hardware that was never powered.
Fixes#112333
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
spi_esp32_get_line_mode() takes the SPI operation as a uint16_t, but the
line-mode bits SPI_LINES_DUAL/QUAD/OCTAL live at bit 16 and above of the
spi_operation_t type, which is widened to uint32_t when
CONFIG_SPI_EXTENDED_MODES is enabled. Passing the full operation into the
uint16_t parameter truncates those bits, so operation & SPI_LINES_MASK is
always 0 and the function always reports single-line mode. Any request for
dual, quad or octal lines is silently downgraded to single-line, driving
only the D0 data line.
Widen the parameter to uint32_t so the line-mode bits survive, matching
how every other SPI driver reads the operation. Verified on an
ESP32-S3-Touch-AMOLED-1.8 QSPI panel, where quad transfers only produced
correct colors with this fix.
Signed-off-by: Dylan Rowe <dylanthomasrowe@gmail.com>
RDJDID (9Fh) on this part returns 9d 60 1a, so the existing 0x20609d
case never matched and the driver fell through to the SFDP path. Add
the ID the part reports, keeping 0x20609d alongside it.
Signed-off-by: Emilio Bottoni <emilio.bottoni@edge.ufal.br>
Currently, the CAN frame is only zeroed at the start of the function,
and if multiple frames are read in a single pass, any flags that were
ORed into the flags field will be carried into later frames, even if the
later frame should not actually have those flags set. Instead, leave the
frame variable uninitialised and zero it out on each iteration loop.
Signed-off-by: Zee Yudenko <zyudenko@internships.antmicro.com>
Update comments to use the controller/target terminology ratified by
coding guideline A.2 and already used by the Zephyr I2C API.
Identifiers mirroring the ITE datasheet
(e.g. ITE SMBus host/target register mnemonics SMB_* and their verbatim
datasheet register-title comments, ITE IT8XXX2_SMB_* / IT8XXX2_I2C_*
register accessor macros, ITE command-queue datasheet bit names) are
kept unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Update comment and driver-local identifiers to use the
controller/target terminology ratified by coding guideline A.2
and already used by the Zephyr I2C API.
Identifiers mirroring the DesignWare databook
(e.g. IC_CON union bitfields, IC_TAR union bitfield ic_10bitaddr_master,
IC_TX_ABRT_SOURCE union bitfields) are kept unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The driver provided no .i2c_api.configure hook, so the I2C bus speed
could only be set from devicetree and i2c_configure() faulted on the
unset function pointer. Map the standard speed selectors onto
ctrl_config.scl.i2c and reprogram the SCL timing, following
cdns_i3c_i2c_api_configure(). Speeds above fast mode plus are
rejected; the IP has no timing register beyond SCL_I2C_FMP_TIMING.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
The i2c-scl-hz property was parsed into ctrl_config.scl.i2c and never
read; SCL_I2C_FM_TIMING was always computed for the fixed
I3C_BUS_I2C_FM_SCL_RATE. Derive it from the configured rate, holding
tLOW at the spec floor for the mode that rate falls in, 4.7us at or
below 100 kHz and 1.3us above. Fall back to the attached devices' LVRs
when unset, and clamp HCNT and LCNT to their 16-bit fields, which the
register macros otherwise mask silently.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
dw_i3c_configure() validates a new controller configuration by calling
dw_i3c_init_scl_timing() before storing it, but the push-pull timing
read scl.i3c back from data->common.ctrl_config, which still held the
previous value. A new I3C SCL rate therefore only took effect on the
following call. Read it from the passed-in configuration, as the open
drain minimums already are.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
The I3C_CONFIG_TARGET branch casts the config argument and writes
through it without a NULL check. Assert on it up front.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
