Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
This driver called the arm_gic_irq_* pending helpers directly; the
portable API removes the GIC-specific dependency. The gic.h include
stays for GIC_SPI_INT_BASE.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace the direct NVIC_ClearPendingIRQ() call with
k_irq_clear_pending() and drop the cmsis_core.h include.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace the direct NVIC_ClearPendingIRQ() call with
k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There are some situations where a NACK is expected from
the target after sending the address. One example would be
MCTP, where the target would NACK if there is no data to return
during polling. This use case is not entirely conforming to
traditional I2C/I3C transfer mechanism where a NACK after
the address byte means there is no target with this address
or the target is not responding to the transfer request.
In order to support MCTP, we will need to handle this type of
transfer gracefully, by adding a new transfer message flag to
indicate this type of transfer. A new return value is also
being introduced to i3c_transfer() to signal the expected NACK
is received. Since most of the wire interactions are handled
by the hardware, each individual driver will need to purposely
handle this use case. For now, this commit only introduces
the building block needed for the drivers to implement the bits
to support this use case.
Also changed the RTIO generic I3C code to support this.
Relates to #114312
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Replace the direct NVIC_ClearPendingIRQ() call in the RTS5912 quirk
path with the portable k_irq_clear_pending() and drop the cmsis_core.h
include, removing the last piece of CPU-specific code from the
DesignWare I2C driver. RTS5912 is a plain-NVIC Cortex-M33, so the
capability is always available where the quirk compiles.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
i2c_dw_transfer_complete() clears the NVIC pending bit for its own IRQ
line after clearing the IP-level interrupt source. This was added along
with the RTS5912 support in commit 748789eadf ("drivers: i2c: rts5912
i2c dirver") but gated on CONFIG_CPU_CORTEX_M, so every Cortex-M user of
the DesignWare IP -- RP2040/RP2350, SiWG917, Synaptics SR100 -- silently
inherited a Realtek-specific workaround, and the shared IP driver grew a
dependency on cmsis_core.h.
Clearing the NVIC pending bit after the source has already been cleared
also discards any interrupt that latched in between, so it is not a
harmless no-op on parts that do not need it.
Gate the call, the cmsis_core.h include and the irqnumber config member
on CONFIG_I2C_RTS5912 instead, matching the other RTS5912 carve-outs
already present in Kconfig.dw. Behaviour on RTS5912 is unchanged; other
Cortex-M platforms return to the pre-748789eadf710 behaviour. Dropping
irqnumber for everyone else also removes a DT_INST_IRQN() on PCIe
instances, which have no devicetree interrupt of their own.
Also drop the unused zephyr/arch/cpu.h include added by the same commit;
it is a pure dispatch header and kernel.h and irq.h already provide
everything the driver uses.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The native TLS socket layer calls zsock_fcntl(F_GETFL) on the
underlying offloaded socket to clear and restore O_NONBLOCK around the
TLS handshake (ztls_connect_ctx), before issuing the underlying
connect. offload_ioctl() only handled the poll ioctls, so the fcntl
failed with EINVAL and any connection over TLS-native sockets on top of
this driver aborted before AT+CAOPEN was ever sent, with only a
confusing "AT+CACLOSE=0 ret: -5" from the cleanup path in the log.
Handle ZVFS_F_GETFL and ZVFS_F_SETFL by returning 0: the offloaded
socket is always blocking and non-blocking reads are requested per
call via MSG_DONTWAIT. This is the same approach used by the
ublox-sara-r4 and hl78xx drivers.
Tested on SIM7080G (Cat-M1) hardware against an MQTT broker on port
8883 with CONFIG_NET_SOCKETS_SOCKOPT_TLS=y and CONFIG_MQTT_LIB_TLS=y:
without this change mqtt_connect() always fails with -EINVAL; with it
the TLS handshake and MQTT session complete normally.
Note: this issue was diagnosed and the fix developed with the
assistance of an AI tool; the change was reviewed and verified on
real hardware by the author.
Assisted-by: AI tool (Claude Code)
Signed-off-by: Angel Covarrubias <angelcovarrubias319@gmail.com>
TIMER_CORE_MAX_UNANNOUNCED_CYCLES was the smaller of two unrelated
limits: what the counter can still resolve, and what the alarm can
express. The tick clamp divides by it, so where a tick is longer than the
alarm can hold, it comes out zero and the arm path collapses:
span = 0 /* clamped */
want = 0 * CYC_PER_TICK = 0
rel = (want > done) ? want - done : 0 /* 0 */
rel < ALARM_MIN /* floored */
set_reload(ALARM_MIN)
On frdm_mcxn947 at 150 MHz with CONFIG_SYS_CLOCK_TICKS_PER_SEC=1 a tick
is 150000000 cycles against a 24-bit SysTick reload of 16777215, so the
driver arms 1499 cycles, the 10 us floor, and interrupts 78000 times a
second announcing nothing. Asking for one tick a second then costs more
interrupts than any other tick rate.
Only the counter's reach bounds how much unannounced time may accumulate.
The alarm's reach bounds a single arm. Split them:
MAX_UNANNOUNCED_CYCLES = COUNTER_SAFE_SPAN
MAX_ARM_CYCLES = MIN(COUNTER_SAFE_SPAN, ALARM_MAX_CYCLES)
The tick clamp uses the first, so a tick always fits, and each arm is
capped at the second. That board now spans 14 ticks and arms 16777215
cycles at a time, nine interrupts to cross one tick, which is what the
driver already did for a timeout longer than its reload.
The cap is guarded on the two bounds differing, so it folds away where
the alarm covers the whole span and the span clamp has already bounded
the value.
Fixes: #117169
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Centralise the GPIO arbitration and remove duplication. Add initial value
setting based on provided flags.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
The functions eusart_silabs_ll2cfg_*() have never been used. Probably the
original author wrote them for the completeness since their
eusart_silabs_cfg2ll counterparts were required.
Orphan function generate warning that could in turn generate error with
-Werror.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The functions uart_silabs_ll2cfg_*() have never been used. Probably the
original author wrote them for the completeness since their
uart_silabs_cfg2ll counterparts were required.
Orphan function generate warning that could in turn generate error with
-Werror.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The dai_config_set()/dai_config_update() syscall verifiers copied the
user-space bespoke configuration blob into a fixed stack buffer of
CONFIG_DAI_MAX_BESPOKE_CFG_SIZE bytes and rejected anything larger with
-EINVAL. This turns out to be too limiting and we need to support larger
configuration objects.
Decouple the stack buffer size from the maximum allowed blob size and
change implementation such that objects up to DAI_BESPOKE_CFG_STACK_SIZE
are validated on the stack as before, but for larger objects,
k_malloc'ed kernel buffer is used instead.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Since recover-bus-on-init DT property if of boolean type, use of
dt_compat_any_has_prop() without an explicit value argument of True
makes that function to always return true and
CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY and
CONFIG_I2C_MCUX_FLEXCOMM_BUS_RECOVERY configuration options always enabled
(when their dependencies are met).
Set function argument value to True to get the expected behavior.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The AHB GDMA path passed dma-host, the SPI host index, as
the DMA peripheral trigger. That happens to match on SoCs
where the SPI2 trigger is zero, but on esp32c5 and esp32c61
the SPI2 trigger is 1, so RX and TX were connected to the
wrong peripheral and no data was transferred. Derive the
trigger from the SPI2 base as the AXI path already does.
spi_loopback DMA mode passes on esp32c5 and esp32c61.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The esp32c5 and esp32c61 devicetree binding value for the rc
fast cpu clock source does not match the hal enum, so the
fallback comparison could accept a pll configuration when rc
fast was requested. Compare the rc fast case explicitly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Wire the esp32c61 into the pmu clock driver: per-soc
includes, the rc32k exclusions, the regi2c slow-clock
tuning writes, the devicetree clock-source mapping for the
fixed 160 MHz pll, and clocking the console uart from xtal
since the bbpll is transiently disabled during ocode
calibration. Configure the regi2c analog master clock when
the cpu runs from the pll, as done for esp32c6, and guard
the deprecated periph_module calls out as on the esp32p4.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
pgain was shifted by one instead of two, so the selection landed below
the PGAIN field of register 0x8F and was masked away entirely: every
board ran at 1x proximity gain no matter what devicetree asked for.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The ppulse-length selection was OR'd straight into ppcount, landing in
the PPULSE pulse-count bits instead of PPLEN (bits 7:6) of register
0x8E. Every configuration therefore ran with 4 us pulses, and the 16 and
32 us selections corrupted the pulse count on top of that.
Shift the selection into PPLEN and mask the count to the six bits the
field actually has.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The pgain, again, ppulse-length and pled-boost enums spelled the 2-bit
register fields they select in hex, i.e. 0x00/0x01/0x10/0x11, so the
last two selections were really 16 and 17 and reached the registers as
such. The pgain entries were also mislabelled, listing 4x twice instead
of the 1x/2x/4x/8x the part supports.
Express each enum as the physical value it selects - gain multipliers,
microseconds and percent - and let DT_INST_ENUM_IDX() turn the selection
back into the register field value, which the enums are already ordered
to match. Devicetree now describes the sensor instead of its register
encoding, and the defaults keep selecting the same settings as before.
While here, give every default the justification the binding guidelines
require, and bound ppulse-count to the 1 to 64 pulses the PPULSE field
can encode.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit updates the usage of ring_buf to utilize the new
put_ptr/commit/get_ptr/consume pattern instead of the traditional
claim/finish approach. This change is part of a larger refactor aimed at
streamlining the ring_buf API and improving its efficiency.
Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
The OUTPUT_GAIN register codes 0..3 select a gain of 1/4/8/16, but the
12-bit frequency conversion used the raw code as a power-of-two exponent,
so any non-zero gain reported twice the actual frequency (and a quarter of
the actual capacitance). Map the code to its real log2(gain) instead.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
fdc2x1x_raw_to_freq() converted raw data using the raw controller
clock, ignoring the per-channel CHx_FREF_DIVIDER the driver programs
at init. The datasheet defines the conversion against the divided
reference f_REFx = f_CLK / CHx_FREF_DIVIDER, so frequency and
capacitance were wrong on any channel with a divider other than 1.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The CHx_FREF_DIVIDER field of CLOCK_DIVIDERS_CHx is 10 bits wide, but
the SET/GET accessors masked it to 9 bits while the field mask covered
bits 9:0, so any divider from 512 to 1023 was programmed as value-512.
Widen both accessors to 0x3FF to match the mask and the binding.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The channel mult/div scale factors are uint32_t, so the sign-extended
sample was converted to unsigned and the division performed unsigned,
turning negative readings into large positive ones (e.g. INA226 shunt
voltage, which uses 2500/1000). Scale in signed 64-bit arithmetic.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
struct ina230_data did not start with a struct ina2xx_data, so the
shared ina2xx_sample_fetch()/ina2xx_channel_get() code, which casts
dev->data to struct ina2xx_data *, wrote raw register bytes over the
cached device pointer used by the alert trigger. Embed the common data
struct as the first member and drop the now unused value fields.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The PM hook only handled TURN_OFF, which the PM core rejects unless the
device is already suspended, so the shutdown and wake sequences were
unreachable and the gauge kept running. Handle SUSPEND to enter shutdown
mode and accept TURN_ON/TURN_OFF as no-ops.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Exiting shutdown mode causes a POR that reverts the gauge data memory
to its ROM defaults, but data->configured was never cleared, so devices
using zephyr,lazy-load kept reporting values computed from the default
design parameters. Clear the flag on resume so the next sample fetch
reprograms the gauge.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The aligned path clears FBYTE and computes a word count but set
byte_mode to true, and the unaligned path did the opposite, so
manual transfers moved a quarter of the data or overran the buffer
fourfold. Swap the two assignments to match the FBYTE setting.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The LL_IPCC_GetChannelConfig() function is Zephyr-specific and was added
via a patch to hal_stm32 when STM32CubeMP1 v1.0.0 was in use, as this
version of the package lacked a function to get the number of channels
in the IPCC...
In STM32CubeMP1 v1.1.0, function LL_IPCC_GetChannelNumber() was added
and should have replaced the custom one... but never did! Both the
custom function and its user lingered in tree since then...
Since LL_IPCC_GetChannelNumber() exists in both MP1 and MP2 packages
and is the *official* name, drop the #if series check and just use
that function unconditionally on all series. This will allow removal
of the custom LL_IPCC_GetChannelConfig() in the future.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The divider was left at its reset value, so with a pll source
the peripheral input exceeds its limit and the first clocked bit
is corrupted on esp32p4. Compute an even divider that respects
the limit and program it when the device is configured.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The interrupt path released the context without waiting, so a
synchronous caller could read the rx buffer while the isr was
still filling it. Wait for completion before releasing.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Without this esp_clk_tree_enable_src() is a no-op, so the pll
reference branches keep their cold-boot state. On esp32p4 the
80 MHz branch comes up gated and the timers never tick. Run it
from the clock driver rather than early boot, where gating the
branches stalls the flash bus.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The polling read programmed the chip-global unit and started the
conversion unlocked, so concurrent reads could return another
caller's channel or attenuation. Take the same per-unit lock the
dma read path already uses.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The key registers are chip-global but the key was written once
at session start with no lock held, so two sessions with
different keys could encrypt under each other's key with no
error. Program the key inside aes_lock on every operation.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Allow an LPADC channel node to reference an optional bandgap supply.
Enable the supply when channel setup selects the physical input
described by that node so continuous monitoring needs no additional
application control.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Expose the buffered SPC bandgap output through the regulator API so
consumers can acquire it only while needed. Use the common regulator
reference counting and always-on policy instead of defining a separate
resource lifecycle.
The output has a fixed voltage and supports enable and disable operations.
Device PM restores the hardware state when an active regulator resumes.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Following the standard pattern for sensor Kconfig files and
allows access to the named choice symbol QMI8658A_TRIGGER_MODE
from out-of-tree Kconfig files. Also add conditional GPIO select
when any binded DTS node expose a int-gpios property.
Signed-off-by: Stephan Linz <linz@li-pro.net>
CH_RESUME_WE() and CH_RESUME() expand to bit masks, but resume
passed them to WRITE_BIT(), which expects bit positions, shifting
by the mask value and leaving the suspend bit untouched. Operate
on the masks directly.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Remove remaining uses of the internal __ASSERT_ON macro. Let __ASSERT()
handle disabled assertions, mark assert-only values as unused where needed,
and use CONFIG_ASSERT for assertion-only state.
Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
__ASSERT_MSG_INFO() is an internal helper of <zephyr/sys/__assert.h>, not a
public API. A handful of drivers and inline helpers called it directly to
emit a message without an accompanying assertion.
Replace those direct uses with the appropriate mechanism: LOG_ERR() for the
recoverable runtime error paths in the display, RTC, SPI and CRC code, and
__ASSERT(false, ...) for the out-of-range programming errors in the ADC and
DAC inline helpers.
Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
Invert the in-tree ethernet driver configuration logic.
The current logic is boards enabling `NET_L2_ETHERNET`, which then
unconditionally defaults `ETH_DRIVER` to enabled. This means that
`ETH_DRIVER` end up set for boards that use the L2 Ethernet layer but
don't have an ethernet device (see some WiFi drivers).
This commit:
* Removes the `default y if NET_L2_ETHERNET` from `ETH_DRIVER`
* Adds `default y if ETH_DRIVER` to `NET_L2_ETHERNET`
* Adds `imply ETH_DRIVER` to `NET_QEMU_ETHERNET`
* Updates in-tree ethernet boards to default `ETH_DRIVER` instead of
`NET_L2_ETHERNET`
The outcome of this PR is that Kconfig can now use `ETH_DRIVER` to
reasonably assume that an actual ethernet driver is enabled.
Conversion of in-tree boards/samples performed by GPT-5.5.
Assisted-by: GPT-5.5
Signed-off-by: Jordan Yates <jordan@embeint.com>
Update comments, log messages, Kconfig prose, and driver-local
identifiers to use the controller/target terminology ratified by
coding guideline A.2 and already used by the Zephyr I2C API.
Identifiers mirroring the Renesas Smartbond datasheet
(e.g. I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk,
I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk,
I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk) are kept unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The MAPD command's size field declares ITT capacity as 2^(size+1).
The size was computed from nr_ites via fls_z(nr_ites) - 2, which is
only correct when nr_ites is a power of 2.
For non-power-of-2 values (e.g. 5), the resulting ITT is too small,
causing MAPTI commands for higher event IDs to be rejected by
hardware and the ITS command queue to time out.
Fix by rounding nr_ites up to the next power of 2 before computing
size and allocating ITT memory.
Signed-off-by: Chang Jianpeng <changjianpeng@kylinos.cn>
Update comments, log messages, Kconfig prose, and driver-local
identifiers to use the controller/target terminology ratified by
coding guideline A.2 and already used by the Zephyr I2C API.
Identifiers mirroring the ESP-IDF HAL
(e.g. i2c_ll_master_*, i2c_hal_master_*, i2c_hal_slave_init) are kept
unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
