data->target_config is NULL until i3c_target_register() is called by
the application layer. The I3C bus master can assert a STOP condition
during board init before registration occurs, firing the ISR while
target_config is still NULL.
Both npcx_i3c_target_isr() and npcx_i3c_target_xfer_end_handle()
unconditionally dereferenced data->target_config->callbacks, causing
an MPU Instruction Access Violation when the resulting garbage pointer
was used as a function pointer.
Guard the callbacks pointer derivation with a NULL check on
target_config in both sites. Existing per-callback NULL guards
downstream already handle the NULL case correctly.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
The escape_conf bits reset to 1 and were left set, escaping 0xC0 and
0xDB on the async path even with SLIP off. Clear them, then enable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
use min-len/max-len for asserting the correct length of the
array, drop corresponding build asserts
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The driver discarded the load offset returned by pio_add_program() and
started the state machine with pio_sm_init(pio, sm, -1, ...). The -1 is
silently masked to PC 31 by pio_encode_jmp(), which only works by
accident while the ws2812 program is the sole program in the PIO
instance: top-down placement puts it at offsets 28..31, and PC 31 then
happens to hit the program's final jmp back to its start.
As soon as another program is loaded into the same PIO instance first
(lower init priority), the ws2812 program is placed at a lower offset.
The SM then starts inside foreign code, falls through into empty
instruction memory and loops there forever, so the data pin stays
silent without any error being reported.
Store the offset in a data struct of the parent PIO program device and
pass it to pio_sm_init() as the initial PC, with error handling for
exhausted instruction memory. Parent-before-child init order is given
by the devicetree dependency ordinals; a device_is_ready() guard is
added as a safety net.
Signed-off-by: Andreas Petter <andreas@ibpetter.de>
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Simplifies the sys_clock_set_timeout() calculation used to determine
the next correct cycle at which to trigger the timer interrupt. There
is no risk that number of cycles we are adding will exceed MAX_CYCLES.
--
Furthermore, should the current cycle count match the 'last_count',
it prevents the timer from firing one tick too early. That firing
would not lead to miscount of ticks, nor mis-execution of handlers.
However it could lead to one extra timer interrupt being processed
unnecessarily.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
Init the sensorhub targets using 8-bit i2c_addr for those drivers
when their STMEMSC API requires it.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
`uart_irq_tx_ready` should report true if transmit is empty
and the transmit interrupt is enabled. This isn't documented in
drivers/uart.h but is required by code such
`subsys/modules/modbus_serial.c` and implemented in drivers such as
`uart_sam.c` and `uart_stm32.c`.
Fix.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Add a driver for the u-blox M10 GNSS receiver.
It is heavily modeled on the F9P implementation.
Signed-off-by: Gaston Donikian <gastondonikian@gmail.com>
- Adds the CRC-32/MPEG-2 variant
(ISO/IEC 13818-1 Annex A, ITU-T H.222.0)
to both the software CRC subsystem and the CRC device API.
- Adds crc32_mpeg2() and crc32_mpeg2_update().
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Install flash functions at driver init, once the scheduler
is running, since early boot leaves the chip on the no-OS path.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For STM32H7, disable IRQ in RTIO when tranfer is completed to prevent
spurious IRQ to stall the system.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For st,stm32h7-spi compatible, always use the TSIZE register and the FIFO
for polling and interrupt mode. This increases performance compared to not
using it, and it reduces code complexity. This removes the need for the
fifo-enable property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For st,stm32h7-spi compatibles, when fifo-enable property is set, the
driver was setting the TSIZE register with the size of each buffer in the
transaction, leading to several disable/enable of the SPI instance.
Now, it sets the complete size of the transaction without intempestive
disabling of the SPI.
To add flexibility, the FIFO threshold is now configurable from a dts
property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit simplifies the flow of the STM32 SPI DMA transfer.
For the "st,stm32h7-spi" compatible, do not set the TSIZE register for a
DMA transfer (to define the size of the transfer). This setting was
leading to several disable/enable of the SPI instance in case multiple
buffers were used in the transaction, and it didn't bring noticeable
performance benefit. At the same time, do not use the SPI FIFO because
it's a hurdle to use without the TSIZE.
Rework the flow of initial operation to better match the procedure
described in the Reference Manuals.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When waiting for DMA transfer done, wait for both TX and RX, instead of
only one of them.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
sys_clock_set_timeout() computed the compare value as
cyc = ticks * CYC_PER_TICK + unannounced;
cyc = DIV_ROUND_UP(cyc, CYC_PER_TICK) * CYC_PER_TICK;
target = last_count + cyc;
The DIV_ROUND_UP forces the fire onto the next tick boundary *after*
the requested point, but the driver never subtracts the unannounced
sub-tick offset back out. When the caller arms partway through a tick
(the common case), the timer therefore fires one tick later than the
kernel asked for -- k_timer_start(K_TICKS(N), ...) ends up firing at
roughly N+2 ticks instead of N+1.
Adopt the absolute tick-aligned deadline pattern already proven in
arm_arch_timer.c and riscv_machine_timer.c:
- Track last_elapsed: the tick count the kernel last observed via
sys_clock_elapsed(). Reset to 0 in the handler at announce.
- sys_clock_set_timeout() computes the target as
target = last_count + (last_elapsed + ticks) * CYC_PER_TICK
and clamps the cycle delta from last_count at MAX_CYCLES so the
24-bit compare register is satisfied relative to the current
counter.
- The handler reads the current counter (not the scheduled expire
time) to compute dticks, advancing last_count to the actual tick
boundary just past now in one shot. This subsumes the previous
"wrap protection" branch: a large unannounced delta naturally
produces a target in the past, compare_set forces an immediate
IRQ, and the handler catches up in a single invocation.
- sys_clock_elapsed() records the delta in last_elapsed.
A v1 of this change (commit 67a29d7f98 ("drivers: timer:
nrf_rtc_timer: switch to absolute tick-aligned deadlines"), since
reverted) kept a separate "if unannounced >= COUNTER_HALF_SPAN,
target = last_count" branch. That broke the handler invariant:
dticks evaluated to zero, last_count never advanced, and the ISR
re-pended in an infinite loop once the counter naturally crossed
COUNTER_HALF_SPAN (~4m17s on nrf52). The structural change above
removes the need for any such recovery branch.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
add support for the stm32 f series in the
dwmac driver.
Assisted-by: Github Copilot:Claude Haiku 4.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
add support for the dwc_ether_mac10_100_1000_universal,
that is used, f.e. on the stm32 f series.
Assisted-by: Github Copilot:Claude Haiku 4.5
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add new KConfig BT_STM32WBA_BASIC_PLUS_LIB specifying the
configuration of the stm32wba ble library for bluetooth
basic plus features.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ support to pinctrl
driver for Infineon
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
The alarm ISR read data->alarm_active under the spinlock into a local
"rearmed" snapshot, released the lock, and only then acted on it by
stopping and reprogramming the LPTMR. That split the check from the
action: on SMP (or a nested context) a concurrent
counter_set_channel_alarm() could re-arm the alarm in the window
between the unlock and LPTMR_StopTimer(), and its freshly programmed
period/run state would be clobbered by the restore here.
Hold the lock across both the re-arm check and the stop/restore so the
decision and the HW action are atomic with respect to other lock
holders. Whichever context sets alarm_active under the lock owns the
timer configuration; the ISR only stops/restores when it observes
alarm_active == false while holding the lock, so it can no longer
overwrite a concurrent re-arm.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The alarm ISR was stopping and reprogramming the LPTMR before
invoking the user callback. Because LPTMR_StopTimer() resets the
counter back to zero, counter_get_value() called from inside the
callback observed 0 while the ticks argument still reflected the
pre-stop count. The single_shot_alarm scenarios in
tests/drivers/counter/counter_basic_api caught this as a large
diff between reported alarm and observed counter on
frdm_imxrt1186/mimxrt1186/cm7.
Move LPTMR_StopTimer() and LPTMR_SetTimerPeriod() to run after the
callback, skip them when the callback re-armed a new alarm via
counter_set_channel_alarm(): the counter API documents that the
channel becomes available inside the expiration handler and that
re-arming is allowed there.
Verified by building tests/drivers/counter/counter_basic_api for
frdm_imxrt1186/mimxrt1186/cm7 with armgcc.
Fixes#110250
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Switch to using a macro for declaring the Bosch M_CAN driver data struct
and have the macro statically initialize the k_mutex structures at build
time.
The "lock" mutex can be used by the vendor-specific driver front-ends
before the can_mcan_init() function is called (e.g. for configuring the
Message RAM), which will result in attempts to lock an unitialized k_mutex.
Fixes: #111031
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add frame buffering before delivering packets to speed up HAL frame
release.
Update IEEE802154 hw capabilities.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- DMA presence is detected from the definition in the device tree
and properties are added in the filter configuration structure
- DMA buffer is internally allocated depending on a configuration parameter
runtime checks are performed to ensure that kslab user allocation is not
too large respect to the internal buffer
- in the configure function the DMA is now configured
- start and stop functions are changed to support DMA if defined
in device tree
Signed-off-by: Daniele Aimo <d.aimo@arduino.cc>
Add a build assertion to ensure PLL1 DIVP division factor is not
an odd value different from 1 since not allowed as per SoCs reference
manuals.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
For Gen5 SoCs:
- Register offsets are different.
- The direction (either input or output) must be selected.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Convert the driver clock accesses to use the new generic API, so the
driver can be used on R-Car boards generations 3, 4 and 5 without changes.
Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
Synchronous RTIO I2C operations (RTIO_OP_I2C_CONFIGURE) and unsupported
or invalid RTIO I2C operations do call i2c_rtio_complete() but do not
trigger next message processing. Fix that ensuring synchronous operations
are each related to an RTIO completion notification.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Cleanup i2c_stm32_start() and i2c_stm32_msg_start() regarding their
return values. The return value of the former was not handled and
the later always succeeds.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Factorize STM32 I2C RTIO sequence completion instructions into a
common i2c_stm32_rtio_complete() helper function that applies to both
I2C STM32 v1 and v2 driver flavors.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add PM runtime support to I2C STM32 v1 driver in target mode in both
RTIO and non-RTIO drivers.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct unbalanced PM runtime device state in STM32 I2C v2 RTIO
and non-RTIO drivers in target client registering/unregistering.
In the target register sequence, put device runtime PM resources upon
on failure to register.
In the target un-registering sequence, put device runtime PM resources
when there remain a target as when 2 targets are registered, each has
get the device runtime PM resources, hence related reference counter
was incremented twice.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Filter out unsupported 10 bit address modes in STM32 I2C v1
driver in target mode before bus is enabled, preventing to leave
it enabled upon such configuration failure.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
If UARTE instance is using GPPI during the initialization and GPPI is
using Ironside then that instance need to be initialized once Ironside
and GPPI is initialized. Delay initialization to POST_KERNEL and
derive init priority from Ironside call init priority (+2 as +1 is
used by GPPI).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Inside the work that is scheduled by net_eth_carrier_on
and net_eth_carrier_off there is already a log message,
when the carrier changes, we don't need to log the same
info in the ethernet drivers.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a driver for VIRTIO input devices. Events are forwarded to the input
subsystem as-is since the event codes match the Linux ones. ABS_X/ABS_Y
values can optionally be scaled to the resolution of a referenced display.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
