The IWDG4 is on the APB3 bus on STM32MP2x SoCs. When the system is
in debug mode, the watchdog should be frozen to prevent it from
expiring and resetting the system during debugging sessions.
Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
Like the H7x series, the MP2x series has a WWDG1 peripheral in the APB3
bus. The MP2 has the same LL function to freeze the watchdog in debug
mode.
Signed-off-by: Luc BEAUFILS <luc.beaufils@savoirfairelinux.com>
EM4 wakeup interrupts are dedicated interrupts tied to specific
pins that enable wakeup from EM4 through reset. Add support
for using these interrupts instead of the regular interrupts when
the GPIO_INT_TRIG_WAKE flag is set.
Since it's not possible to tell what pin is associated with what
EM4WU interrupt at runtime, the driver must store a mapping table
sourced from device tree.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
When the application is executed in external flash, the read operation
cannot be in indirect mode but with memcopy.
Note that writing or erasing the external flash being executed
is not possible during the execution.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Cancelling the alarm needs to reset the callback to NULL, else setting
an alarm subsequently will never work.
chan_id parameter being unused, using ARG_UNUSED() relevantly then.
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Use a temporary variable to store and compare the reference time
instead of calling the time function multiple times,
which may lead to slight mismatches in comparison due to timing drift.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
The current initialization sequence enables the I3C controller before
setting the controller information, which can result in improper setup
and cause the controller to not function as expected.
Fix the initialization order by ensuring that the controller information
is set prior to enabling the controller.
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Balanakakamal V <balanakakamal.v@amd.com>
Commit df0f74d491c851b3e7e970f898c5c2fc3aab5b80 added a shell command to be
able to print out the partitions. However the label property is optional.
Print both the name and label if available.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This refines log message in udc_common.c, including:
1. Add address of allocated net_buf info into udc_ep_buf_alloc log so
that net_buf create/destroy can be easily monitored with calls to
udc_ep_buf_alloc and udc_buf_destroy.
2. Add ep info into udc_ep_buf_alloc log on failure.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Those memories should be disabled by default and enabled
at application level.
Incidentally, fix the way Kconfig symbol is enabled as
we should not parse status of ramcfg, but status of enabled
memory nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The uart_sam0_irg_rx_ready() function always returns true, even if
interrupt is disabled. This happens because the function do not
evaluate if the interrupt is enable of not. This fixes the issue
by adding the missing check.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Implemented siwx91x_set_rts_threshold and siwx91x_get_rts_threshold
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Instead of using mdio bus for getting link state, only get it in the
monitor and save it off for get rate api implementation to use
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Two issues are being simultaneously address in this commit:
Issue 1:
Current issue is that zephyr boot / init is slow because it is blocked
by the phy ksz8081 init doing autonegotiation which can take on the
order of a few seconds.
Fix by now doing autonegotiation in the monitor handler instead of in
the cfg link call. The cfg link call will now only set the ANAR register
and a software flag to let the monitor handler know whether or not to
redo the autonegotiation sequence.
Issue 2:
The ksz8081 phy currently does not link up ever on cold boots on the NXP
RT platforms due to regression on mainline. My understanding of why is
not clear, but I found that re-setting the RMII override bit by the time
the monitor work handler runs with the change to fix the first issue,
makes the link come up.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add tearing effect support for better display synchronization. If
tearing effect is configured in the mipi_dbi device, the display
controller configures its tearing effect register.
Display orientation configuration is updated to also rotated the
direction of the display pixel vertical scanline, such that scan order
matches the display orientation.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Add tearing effect support for better display synchronization. This
allows users to configure an external interrupt on falling/rising edges
of the gpio connected to the display controllers tearing effect pin.
See dt-bindings/mipi_dbi/mipi_dbi.h for details of how this works for
mipi_dbi display interfaces.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
The nrfs_gdpwr driver has a two stage init, which requires tracking
an "expected" state of the power domain, to be applied once the
ipc service needed to control the power domain is ready. This was
tracked with the "off" member of struct domain_data.
So, "off" was initialized to false, but, should actually be
initialized to true, since by default, if nothing needs the power
domain, it should be turned off when ipc service is ready.
To fix this, rename "off" member to "on" and adjust logic.
Additionally, define the correct struct domain_data in the
DOMAIN_DEFINE() macro. Can save 2 bytes. This did not cause any
issue since we typecast it anyway, and its size is large enough.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
No need to toggle reset line manually, use the standard reset API.
This improves code searchability and aids debugging.
Requires f2f496df84 to make sure reset
deassertion is waited for.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Fix compilation issue in test overlay without pll
like hse_8_bypass.overlay and hsi_8.overlay
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Add ethernet support for RA6M4, RA6M5.
Add soc script for generating Renesas Partition Data (RFP file).
Signed-off-by: Ta Minh Nhat <nhat-minh.ta.yn@bp.renesas.com>
Singed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Enable uart_elementary test and fix edge cases where the
configure function did not return the appropriate error code
when given invalid parity or flow control parameters.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Properly return the correct error codes when the watchdog API
is misused. Fail timeout install if WDT_FLAG_RESET_CPU_CORE is
set, a watchdog reset will at a minimum cause a soft reset of
the entire SoC.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Enable the adc_error_cases test on Series 2 devices and change
the return values in the driver for unsupported configurations
to what the test expects.
Ensure that the resolution configuration in the test is valid
such that the invalid buffer test correctly receives -ENOMEM.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a guard clause in flash_esp32_read() to return 0 when the
requested length is zero. This avoids unnecessary operations
and aligns with expected flash API behavior, where reading
zero bytes is treated as a no-op.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
At this moment, DMA for SPI 3-wire half-duplex operation is not supported
by the pio driver. A check was implemented there to prevent user from
enabling DMA, but wasn't bypassed when CONFIG_SPI_RPI_PICO_PIO_DMA is
not enabled at all, under which the `dma_config` structure isn't defined
at all.
Fixed#94897.
Signed-off-by: Terry Geng <terry@terriex.com>
Duty value in the driver is calculated from timer cycles, which
can introduce precision loss when converting from pwm_set() to
pwm_set_cycles(). To avoid truncating values with a fractional
part ≥ 0.5 and further drifting the effective duty, round the
computed duty to the nearest integer.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Currently, if a SV is tracked, we try to store:
flags & BIT(3) -> 0b1000 -> least significant bit 0 is stored.
Same is valid for the is_corrected field.
Use double negation to treat any non-zero value as true.
Signed-off-by: Philémon Jaermann <p.jaermann@gmail.com>
