drivers: serial: pl011: Add support for Ambiq Apollo510 SoC UART
Added more clock sources for Apollo510 support Signed-off-by: Hao Luo <hluo@ambiq.com>
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7090605026
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1e8fb26b67
3 changed files with 12 additions and 1 deletions
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@ -38,7 +38,7 @@
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#include "uart_pl011_ambiq.h"
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#endif
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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#if defined(CONFIG_SOC_SERIES_APOLLO3X) || defined(CONFIG_SOC_SERIES_APOLLO5X)
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#define PM_INST_GET(n) PM_DEVICE_DT_INST_GET(n)
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#else
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#define PM_INST_GET(n) NULL
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@ -37,6 +37,16 @@ static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk)
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case 24000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_24MHZ;
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break;
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#if !defined(CONFIG_SOC_SERIES_APOLLO3X)
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case 48000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_48MHZ;
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break;
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#if !defined(CONFIG_SOC_SERIES_APOLLO4X)
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case AM_HAL_UART_PLLCLK_FREQ:
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clksel = PL011_CR_AMBIQ_CLKSEL_PLL;
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break;
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#endif
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#endif
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default:
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return -EINVAL;
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}
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@ -114,6 +114,7 @@ volatile struct pl011_regs *get_uart(const struct device *dev)
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#define PL011_CR_AMBIQ_CLKSEL_6MHZ 3
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#define PL011_CR_AMBIQ_CLKSEL_3MHZ 4
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#define PL011_CR_AMBIQ_CLKSEL_48MHZ 5
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#define PL011_CR_AMBIQ_CLKSEL_PLL 6
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/* PL011 Interrupt Fifo Level Select Register */
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#define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3)
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