remove unneeded soft irq, as disabeled irqs
will still be registered, but just not propagated
to the cpu until it is enabled again.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
I manually checked the errata sheets for all STM32Hxx/STM32Uxx parts to
confirm the defect's presence or absence. It appears to have been resolved
in silicon on newer parts (e.g., STM32U3xx family), so hopefully this test
will not need grow further (knock on wood).
Co-authored-by: Nicolas Zuluaga <nicolas.zuluaga@rbr-global.com>
Signed-off-by: Samuel Coleman <samuel.coleman@rbr-global.com>
Update ethosu_flush_dcache() and ethosu_invalidate_dcache() to accept
base_addr and base_addr_size arrays, with num_base_addr as the element
count, as required by the new Ethos-U driver. Add (uintptr_t) casts to
support 32-bit targets.
Signed-off-by: Johan Alfvén <johan.alfven@arm.com>
Some devices supported by this driver do not have a write-block-size
of 1 such as the mt35xu01gbba. This value is assigned in the dts and can
be used instead.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Counter RTC driver is written using the counter API as a
target instead of a hardware. It can adapt to all RTC
device without broken-down time register but with counter.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The ws2812_spi driver supports both a fast path for 8-bit symbols and
a generic path for other sizes.
This change introduces a devicetree-based, build-time check to
determine if all enabled instances use 8-bit symbols. If so, the
generic path logic is removed from the build.
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420
(semi)planar formats which can be output by the main #1 pipe.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
ISP is part of the pixel pipes hence it doesn't make any sense to
try to call ISP external handlers if the DCMIPP doesn't have pixel
pipes available.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The maximum frequencies for SYSCLK, AHB and APB bus have changed since
the first issue of the datasheet. Setting values according to the up-
to-date datasheet.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Add a UART driver for the VIRTIO console device.
This driver has support for both polling- and interrupt-based i/o,
as well as interacting with up to 32 console ports (disabled by
default). Based on the Xen HVC driver.
Tested with the console subsystem sample programs. Aside from
enabling CONFIG_PCIE, setting CONFIG_HEAP_MEM_POOL_SIZE to a
high enough value (for example 100000) is necessary -- as is done
in the virtiofs sample.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
This fixes:
* if-statements that check whether a given bit lies within
specification-defined ranges
* a behavior in virtio_pci.c -- where it would read feature bits
from the device and write them back whenever the user tried to
set their own -- which led to bugs
* struct virtio_pci_common_cfg, adding two new fields, bringing
it in line with the specification; the entire struct definition
was reformatted as following the existing style would trigger
warnings
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Use DIV_ROUND_UP to ensure listen_interval is rounded up instead of
being truncated during division by the beacon interval.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
In the Japan regulatory domain, channel 14 is restricted to
802.11b/g operation and does not support HT (802.11n) capabilities.
Disable HT capabilities when operating on channel 14 in AP mode.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
Fix stm32 XSPI driver to restore the bus command concurrent access
protection that was mistakenly removed on memory mapping operation
by commit e5620e07c9 ("drivers: flash: stm32 xspi flash read with
memcopy when executing").
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
- Add ``R_BSP_SecondaryCoreStart`` for the primary core to start
the secondary core
- Disable ``clock_init`` for the secondary core
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add support for clock subsystem configuration and pinctrl in the
DesignWare I3C driver to enable proper clock control and pin
management on platforms that require them.
Changes include:
- Add clock_subsys field to dw_i3c_config structure.
- Update clock_control_get_rate() and clock_control_on() calls to use
the configured clock subsystem instead of NULL.
- Use COND_CODE_1 with DT_INST_PHA_HAS_CELL to conditionally extract
clock subsystem ID from devicetree, providing backward compatibility
for platforms without clkid cell.
- Include pinctrl-device.yaml in devicetree binding to enable pinctrl
support for platforms that need pin configuration.
- Gracefully fallback to NULL behavior when clkid is not specified.
This follows the same pattern used by other I3C drivers (mcux, renesas_ra)
and enables proper clock management for SoCs that require clock subsystem
identifiers while maintaining compatibility with existing devicetree
configurations.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
The I2C target implementation for i2c_dw does not follow the
zephyr target specification. The following three issues are corrected:
1) The read_requested CB is called on every byte of the transaction
- it must be called only on the first byte of the transaction
2) The read_processed CB is called on every byte of the transaction
- it must be called only on bytes following the first byte
3) Bytes returned in the data ptr param of read_processed are not
sent to the controller
-These bytes must be sent to the controller
Signed-off-by: James Growden <jgrowden@tenstorrent.com>
This is a follow-up to commit cafa288197.
Bit masks should use the bitwise OR operator, not the logical one...
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The fast wake feature in the MSPM0 GPIO peripheral allows the GPIO module
to stay in a low-power state and detect interrupt events on the device pins
without requiring a high-speed clock. This allows the device to support
fast wakeup from low-power modes, such as STOP and STANDBY, on any GPIO
pin.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Extend vpr_launcher and device tree bindings to support configuring
the DMA secure attribute.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
* Changes driver naming to reflect hardware IP being used (TCPWM)
instead of referencing cat1. Cat1 is an internal infineon
reference which has little meaning to users and is being phased
phased out.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
flush pending irq before enableing the irq.
In the litex soc, if an irq is not enabled, it will
it can still be registered and will be pending
if it occurs, it will just not be send to the cpu
until the irq is enabled.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
When Octal IO mode is to be used with DDR in mx25u family chips,
bit 1 instead of 0 must be set in the Configuration Register 2 at
address 0.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for supplying power to the flash chip by activation of
a GPIO specified through the "supply-gpios" property. Implementation
of gpio_reset() is also slightly modified so that it is consistent
with soft_reset() and the new power_supply() and so that all these
functions can use a common routine that performs a reset recovery
delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Using a GPIO reset for a flash chip that has a dual function pin
(RESET# or SIO3) and is to be used in Quad mode is rather a bad idea
and so is clearing of the Quad Enable bit at every initialization
of the flash driver, since this bit is usually non-volatile, so such
operation means unnecessary wearing of the flash chip. Soft Reset
should be use instead in such case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add implementation of the most common Soft Reset routine (sequence of
reset enable instruction 0x66 and reset instruction 0x99).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Complete implementation of quad_enable_set() by adding support for all
possible Quad Enable Requirements (QER) as specified by the SFDP JEDEC
standard (JESD216). Add also corresponding octal_enable_set() to handle
Octal Enable Requirements.
Also remove initial waiting from mxicy_mx25r_post_switch_mode() which
became unneeded, as now such waiting is done in cmd_wrsr() which is
called at the end of quad_enable_set().
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Use standard operation codes and parameters from SFDP for handling
the used flash commands (allow to override some of them through dts
with the `read-command`, `write-command`, and `rx-dummy` properties)
- Use all available erase types as specified by SFDP
- Allow using all IO modes
- Add support for switching to 4-byte addressing mode
- Use common functions for reading and writing of status registers
and for enabling write operations
- Switch IO mode (between the target one and Single IO) in a common
function that performs transfers and do it only when required for
a given command
- Make checking of JEDEC ID at initialization optional
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Get parameters for used flash commands and requirements for enabling
Quad and Octal modes from dts uint8-arrays containing data read from
SFDP tables for particular flash chips.
Also introduce `pre_init` quirk that allows alteration of the above
parameters or complementation of them in a specific way for particular
flash chip families.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Define a video device for each pipe instead for the main dcmipp device
since the pipe is the device that communicates with application
(zephyr,camera chosen node), not the dcmipp device.
This helps to enable camera controls as well.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The pipe nodes are not video interfaces. Describe them as normal child
nodes instead of using port/endpoint.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The missing variable "config" in phy_mc_ksz8081_cfg_link() maybe
used by the macro "USING_INTERRUPT_GPIO", add the variable to avoid
compiling errors.
fixes: #95492
Signed-off-by: Tony Han <tony.han@microchip.com>
Asynchronously release the device after a small delay to minimise power
state transitions under multiple sequential API calls (e.g. NVS).
Signed-off-by: Jordan Yates <jordan@embeint.com>
