Provide proper adaptions as bootloader ROM offset, flash load
offset and dts definitions for the nRF54H20 iron board to make it
ready for the MCUBoot bootloader.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
In the default configuration, cv32a6 does not have an FPU and does not
implement RISC-V's F and D extensions.
Hence, the FPU flags should not be added.
In the future, a second SoC for cv32a6 systems with FPU can be added.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The original commit uses the incorrect value 42 for
CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs,
which is the total number of IRQs in the system.
This commit corrects this to 30, the number of IRQs for the PLIC.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit adds an option to verify weather the host has read the value
after the wire 3-0 bits have been updated.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
- 196kB
- 256kB
- 320kB
Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x hardware use specific memory areas to store descriptors
for DMA requests. These areas are tightly coupled between the CPU and
the hardware. This helps in reducing the wait cycles.
Until now these addresses was also hard coded in the DT and in the
linker script. This patch leverage the zephyr,memory-region driver to
centralize the information in the DT.
Then, with this new implementation, the memory mapping is easier to
understand for the reader.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The npcx4 SoC only uses 86 NVIC IRQ numbers.
This commit updates the number from 128 to 86 to reduce the memory
usage.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Since the necessary register values are now pre-computed and
stored in the memory domain struct, we can use them directly
in various assembly locations, thus replacing the function
call to xtensa_swap_update_page_tables().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP as it is
remnant from early MMU enabling work which is not needed as
the page table code is different from early version where
the PTEVADDR would be the same for all memory domains.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch adds an header file which contains helper macros.
These macros can be used to access some device tree properties.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The samples/subsys/llext/shell_loader test fails when running as a
twister test on the stm32mp135f_dk/stm32mp135fxx platform, with the
following error:
soc/st/stm32/stm32mp13x/soc.c:46:36:
error: array type has incomplete element type 'struct arm_mmu_region'
46 | static const struct arm_mmu_region mmu_regions[] = {
This commit adds the missing arm_mmu.h include to fix the build issue.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Remove sleeptimer as default soc timer and it should be only
used as soc timer if PM is enabled.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add initial support for Renesas RZ/G2LC (r9a07g044c22gbg), a 361-pin
package variant of RZ/G2L
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
- AM6232 is a dual core variant of AM6234 with everything being smae.
- Used in the first batch of PocketBeagle 2
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Microchip MEC was configuring the kernel timer tick rate at the
board level instead of the SoC level. We unify all this by moving
the Kconfig logic out of the board level into each mec chip.
We also derive SYS_CLOCK_HW_TICKS_PER_SEC from the device tree
node enabled for the kernel timer: Microchip's 32 KHz RTOT timer
or Cortex-M4 SYSTICK. The soc kconfig rules are loading all mec
subdirectories for every build causing warnings when building
new socs with this change. We made the changes for all the mec chips.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Previously, the RAM code size was limited to 1K, causing issues when the
code exceeded this limit. This update modifies the implementation to
support RAM code sizes up to 4K
test: zephyrproject/zephyr/tests/drivers/flash/common --> pass
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add nrf_cache_power_up and nrf_cache_power_down functions. In case of
s2ram power up cache as early as possible, before restoring ARM core
registers. It improves restore time from 180 us to 33 us.
As a minor optimization nrf_memconf_ramblock_control_mask_enable_set is
used which allows to control ram blocks for icache and dcache in a
single register write.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This renames the STM32_PWR_WKUP_PIN_SRC_x symbols to better match
their meaning. It also adds a new symbol (STM32_PWR_WKUP_PIN_NOT_MUXED)
for SoCs without wake-up mux support.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
Add an entry for the RAM region assigned to soft peripherals that will
disable caching for that region. Without this, communication with the
FLPR coprocessor cannot be performed correctly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Some files should be separated from the common folder to
each soc folder for future expansion of the chip.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
