This maps to Zephyr power state Standby. In this power
state the OS Timer cannot be used as a wakeup source as
it will be powered off. Hence the counter is enabled
and RTC is used to keep track of system ticks and wakeup
the system.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since the clock source when running in PM mode 3 is the
slower 1KHx clock, we adjust the SYS_CLOCK_TICKS_PER_SEC
value to get better accuracy.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This clock is used for certain peripherals such
as RTC.
On certain RW612 boards such as rd_rw612_bga, XTAL32K
and ENET share pins. Add code to check if ENET and
XTAL32 are enabled at the same time.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add calls to sys_trace_idle and sys_trace_idle_exit in nrf54h specific
idle states to allow measuring CPU load on nrf54h20 when power
management is enabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
These socs were missing a config line to disable SYSTICK if the LPTMR is
configured for the system timer, similar to how other SOCs do this for
alternative system timers than systick.
This fixes build errors in the case where that lptmr kconfig is enabled.
Also, the LPTMR kconfig should be default no because it is a secondary
option for the system timer, being lower resolution than systick. This
also resolves build errors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Migrate LINKLAYER_PLAT_EnableIRQ and LINKLAYER_PLAT_DisableIRQ
from linklayer_plat.c (hal/stm32 module).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Migrate LINKLAYER_PLAT_EnableRadioIT and LINKLAYER_PLAT_DisableRadioIT
from linklayer_plat.c (hal/stm32 module) and adapt it using irq
Zephyr APIs.
Correct casting of irq type between using NVIC APIs or irq Zephyr APIs
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Increase the link layer thread priority to be more than the BLE CTRL
thread and more than the Zephyr BLE stack threads.
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
What is the change?
This commit adds support for Armv8.1-M MPU architecture's PXN attribute.
This includes support for configuring MPU regions with PXN via
custom mpu_config, devicetree and static mpu_config.
The existing MPU region attribute macros are updated to retain existing
behaviour with this change with an addition of REGION_RAM_ATTR_PXN to be
used if one needs to configure a RAM region with PXN MPU attribute.
Why do we need this change?
Armv8.1-M architecture introduced a new MPU region attribute called
Privilege eXecute Never (PXN).
If an MPU region is configured with the PXN attribute set and if the,
processor attempts to execute code in this region while at
privileged level, a Memory Management Fault exception is triggered.
This ensures that specific tasks are executed only in unprivileged mode
and helps in preventing secure privilege escalation attacks.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add a warning in the build system if both `CONFIG_PM` and
`STM32_ENABLE_DEBUG_SLEEP_STOP` are enabled at the same time. The first
is likely only enabled if the SoC is intended to be driven into low
power states to save power, while the later prevents the SoC from being
as low power as it can be.
Signed-off-by: Jordan Yates <jordan@embeint.com>
It was detected by test_sw_isr_irq_parent_table_idx in arch.interrupt:
ASSERTION FAIL [table_idx < (186 - 0)]
@ WEST_TOPDIR/zephyr/arch/common/multilevel_irq.c:91
table_idx(186) < IRQ_TABLE_SIZE(186)
NUM_IRQS was previously set to the same value as MAX_IRQ_PER_AGGREGATOR
and it didn't take into account the number of 1st level interrupts
specified by 2ND_LVL_ISR_TBL_OFFSET. In the generated __sw_isr_table,
Level 2 interrupts start at the offset specified by 2ND_LVL_ISR_TBL_OFFSET.
For PolarFire SoC, upper interrupt sources for PLIC correspond to
Bus Error Unit and Fabric Interface. They are currently not used by
platforms in Zephyr, so the previous value of NUM_IRQS hasn't caused
issues for regular applications.
As it doesn't look like an explicit memory optimization, increase NUM_IRQS
to allow kernel interrupt tests to pass.
Note:
2ND_LVL_ISR_TBL_OFFSET=13 and NUM_IRQS=199 don't include additional
48 Local Interrupts supported by cores. In total, there are
64 bits in Machine Interrupt Pending Register (mip)
which can be used to configure 1st level interrupts.
As a further extension to the platform, values could be extended to
2ND_LVL_ISR_TBL_OFFSET=64 and NUM_IRQS=250. This commit increases
NUM_IRQS by a minimal value required to pass kernel interrupt tests.
Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Added configuration for new audio PLL service.
Pull in new service implementation in new hal nordic.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Enabled west flash and west erase for nRF54L20 PDK FLPR core.
Added missing reset qualifier for nRF54L20 and nRF54L09.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
The first two partitions in padconfig mmr regions need to be unlocked for
the pinctrl driver to be able to write. However, the base addresses for the
the registers can be different across SoCs and domains. Besides, currently
this is only done for M4 and that too not in the local (M4's) view.
This patch introduces a file specifying all ctrl partition base addresses
using ifdef directives for different SoCs and variants, and unlocking them
before the kernel and drivers initialize.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
There is a configuration of the DCDC in the clock_init for the RT10xx.
The RT11xx has a kconfig flag ADJUST_DCDC to enable or disable DCDC
adjust code. This flag is now also used for the RT10xx to be able to
enable or disable the DCDC adjust code.
Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
In the case where more than a full tick was unannounced when
sys_clock_set_timeout() was called, the timer driver would
subtract it from the next timeout. However, this is already
done by the caller through the elapsed() function in timeout.c,
leading to the timer interrupt firing too early.
With this fix, SYS_CLOCK_TICKS_PER_SEC can be increased to the
full speed of the low frequency timer. The underlying sleeptimer
API must be called with a timeout of at least 1, and will if needed
increase the value to the minimum value required by the hardware.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added Kconfig options to allow use of TWIM frequency
workaround in NRFX for nRF52 and nRF53.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
In spi loopback test, high bandrate is 16Mbps while some source of lpspi
are too low to support this bandrate. According the reference mannual,
to support 16Mbps, Input frequency at least should be 2*16MHz.
Update LPSPI input freq to maximum to get more accurate band rate
because band rate must be divisible by input freq.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
List NEORV32 v1.11.2 as the currently supported version. No changes to the
in-tree drivers needed for the changes between v1.11.1 and v1.11.2.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
We disable power management by removing select HAS_PM. At this time
these new SoC do not have any power management code. With HAS_PM
selected the zephyr test runner will choose PM tests which fail to
build. PM support will be enabled in the future once we decide
which of the many Zephyr PM implementations we will support.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME depends on
CONFIG_SYS_CLOCK_EXISTS, so CONFIG_SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME
needs to depend on CONFIG_SYS_CLOCK_EXISTS for selecting it.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The current default RAT configuration puts the first 512MB of
address space on top of the first 512MB of DRAM. This DRAM
can include the carveout region assigned for IPC with the
host core, for instance the M4 on AM62 uses 0x9cc00000.
Split this first translation from 0x80000000 to 0x60000000 and
0xc0000000. Shrink the 0x40000000 translation and move down
to 0x70000000. This provides the same system IP coverage without
blocking access to the first 512MB of DRAM.
While here, fix typo with leading 0 for a couple BASE_ADDR
translations, no functional change.
Signed-off-by: Andrew Davis <afd@ti.com>
This is the initial commit to support PINCTRL driver for Renesas RZ/T2L
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
On ZynqMP, the RPU Cortex-R5 cores come up by default without
instruction and data caches enabled. Enable them as part of
soc_early_init_hook when CONFIG_CACHE_MANAGEMENT is enabled.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This patch will set MMU permissions for .cold* sections
Fixes cold section execution if MMU is enabled
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Improve naming of the scheduler and call it what it is: simple. Using
'dumb' for the default scheduler algorithm in Zephyr is a bad idea.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A few option defaults that were so far defined in the board _defconfig
files are actually entirely SoC family (nRF54L) dependant, so it makes
much more sense to have them defined at the SoC family level in order
for all boards based on these SoCs to automatically inherit them.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Currently, coex application is enable the mbedtls and PAS feature,
this causes BT_LONG_WQ thread to use more stack size.
Signed-off-by: Author You <author.you@nxp.com>
The part numbers for MCXC141VLH and MCXC142VFM
have all been set to MCXC141VFM, which lead to
build errors.
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
This is the initial commit to support pinctrl driver for Renesas RZ/N2L
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
