Replace incorrect call to memc_flexram_dt_partition() with
flexram_dt_partition() to resolve build error on
IMXRT10xx and IMXRT11xx.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Configures AHBSC MASTER_SEC_LEVEL register for the cpu1 before cpu1 is
enabled. By default, this gives CPU1 secure and privileged access to
the rest of the SOC, same as CPU0.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Use `defaut y if` instead of `depends on` as the related Kconfig
should be user configurable even when standby mode is not used.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The buf_in_nocache function is to be used by various device drivers
to check if buffer is in noncacheable region.
The cacheable DMA buffer shall be put into section .ambiq_dma_buff
due to certain restrictions of the SoC.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
There is no need for kernel/internal/smp.h as SOF does not call
z_sched_ipi(). Actually... git log over there has no mention of
z_sched_ipi() anywhere, just arch_sched_ipi().
And include <ksched.h> for source using z_sched_ipi() since
they are using scheduling functions, and would be the correct
file to include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This platform was previously using a default sys_arch_reboot
implementation which did nothing. Add an implementation which uses the
CRL_APB_RESET_CTRL register to initiate a soft reset (SRST) of the
device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
For simplicity/consistency with many other soc families, rename the
bouffalolab_bflb soc family to the simpler bflb.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Moved to: include/zephyr/drivers/misc/flexram/memc_nxp_flexram.h
This change makes it so that the .h file does not need to be pulled in
using the CMakeLists.txt file, and can be included like other public
includes.
Removes drivers/memc/memc_nxp_flexram.h
Add memc_nxp_flexram.h to include/zephyr/drivers/misc/flexram
Modify drivers/memc/memc_nxp_flexram.c to use the new include path.
Modifies the mimxrt1170 magic_addr sample to include the driver using
the new include path.
Modify the soc file: soc/nxp/imxrt/imxrt11xx/soc.c to use the new path.
Add relevant information to migration-guide-4.2.rst.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
Disable GPD for MCUBoot build, as it cannot be
reinitialized later in application (SDFW does not
support reinitialization).
Also, remove the GPD disabling from the mcumgr sample
for nRF54H20 iron board app - it was the reinitialization
that caused problems.
Signed-off-by: Michal Kozikowski <michal.kozikowski@nordicsemi.no>
The symbol SRAM_VECTOR_TABLE is not used in the adi/max32 soc. Removed
it in order to clean up the Kconfig file and avoid confusion with the
upcoming new definition of SRAM_VECTOR_TABLE symbol. (PR #87468)
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Remove the sanity check between Cube HAL SMPS symbol and Kconfig SMPS
configuration.
SMPS is available on all STM32H7R/S SoC, so misalignment isn't possible.
Additionally, point to the hal commit which revert the fix which was done
on hal_stm32 to add this symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Introduces config file entries for STM32F401XD variants. The
STM32F401XD family is related to the STM32F401XE family but with a
reduced flash memory.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
lld will produce warnings for the symtab, strtab, and shstrtab sections
if --orphan-handling=warn is specified and there are no matching rules
in the linker script for these sections. Handle these sections when
building with lld to prevent the warnings.
This is exactly the same as commit
c420733c33, but for the AE350 linker
script.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
As well described in a previous PR [1], the GNU ld and LLVM lld linkers
treat the location counter (`.`) differently. lld always inteprets the
location counter as an absolute address whereas ld interprets it as an
offset from the start of the current object.
The NXP boot header linker script files use `.` assignment to specify an
offset within the rom_start region (ld-style). This causes lld to error
out since it interprets this as the location counter moving backwards.
To fix this, re-use the idea from the previous PR [1]:
replace `. = FOO` with `. += FOO - (. - __rom_start_address)`
This sets the location counter in a way that works with both ld and lld.
[1] https://github.com/zephyrproject-rtos/zephyr/pull/58315
Signed-off-by: Kesavan Yogeswaran <hikes@google.com>
Intel Audio DSP ACE needs to use arch_spin_relax() to give
the bus more time to propagate the RCW transactions among
CPUs, and to avoid sending too many requests to the bus
after failing to lock spinlocks. However, the number of
NOPs results in a very big arch_spin_relax() that spans
multiple instruction cache lines, and requires evicting
them just for NOPs. With 5 CPUs, it can span 6 cache
lines (if using nop.n instead of nop). That's a waste of
space and cache. So instead, we do a tight loop instead.
Since the SoC supports zero-overhead loops, this should
have minimal performance impact.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some weird unknown reasons, the simulator really do not
like the cpuhold_* variables to be tightly packed together.
This results in cpuhold_spawned not being updated, and we
will be stuck in the while loop for it to be set.
Workaround this by explicitly aligning these variables on
16 byte boundary. This seems to work for now.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
