Add config and overlay to samples for testing stop/standby modes:
- samples/boards/st/power_mgmt/blinky
- samples/boards/st/power_mgmt/wkup_pins
I've measured consumption for each low-power mode:
- stop (regulator in run mode) ~217 uA
- stop (regulator in low-power mode) ~206 uA
- standby mode ~3.5 uA
Low-power mode wakeup timings from the datasheet,
but it barely meets these in reality:
- stop (regulator in run mode) 3.6 us
- stop (regulator in low-power mode) 5.4 us
- standby 50 us
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
The ns16550 UART driver has multiple variant Kconfig options. To
successfully run the uart_basic_api test, the correct variant must be
selected. This commit adds the missing Kconfig option.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Add support for the RPU, real-time processing unit on Versal Gen 2 SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versal2.dtsi contains common peripherals integrated into Versal Gen 2
SoC, and versal2_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
This supports nuvoton numaker m55m1x series soc. Besides, it also
has relevant modifications, including:
1. Fix failure to enable HICR48M, which is to clock usbd and phy
2. Support HWINFO for USB device serial number
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The image_def header shall not be added to apps that are booted by a
bootloader, e.g. mcuboot. Added proper handling for UF2 by hanan619.
Signed-off-by: Manuel Aebischer <manuel.aebischer@belden.com>
The first 1 KB is reserved for the NWP (Network Coprocessor). This
change also resolves the null pointer error issue, as a .data or a
_ramfunc might get the address 0x0.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Introduced WIFI_SILABS_SIWX91X_LIMIT_PACKET_BUF_PER_STA.
This flag limits packet queues in AP mode.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
The NWP provides Bluetooth, Wi-Fi and crypto services, and must
be initialized before any users of these. Mbed TLS is initialized
at priority level 40 (kernel default priority), ensure that the
NWP is initialized before that.
Make the priority configurable to allow users to tweak the init
sequence.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Fixes the missing Kconfig resource for the siwx91x SoC. This ensures
that soc_early_init_hook function is correctly called for the siwg917
SoC during initialization.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Code responsible for internal capacitor values containted
leftover workarounds in the calculations after PS update.
Removed redundant conversions and cleaned up both code
and comments to align both LFXO and HFXO calculation.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Some drivers need header file soc.h, according to Zephyr SoC Porting Guide
soc.h must be provided for each SoC, so created an empty one.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.
Signed-off-by: Camille BAUD <mail@massdriver.space>
MDK 8.69.1 included in nrfx 3.10 already applies the workaround,
so there is no need to do it again.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
When PM2 is enabled, it will disable many of the devices, so need to
enable PM policy constraints for this mode also so that device drivers
can work.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Compared to the CH32V003, the CH32V00x series is an evolution that
uses a different microarchitecture (V2C instead of V2A) and different
pinctrl mappings.
Fork the current qingke_v2a and use the new proposed naming convention.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Move creation of last section id from ld linker script LONG() usage to
C code with last section attribute.
The use of `LONG()` works correctly with ld but lld emits a warning
because .last_section section is not allocated as there are no matching
input sections and discards the `LONG()` call, meaning the last section
identifier will not be present in the flash.
> ld.lld: warning: ignoring memory region assignment for
> non-allocatable section '.last_section'
Placing the last section id in `.last_section` in C code makes lld
allocate the memory for the id and thereby create the output section
with the correct output.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The SOC defconfig overrides CONFIG_KERNEL_ENTRY from the default of
__start to _vector_table. This is undesirable for cores such as M4 where
the _vector_table symbol has just raw addresses and no instructions. The
change was done to make sure Zephyr images can be loaded via remoteproc in
which case the entrypoint needs to be 64 byte aligned. To fix this, use
_vector_table as the ELF entrypoint only for R5 cores.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
esp32-mp.c calls z_sched_ipi() so it needs to include ksched.h,
as it is no longer included via kernel.h after removal of
kernel/internal/smp.h.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Port the nordicsemi_nrf53_init to use soc_early_init_hook instead of
SYS_INIT as SYS_INIT is legacy.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
